Dsign of a Low Nois Amplifir in 0.8µm SiG BiCMOS Tchnology Astract Wi Wang, Fng Hu, Xiaoyuan Bao, Li Chn, Mngjia Huang Chongqing Univrsity of Posts and Tlcommunications, Chongqing 400065, China A 60GHz LNA with a thr stag singl ndd is dsignd in 0.8µm SiG BiCMOS tchnology. Th LC rsonanc is usd in th intr stag matching to rduc th transmission loss,y adding a paralll capacitor twn two pols to rduc th ffct of parasitic.from th simulation rsults,w can draw a conclusion that:s2 and th Nois Figur ar achivd 2.6dB and 5.5dB rspctivly, in oprating frquncy of 60 GHz, oth input and output rturn losss S and S22 ar low -0dB from 55GHz to 65 GHz,th pow consumption only 2.8mw with supply voltag of 3.3V. Kywords 0.8µm SiG BiCMOS, Low Powr Consumption, 60GHz LNA.. Introduction A rcivr in mm-wav frquncy, low nois amplifir (LNA) is an important part, it has a dcisiv influnc on th snsitivity of th rcivr []. Th gnral rquirmnts of low nois amplifir, not only hav a vry low Nois Figur (NF), ut also to provid high nough gain to supprss th nois of th rar stag, th input impdanc should matchd to 50Ω, also Th linarity of th low nois amplifir nd to mt crtain rquirmnts. In a varity of low nois amplifir in BiCMOS tchnology, cascod structur is widly usd caus th structur can wll mt rquirmnts in most cass. Th widsprad us of moil dvics proposd mor stringnt rstrictions on th powr circuit, low powr dsign has com a trnd. For xampl,low nois amplifir, mixr, powr filtr and commrcial GPS wr intgratd in a rcivr chip,th powr is gnrally no mor than 40 mw. In low powr constraints, dsign low nois amplifir with mthod of th traditional cascod structur has facd som difficultis, nd to put forward a nw mthod to solv th prolm. On powr constraints, Rfrnc [2] introducs a nois optimization mthod, ut this optimization mthod mad th minimum Nois Figur is oviously highr than that of nois matching can achiv. Through thortical analysis, y adding a paralll capacitor, th rsults of Rfrnc [3] shown that: in low powr conditions, th circuit nois can rducd significantly, ut no spcific dsign mthod is givn.on th asis of rfrnc [3], rfrnc [4] givs a concrt dsign mthod, howvr, aftr th introduction of paralll capacitor, th chang of th circuit prformanc is not clar. In this papr, asd on th input impdanc matching,y adding a paralll capacitor achiv low powr, and th influnc of th shunt capacitanc on various paramtrs of th circuit is analyzd in dtail.th simulation was carrid out y using Cadnc softwar. 2. 60GHz LNA Circuit Svral main faturs of th dsign 60GHz low nois amplifir ar as follows: () Th input impdanc of low nois amplifir must matchd into 50Ω, in ordr to match th 50Ω charactristic impdanc of th antnna; (2) Th Nois Figur of low nois amplifir should as small as possil; (3) Th gain of th low nois amplifir should larg nough (undr th conditions of th systm linarity) to supprss th nois of th rar stag; (4) Th powr consumption of low nois amplifir should small as wll. In rcnt yars, th dsign of 60GHz low nois amplifir mainly has two kinds circuit structur, on is th singl ndd structur, th othr is th diffrntial structur.60ghz low nois amplifir ndd to 27
provid a crtain gain to supprss th nois of th rar stag, in th mm-wav frquncy, with th incras of frquncy, th gain Rapid attnuation, so, th gain of a singl structur is vry small. Rfrnc[6] Simulation of th rlationship twn th frquncy and th maximum availal gain(mag), th rsults shown that th masurd MAG of 90nm NMOSFET is 7.8dB, shown in Fig.. Evn for a cascod configuration, th MAG is only nar 0dB du to th low impdanc on th intr-stag nod. What is mor, considring th loss du to th impdanc matching ntwork, thr is vn lss gain w can gt from a singl stag LNA. Thrfor, multi-stag topology is ndd for LNA to raliz a rasonal gain for ral application. Fig. Rlationship twn th frquncy and th maximum availal gain Cascod architctur is widly usd for its high gain, good isolation twn input and output, making th dsign mor roust and simplifying matching ntwork. Howvr, at mm-wav frquncy, du to th low gain of th common-mittr (CE) transistor and high nois of th common-ac (CB) transistor, th nois contriution of th CB transistor incrass, which maks cascad topology poor nois prformanc for 60GHz LNA. Morovr, th gain of cascod architctur, although a fw db highr ovr CE topology, dcrass havily du to th low impdanc on th intr-stag nod[0], which maks it vn lss attractiv as th first stag for 60GHz LNA. Tak all condition into considration, w choos CE as th first stag of th 60GHz LNA,CE transistor with mittr dgnration topology instad of cascod topology as th first stag, not only simplifying matching ntwork, also dcrasing th total nois for 60GHz LNA. CE transistor with mittr dgnration topology is shown in Fig.2, and transistor s small signal modl shown in Fig.3. Fig.2 CE with mittr dgnration Fig.3 Small signal modl of CE Th input impdanc Z in can calculatd from th quation: Z in jw(l L ) r 28 jwc gm L c St th appropriat valu of inductanc L and L to match th input to 50Ω. But in mm-wav frquncy, if th valu of L is too larg, th nois prformanc will trril. By adding a capacitor C p can Improving th total capacitor twn th as and th mittr, a capacitor C p togthr with th
capacitor C complt nois matching function and incras th C p has no ffct on powr consumption. Th input impdanc Z in will modifid as: Z in jw(l L ) r jw(c c p g ) (c By adding capacitor C p, total capacitor of th input stag whr gt largr,at th frquncy of 60GHz, Rsonant frquncy w 2 =/LC. So th valu of inductanc L coms smallr [5]. Multi-stag topology is usd for LNA to raliz a rasonal gain. According to th total Nois Figur for multi-stags [6]: NF total NF2 NFn NF G G G G Whr NF i Fand G i is th Nois Figur and th gain of i stag rspctivly. From th quation, w can draw a conliusion that th Nois Figur of first stag dtrmins th nois prformanc of th whol systm. As spcifid aov, CE with mittr dgnration transistors is chosn for th first stags. Cascod stag hav n slctd to incras rvrs isolation and gain. So, th implmntation of th first stag is mainly dtrmind y nois considrations. Th two cascod stag is ndd to incras th ovrall gain of th LNA. Schmatic of th LNA is shown in Fig.4. 2 m (n) L c p ) 3. Simulations and rsults Fig.4 Schmatic of th 60GHz LNA Th schmatic of th 60GHz LNA has n implmntd in 0.8µm SiG BiCMOS tchnology. Th layout of 60GHz LNA is shown in Fig.5. Fig.5 Th layout of 60GHz LNA 29
Mak us of Cadnc Spctr RF to Simulation. During th simulatd procss th supply voltag is 3.3V. Th simulation Nois Figur, Gain and input/output rturn loss as shown low. Fig.6 Simulation of Nois Figur Fig.7 Simulation of gain By adding capacitor C p, total capacitor of th input stag whr gt largr, inductanc L coms smallr, choosing optimum nois matching and slction ias dtrmind y nois considrations in first stag, all of this mak th Nois Figur achivs low targt. From th pictur in Fig.6, w can s that: in frquncy of 60GHz, th simulation Nois Figur is 5.5dB. Th simulation of gain is dpictd in Fig.7. Th two cascod stag was usd to incras gain of th 60GHz LNA. In ordr to achivs high gain, scond stag was ia highr than input stag. Th simulation gain is 2.6dB at th cntr frquncy of 60GHz. Fig.8 Simulation of S and S22 Th rsults of th rturn losss for input and output show in Fig.8. Th simulation S is -7.5dB at 60GHz and low -0dB from 55GHz-65GHz. Its covrs mor than 0GHz and. Th simulatd S 22 is -20dB at 60GHz. Th rsults shown good input and output matching in this work. Fig.9 Simulatd of P -db Simulatd db comprssion point P-dB at 60GHz ar plottd in Fig.9. Th input rfrrd comprssion point P-dB is -23.94, th rsults indicatd that th linarity of this work is ttr 30
4. Conclusion A low powr thr-stag singl ndd 60GHz LNA was dsignd in 0.8µm SiG BiCMOS tchnology. By adding a shunt capacitanc C p twn as and mittr nod of CE transistor, th Nois Figur wr significantly rducd. In th 60GHz mm-wav frquncy, inductors L and L wr usd for input impdanc matching and without introducing additional nois. From th simulation rsults,s2 and th Nois Figur ar achivd 2.6dB and 5.5dB rspctivly, input and output rturn loss S and S 22, lowr than -0dB from 55GHz to 65GHz, th powr consumption only 2.8mW with th voltag of 3.3V. Rfrncs [] A. Natarajan, S.K. Rynolds, M.D. Tsai, t al. A Fully Intgratd 6-Elmnt Phasd-Array Rcivr in SiG BiCMOS for 60GHz Communications [J]. IEEE Journal of Solid-Stat Circuits, 20, 46(5):059-075. [2] T. H. L. Th dsign of CMOS radio-frquncy intgratd circuits [M]. Hous of Elctronics Industry, 2002:207-233. [3] P. Andrani, H. Sjöland, t al. Nois optimization of an inductivly dgnratd CMOS low nois amplifir [J]. IEEE Analog & Digital Signal Procssing. 200, 48(9): 835-84. [4] T. K. Nguyn, C. H. Kim, G. J. Ihm, t al. CMOS low-nois amplifir dsign optimization tchniqus[j]. IEEE Microwav Thory & Tchniqus. 2004, 52(5):433-442. [5] P. Andrani, H. Sjöland. Nois optimization of an inductivly dgnratd CMOS low nois amplifir [J]. IEEE Transactions on Circuits & Systms Analog & Digital Signal Procssing, 200, 48(9):835-84. [6] T. Suzuki, Y. Kawano, M. Sato, t al, 60 and 77GHz Powr Amplifirs in Standard 90nm CMOS[C]. IEEE Intrnational Solid-Stat Circuit Confrnc, 2008:562-636. 3