M DW0/DB0 M DW0/DB0 DRAM MODULE

Size: px

Start display at page:

Download "M DW0/DB0 M DW0/DB0 DRAM MODULE"

Ophelia Glenn
5 years ago
Views:

1 & EDO Mode 8M x 32 DRAM SIMM using 4Mx4, 4K/2K Refresh, 5 GENERAL DESCRIPTION The Samsung M (1)0D is a 8Mx32bits Dynamic RAM high density memory module. The Samsung M (1)0D consists of sixteen CMOS 4Mx4bits DRAMs in 24pin SOJ package mounted on a 72pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M (1)0D is a Single Inline Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. PERFORMAE RANGE Speed trac tcac thpc 50 50ns 13ns 90ns 25ns FEATURES Part Identification M D0C(4096 cycles/64ms Ref, SOJ, Solder) M DB0C(4096 cycles/64ms Ref, SOJ, Gold) M D0C(2048 cycles/32ms Ref, SOJ, Solder) M DB0C(2048 cycles/32ms Ref, SOJ, Gold) Extended Data Out before refresh capability only and Hidden refresh capability TTL compatible inputs and outputs Single +5±10% power supply 1st Gen. JEDEC standard PDPin & pinout PCB : Height(1000mil), double sided component 60 60ns 15ns 110ns 30ns PIN CONFIGURATIONS PIN NAMES Pin Symbol Pin Symbol Pin Name Function SS cc A0 A1 A2 A3 A4 A5 A6 A A7 A11 cc A8 A cc PD1 PD2 PD3 PD4 A0 A11 A0 A , PD1 PD4 cc Address Inputs(4K Ref) Address Inputs(2K Ref) Data In/Out Read/rite Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5) Ground No Connection PRESEE DETECT PINS (Optional) Pin 50NS 60NS PD1 PD2 PD3 PD4 * Pin connection changing available SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. * NOTE : A11 is used for only (4K ref.)

2 FUTIONAL BLOCK DIAGRAM U0 2 A0 A11(A10) 4 2 U8 A0 4A11(A10) 1 U1 2 A0 A11(A10) U9 A0 4 A11(A10) 1 U2 2 A0 A11(A10) U10 A0 4 A11(A10) U3 2 A0 A11(A10) U11 A0 4A11(A10) 2 U4 2 A0 A11(A10) U12 A0 4A11(A10) U5 2 A0 A11(A10) U13 A0 4A11(A10) 3 U6 2 A0 A11(A10) U14 A0 4 A11(A10) U7 2 A0 A11(A10) U15 A0 4A11(A10) A0A11(A10) cc.1 or.22uf Capacitor for each DRAM To all DRAMs

3 ABSOLUTE MAXIMUM RATINGS * oltage on any pin relative to SS oltage on CC supply relative to SS Storage Temperature Power Dissipation Short Circuit Output Current Item Symbol Rating Unit IN, OUT CC Tstg * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. Pd IOS 1 to to to RECOMMENDED OPERATING CONDITIONS (oltage referenced to SS, TA = 0 to 70 C) Supply oltage Ground Input High oltage Input Low oltage *1 : CC+2.0/20ns, Pulse width is measured at CC. *2 : 2.0/20ns, Pulse width is measured at SS. Item Symbol Min Typ Max Unit CC SS IH IL * CC+1 *1 0.8 DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) ICC1 : Operating Current * (,, Address ICC2 : Standby Current (===IH) ICC3 : Only Refresh Current * (=IH, ICC4 ICC5 ICC6 : Before Refresh Current * ( and II(L) IO(L) OH OL Symbol Speed ICC Min Max Min Max ICC ICC ICC ICC ICC II(L) IO(L) OH OL : EDO Mode Current * (=IL, Address cycling : thpc=min) : Standby Current (===cc0.2) : Input Leakage Current (Any input 0 IN cc+0.5, all other pins not under test=0 ) : Output Leakage Current(Data Out is disabled, 0 OUT cc) : Output High oltage Level (IOH = 5) : Output Low oltage Level (IOL = 4.2) C Unit ua ua * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while =IL. In ICC4, address can be changed maximum once within one EDO mode cycle, thpc.

4 CAPACITAE (TA = 25 É, CC=5, f = 1MHz) Input capacitance[a0a11(a10)] Input capacitance[] Input capacitance[0, 1] Input capacitance[0 3] Input/Output capacitance[031] Item Symbol Min Max Unit AC CHARACTERISTICS (0 C TA 70 C, CC=5.0±10%. See notes 1,2.) CIN1 CIN2 CIN3 CIN4 C Test condition : ih/il=2.4/0.8, oh/ol=2.0/0.8, Output loading CL=100pF Parameter Symbol Min Max Min Max Random read or write cycle time ns Access time from trac ns 3,4,10 Access time from tcac ns 3,4,5 Access time from column address taa ns 3,10 to output in LowZ tclz 3 3 ns 3 Output buffer turnoff delay from tcez ns 6,11,12 Transition time(rise and fall) tt ns 2 precharge time ns pulse width t 50 10K 60 10K ns hold time trsh ns hold time tcsh ns pulse width t 8 10K 10 10K ns 13 to delay time D ns 4 to column address delay time trad ns 10 to precharge time 5 5 ns Row address setup time tasr 0 0 ns Row address hold time trah ns Column address setup time tasc 0 0 ns Column address hold time tcah 8 10 ns Column address to lead time tral ns Read command setup time S 0 0 ns Read command hold time referenced to H 0 0 ns 8 Read command hold time referenced to trrh 0 0 ns 8 rite command hold time tch ns rite command pulse width tp ns rite command to lead time trl ns rite command to lead time tcl 8 10 ns Datain setup time tds 0 0 ns 9 Datain hold time tdh 8 10 ns 9 Refresh period (4K Ref) tref ms Refresh period (2K Ref) tref ms rite command setup time tcs 0 0 ns 7 setup time(before refresh) tcsr 5 5 ns hold time(before refresh) tchr ns to precharge time C 5 5 ns Unit pf pf pf pf pf Note

5 AC CHARACTERISTICS (0 C TA 70 C, CC=5.0±10%. See notes 1,2.) Test condition : ih/il=2.4/0.8, oh/ol=2.0/0.8, Output loading CL=100pF Parameter Symbol Min Max Min Max Unit Note precharge time (CBR counter test cycle) tcpt ns Access time from precharge tcpa ns 3 Hyper page mode cycle time thpc ns 13 precharge time(hyper page cycle) tcp 8 10 ns pulse width(hyper page cycle) tp K K ns hold time from precharge trhcp ns to precharge time(cbr refresh) trp ns to hold time(cbr refresh) trh ns Output data hold time tdoh 5 5 ns Output buffer turn off delay from trez ns 7,11,12 Output buffer turn off delay from tez ns 7,11 to data delay ted ns pulse width (Hyper Page Cycle) tpe 5 5 ns NOTES An initial pause of 200us is required after powerup followed by any 8 only or before refresh cycles before proper device operation is achieved. IH(min) and IL(max) are reference levels for measuring timing of input signals. Transition times are measured between IH(min) and IL(max) and are assumed to be 5ns for all inputs. Measured with a load equivalent to 2 TTL loads and 100pF. Operation within the D(max) limit insures that trac(max) can be met. D(max) is specified as a reference point only. If D is greater than the specified D(max) limit, then access time is controlled exclusively by tcac. Assumes that D D(max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to OH or OL Either H or trrh must be satisfied for a read cycle. These parameter are referenced to the leading edge in early write cycles and to the leading edge in readwrite cycles. 10. Operation within the trad(max) limit insures that trac(max) can be met. trad(max) is specified as reference point only. If trad is greater than the specified trad(max) limit, then access time is controlled by taa. tcez(max), trez(max), tez(max) and tz(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. If goes to high before high going, the open circuit condtion of the output is achieved by high going. If goes to high before high going, the open circuit condtion of the output is achieved by high going. 13. tasc tcp min 7. tcs is nonrestrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tcs tcs(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle.

6 READ CYCLE IH t IH D tcsh t trsh trad A IH tasr trah tasc RO tcah tral IH S trrh H taa tcez tez tcac OH OL OPEN trac tclz DATAOUT trez

7 RITE CYCLE ( EARLY RITE ) NOTE : DOUT = OPEN IH IH trad D tcsh t trsh t A IH tasr trah tasc RO tcah tral tcl IH tcs tp tch trl IH tds DATAIN tdh

8 HYPER PAGE READ CYCLE IH tp IH trad D tcsh thpc thpc thpc tcp tcp tcp trhcp t t t t A IH tasr RO ADDR trah tasc tcah tasc tcah tasc tcah tasc tcah ADDR trez S H trrh IH tcac tcac tcpa tcac taa taa tcpa taa tcpa taa OH OL trac tcac tdoh ALID DATAOUT tdoh ALID DATAOUT tdoh ALID DATAOUT ALID DATAOUT tclz

9 HYPER PAGE RITE CYCLE ( EARLY RITE ) NOTE : DOUT = OPEN IH tp trhcp IH A IH tasr RO ADDR. trad D tcsh t trah tasc tcah tasc tcah tasc tcah thpc tcp t thpc tcp trsh t tcs tch tcs tch tcs tch IH tp tp tp tcl tcl tcl trl IH tds ALID DATAIN tdh tds tdh tds tdh ALID DATAIN ALID DATAIN

10 ONLY REFRESH CYCLE* NOTE :,, DIN = Don't care DOUT = OPEN IH t C IH tasr trah A IH RO ADDR BEFORE REFRESH CYCLE NOTE :, A = Don't care IH C t C IH tcp tcsr tchr IH trp trh OH OL tcez OPEN * In only refresh cycle of 64Mb Adile & Bdie, when signal transits from Low to High, the valid data may be cut off.

11 HIDDEN REFRESH CYCLE ( READ ) IH t t IH D trsh tchr trad A IH tasr trah tasc RO tcah trh IH S trrh trp taa tcez tcac trez tclz tez trac OH OL OPEN DATAOUT

12 HIDDEN REFRESH CYCLE ( RITE ) NOTE : DOUT = OPEN IH t t IH trad D trsh tchr A IH tasr trah tasc RO tcah IH tcs tp tch trp trh tds tdh IH DATAIN

13 BEFORE REFRESH COUNTER TEST CYCLE IH t IH tcsr tchr tcpt t trsh tral A IH tasc tcah READ CYCLE IH trp trh S taa tcac H trrh tez tcez OH OL tclz DATAOUT trez RITE CYCLE IH trp trh tcs trl tcl tch tp IH tds tdh DATAIN NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.

14 BEFORE SELF REFRESH CYCLE NOTE :, A = IH C ts S C IH tcp tcsr tchs OH OL tcez OPEN IH trp trh TEST MODE IN CYCLE NOTE :, A = IH C t C IH tcp tcsr tchr IH tts tth OH OL tcez OPEN

15 PACKAGE DIMENSIONS Units : Inches (millimeters).133(3.38) R.062(1.57) 4.250(107.95) 3.984(101.19).125 DIA±.002(3.18±.051).400(10.16) 1.00(25.40).250(6.35).080(2.03).250(6.35) R.062±.004(R1.57±.10).250(6.35) 3.750(95.25) ( Front view ).125(3.17) MIN ( Back view ) Gold & Solder Plating Lead.350(8.89) MAX.010(.25)MAX.050(1.27).100(2.54) MIN.041±.004(1.04±.10).054(1.37).047(1.19).225(5.71) MIN Tolerances : ±.005(.13) unless otherwise specified NOTE : The used device are 4Mx4 EDO DRAM (SOJ & 300mil) DRAM Part No. : K4E170411DB (300 mil) K4E160411DB (300 mil) Revision History Rev 0.0 : Oct. 1999

Standard Products ACT15530 CMOS Manchester Encoder / Decoder May 16, 2005

Standard Products ACT15530 CMOS Manchester Encoder / Decoder www.aeroflex.com/avionics May 16, 2005 FEATURES MIL-STD-1553 Compatible 1.25 Megabit/sec Maximum Data Rate Sync Identification and Lock-in Clock