HIGH-VOLTAGE devices such as lateral diffusion transistors

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES 1 Analysis of GIDL-Induced OFF-State Breakdown in High-Voltage Depletion-Mode nmosfets Jone F. Chen, Member, IEEE, Chin-Rung Yan, Yin-Chia Lin, Jhen-Jhih Fan, Sheng-Fu Yang, and Wen-Chieh Shih Abstract A gate-induced-drain-leakage-induced OFF-state breakdown is examined in our high-voltage depletion-mode n-channel metal oxide semiconductor field-effect transistors. By increasing the dosage in the n-region, a bell-shaped trend between the OFF-state breakdown voltage V BD and the dosage in the n-region is observed. Such a bell-shaped trend is found to result from two competing factors: an electric field in the gate edge and an electric field associated with the drain bulk junction. The latter electric field is responsible for the falling part in the bell-shaped trend. Our model can explain the data of the slightly bell-shaped trend between OFF-state V BD and implant energy in the n-region. Additionally, the effect of Si recess variation on OFF-state V BD variation can be understood from our model. According to our model, approaches to improve OFF-state V BD and the effect of Si recess variation on V BD variation are proposed. Index Terms Bell-shaped, gate-induced drain leakage (GIDL), OFF-state breakdown, Si recess. I. INTRODUCTION HIGH-VOLTAGE devices such as lateral diffusion transistors have been widely used in liquid crystal display drivers, NAND Flash periphery circuits, and smart power management applications due to the fact that the fabrication of the devices is easily integrated into a standard complementary metal oxide semiconductor (CMOS) process. Because highvoltage devices are operated under high voltage, the OFF-state breakdown voltage V BD is a key device parameter. It has been shown that gate-induced drain leakage (GIDL) is one important mechanism in determining the OFF-state V BD of a device [1] [3]. GIDL is caused by band-to-band tunneling (BTBT) and becomes a major leakage component in devices operated under high voltage. In previous studies, some data show a negative correlation between GIDL-induced V BD and the dosage of a Manuscript received October 28, 2010; revised December 27, 2010 and February 14, 2011; accepted February 18, The review of this paper was arranged by Editor D. Esseni. J. F. Chen is with the Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan, and also with the Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 701, Taiwan ( jfchen@mail.ncku.edu.tw). C.-R. Yan is with the Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan; with the Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 701, Taiwan; and also with the Powerchip Technology Corporation, Hsinchu 300, Taiwan. Y.-C. Lin, J.-J. Fan, S.-F. Yang, and W.-C. Shih are with the Powerchip Technology Corporation, Hsinchu 300, Taiwan. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED device in an n-region [4] [6]. That is, GIDL-induced V BD decreases as the dosage of an n-region increases. There is an inconsistent trend reported that GIDL-induced V BD increases as the dosage at a gate overlap region increases [7]. Another report shows a reverse bell-shaped trend between GIDL-induced V BD and the dosage [8]. First, V BD decreases, but V BD increases later on as the dosage increases. In this paper, a different trend (i.e., a bell-shaped trend) between GIDL-induced V BD and the dosage in an n-region is found. The two competing factors responsible for such a trend are discussed. Furthermore, as devices are integrated into a chip, device density in the chip affects process variation and further affects the device OFF-state V BD. To evaluate such an issue, the variation in Si recess process for the n-region is also examined to analyze its impact on OFF-state V BD. II. EXPERIMENT The high-voltage depletion-mode n-channel MOS fieldeffect transistors (nmosfets) used in this paper are fabricated by Powerchip Technology Corporation. The device has an n + poly gate/oxide/p-well structure, and the width W and length L of the device are W/L = 10/2 µm. The gate oxide thickness is 41 nm. A low-doped drain structure is formed next to the source and the drain. The n-region is defined by a gate selfaligned implant before spacer formation, and the n + area is defined by a contact self-aligning implant. Note that in a sidewall spacer formation process, spacer etching results in Si surface recess, leading to dopant loss at the Si surface in the n-region. The typical Si surface recess depth is 10 nm. Fig. 1(a) and (b) shows the device structure and process steps related to this paper. In OFF-state breakdown measurement, both gate and bulk terminals are connected to the ground, whereas the source terminal is biased to 7 V to turn-off the channel as the device is a depletion-mode transistor. The drain voltage V D is increased from 7 V until V BD is reached. V BD is defined as V D when the drain current I D reaches 3 na based on circuit specifications. Using this test condition, two possible mechanisms, i.e., GIDL and punchthrough, may lead to a device breakdown. The actual breakdown mechanism can be judged by the path of the I D flow. If the I D flow is from the drain to the source, punchthrough occurs. On the other hand, if the I D flow is from the drain to the bulk, GIDL occurs. Note that the possibility that some of the GIDL current going to the source electrode is negligible based on the following two reasons. First, the channel is turned off when a bias of 7 V is applied to the source electrode due to a body effect. Thus, the GIDL current that occurred in the drain side has no path /$ IEEE

2 2 IEEE TRANSACTIONS ON ELECTRON DEVICES Fig. 1. (a). Structure and process steps of the high-voltage depletion-mode transistor and the cross section of the device. (b). Step 1 is the n-region selfalignment implant by the gate, step 2 is passivation-layer tetraethyl orthosilicate deposition, and step 3 is dry etching for sidewall spacer definition. Note that Step 3 induces an Si recess, leading to dopant loss at the Si surface in the n-region. to flow to the source electrode. Second, although the voltage difference between the source and gate electrodes is 7 V, the GIDL current that occurred in the source side is still negligible as a gate oxide thickness of 41 nm is thick enough. According to our experimental data, GIDL is identified as the mechanism that leads to an OFF-state breakdown. The relationships between the GIDL-induced OFF-state V BD and the following three factors, i.e., the implant dosage in the n-region, implant energy in the n-region, and the Si surface recess, will be discussed in the following. III. RESULTS AND DISCUSSION As aforementioned, GIDL is responsible for the OFF-state breakdown in this device. Previous studies have pointed out that a GIDL-induced breakdown is correlated with the electric field in the overlap region between the gate edge and the n-region due to lateral diffusion (in the gate overlap region). When the electric field in the gate overlap region increases, BTBT occurs in the gate and the n-overlap region, leading to GIDL and an OFF-state breakdown [9]. In this paper, Fig. 2(a) and (b) shows the relationship between OFF-state V BD and the n-region implant dosage and implant energy, respectively. Since V BD values are measured on several devices in each process condition, data in Fig. 2(a) and (b) are plotted from the average V BD value in each condition. Note that bell-shaped trends Fig. 2. (a) Bell-shaped trends are observed between OFF-state V BD and the implant dosage. (b) Implant energy in the n-region versus V BD performance are observed particularly in Fig. 2(a). As shown in Fig. 2(a), OFF-state V BD increases with an increase in the n-region dosage when the dosage is lower than cm 2,butV BD decreases when the dosage is higher than cm 2. Such a bell-shaped trend suggests that there are two competing factors. The electric field in the gate overlap region is not the only factor that determines OFF-state V BD. Note that, during OFF-state breakdown measurement, a high V D is applied such that I D reaches 3 na. Such a high V D value (a reverse bias for the drain bulk junction) creates a depletion region in the drain bulk junction. It is suspected that the electric field associated with the depletion region is the other factor that determines OFF-state V BD. To verify the aforementioned argument, Fig. 3(a) shows the technology computer-aided design (TCAD) results of the electric field and the depletion area for devices with various dosages in the n-region. TCAD simulations are performed at the same bias condition. A bias of 32 V is used because it is close to the lowest V BD experimental data shown in Fig. 2(a). If the simulations are performed at a higher V D bias, a similar trend in simulation results is also observed. From the simulation results, two regions of electric fields are observed. The first electric field (denoted as E 1 ) is located at the gate edge (X 1 = 1.1 µm),

3 CHEN et al.: ANALYSIS OF GIDL-INDUCED OFF-STATE BREAKDOWN IN nmosfets 3 Fig. 4. Schematic implant profile in the n-region is drawn. When implant energy is increased, the dosage at the Si surface in the n-region is decreased. When the amount of the Si recess is increased, the dosage at the Si surface in the n-region is increased. Fig. 3. (a) Two-dimensional electric field. (b) One-dimensional electric field (cutline from A to A ) distribution of devices with four different dosages in the n-region. whereas the second electric field (denoted as E 2 ) is associated with the drain bulk junction (X 2 = µm). Since E 1 has been shown to affect the OFF-state breakdown [5], [6], E 2 is suspected to be the second factor that determines OFF-state V BD. Although the magnitude of E 2 is smaller than E 1, the effect of E 2 on V BD may still be significant. One possible reason is that an electric field close to the n + region (i.e., E 2 )may have a greater impact on V BD. Such an argument is consistent with the fact that junction breakdown voltage is lower when the doping concentration is higher. To examine the effect of the dosage in the n-region on E 2, the depletion region and E 2 can be analyzed from the results in Fig. 3(a). As shown in Fig. 3(a), in the device with the heaviest dosage ( cm 2 ) in the n-region, the location of the maximum E 2 (X 2 = 1.4 µm) is closer to the gate edge (X 1 = 1.1 µm). On the other hand, in the device with the lightest dosage ( cm 2 ),the location of the maximum E 2 is shifted toward to the n + area (X 2 = 2 µm). This trend is more evident from the 1-D lateral electric field distribution (cutline from A to A ) plot, as shown in Fig. 3(b). Additionally, it is clear that the lateral distribution of E 2 is more uniform when the dosage is or cm 2. Note that the dosage of or cm 2 produces a higher V BD value, as shown in Fig. 2(a), and the TCAD results in Fig. 3(a) and (b) suggest that a more uniform distribution of E 2 produces a higher V BD value. Such an inference is reasonable because a uniformly distributed E 2 value produces a smaller maximum value of E 2, resulting in a higher V BD value. Note that a different, i.e., reverse bell-shaped, trend between GIDL-induced V BD and the dosage was reported in [8]. Two competing mechanisms including the magnitude of electric fields and the area where BTBT occurred are proposed to explain their results. In this paper,the occurrence of another mechanism, i.e., the shift in electric fields, is responsible for the different trend with the previous report. According to the previous analysis, the slightly bell-shaped trend between OFF-state V BD and implant energy in the n-region shown in Fig. 2(b) can also be explained. Remember that a bell-shaped trend between V BD and the dosage in the n-region is the result of contributions from E 2. Additionally, E 2 is dependent on the dosage at the Si surface in the n-region. As implant energy increases, the peak of the implant dopant is located deeper from the Si surface after diffusion by thermal treating. Thus, the dosage at the Si surface decreases when implant energy increases. This argument is schematically drawn in Fig. 4. Since implant energy indirectly affects the dosage at the Si surface, the effect of implant energy on V BD is less than the effect of the implant dosage on V BD. Thus, a slightly

4 4 IEEE TRANSACTIONS ON ELECTRON DEVICES Fig. 6. Electrical field distribution of devices with two different distances between the gate edge and the n + region (G off ). Fig. 5. (a) The relationship between the resistance of the resistor and the V BD of the nmosfet. (b) A simplified device structure shows how Si recess affects the dosage at the Si surface in the n-region. bell-shaped trend between V BD and implant energy is observed in Fig. 2(b). Previous discussions point out that OFF-state V BD is affected by the dosage at the Si surface in the n-region. Such an argument indicates that a process, e.g., Si recess, that affects the dosage at the Si surface in the n-region may have impact on V BD. In the CMOS process, the Si recess occurs and leads to the loss of a dopant at the Si surface in the n-region, as depicted in step 3 in Fig. 1(b). Since the amount of Si recess varies with device density, the Si recess variation caused by process variation may cause a significant variation in OFF-state V BD. To evaluate this concern, a special design of experiment is conducted. In this experiment, the sheet resistances of the resistors of n-region devices that have the same process with the depletion-mode nmosfets are measured. The resistors are located close to the depletion-mode nmosfets in each die. It is reasonable to assume that the amount of Si recess is roughly the same between the resistor and the nmosfet provided that they are in the same die. Since the only factor that affects the resistance value of the resistor is the amount of Si recess, one can measure the resistance of the resistor and the V BD value of the nmosfet in the same die to evaluate the effect of Si recess on V BD. Results are shown in Fig. 5(a), where data of different groups are collected from different wafer lots. It is clear that a higher resistance of the resistor is closely related to alowerv BD value of the nmosfet. Since a higher resistance of the resistor is resulted from more Si recess, it is suggested that more Si recess produces a lower V BD value. Such a trend is consistent with our previous argument. When the amount of Si recess is increased, the dosage at the Si surface in the n-region is increased (this can be understood by considering the dopant profile such as that in Fig. 4). Thus, more Si recess results in a higher dosage at the Si surface [as schematically depicted in Fig. 5(b)], leading to a lower V BD. According to our analyses, possible solutions to improve OFF-state V BD and the impact of Si recess variation on V BD variation are proposed as follows. 1) To improve OFF-state V BD, based on the results in Fig. 3(a) and (b), a better OFF-state V BD value can be obtained when E 2 is distributed more uniformly. One possible solution is to increase the distance between the gate edge and the n + region (i.e., G off,asshownin Fig. 1). This argument can be confirmed from the TCAD results shown in Fig. 6. Increasing G off from to µm produces a more uniform E 2 distribution and reduces the maximum value of E 2 even if the dosage in the n-region is light ( cm 2 ).Thus,alower electric field and a higher OFF-state V BD value can be achieved. 2) In improving the effect of Si recess variation on OFF-state V BD variation, Si recess variation affects OFF-state V BD variation due to the variation of the dosage at the Si surface in the n-region. Increasing the implant

5 CHEN et al.: ANALYSIS OF GIDL-INDUCED OFF-STATE BREAKDOWN IN nmosfets 5 OFF-state V BD and the implant energy in the n-region. Additionally, the effect of Si recess on OFF-state V BD can be understood by our proposed model. Finally, two approaches are proposed to improve OFF-state V BD and the effect of Si recess variation on V BD variation: First, increasing the distance between the gate edge and the n + area can improve OFF-state V BD, and second, increasing the implant energy in the n-region can improve Si-recess-variation-induced V BD variation. ACKNOWLEDGMENT The authors would like to thank W.-Z. Wong for assistance in the measurement. Fig. 7. Relationship between the V BD value of the nmosfet and the resistance of the resistor for two different implant energy values in the n-region. energy is proposed to alleviate such a problem, and an example is shown in Fig. 7. The first plot in Fig. 7 shows that the data obtained from group 4 have the same trend as those in groups 1 3, where groups 1 3 are the same data in Fig. 5(a). The second plot in Fig. 7 shows the data obtained from group 4 with two different implant energy values in the n-region. As shown in the latter figure, the effect of resistance of the resistor (i.e., the effect of Si recess) on V BD becomes weaker as the implant energy is increased from 75 to 85 kev. Such a trend can be understood by the fact that heavier implant energy reduces the dosage at the Si surface. Thus, Si recess variation has less effect on Si surface dopant variation, leading to more uniform V BD values. IV. CONCLUSION In this paper, high-voltage depletion-mode nmosfets have been used to study the GIDL-induced OFF-state V BD. A bellshaped trend is found between OFF-state V BD and the dosage in the n-region because two competing factors, i.e., the electric field at the gate edge and the electric field associated with the drain bulk junction, determine the value of V BD. Such a model can also explain the slightly bell-shaped trend between REFERENCES [1] H. Sasaki, M. Saitoh, and K. Hashimoto, Hot-carrier induced drain leakage current in n-channel MOSFET, in IEDM Tech. Dig., 1987, pp [2] C. Duvvury, D. J. Redwine, and H. J. Stiegler, Leakage current degradation in n-mosfets due to hot-electron stress, IEEE Electron Device Lett., vol. 9, no. 11, pp , Nov [3] Z. J. Ma, P. T. Lai, and Y. C. Cheng, OFF-state instabilities in thermally nitrided-oxide n-mosfets, IEEE Trans. Electron Devices,vol.40,no.1, pp , Jan [4] S. A. Parke, J. E. Moon, H.-J. C. Wann, P. K. Ko, and C. Hu, Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model, IEEE Trans. Electron Devices, vol. 37, no. 7, pp , Jul [5] K.-W. Kim, C.-S. Choi, and W.-Y. Choi, Analysis of a novel elevated source drain MOSFET with reduced gate-induced drain-leakage current, in Proc. IEEE Hong Kong Electron Devices Meeting, 2000, pp [6] D. Rideua, V. Quenette, D. Garetto, M. Weybright, J. P. Manceau, O. Saxod, C. Tavernier, and H. Jaouen, Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model, in Proc. IEEE ICMTS, 2010, pp [7] J.-C. Guo, Y.-C. Liu, M. H. Chou, M. T. Wang, and F. Shone, A threeterminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET, IEEE Trans. Electron Devices, vol. 45, no. 7, pp , Jul [8] R. Shirota, T. Endo, M. Momodomi, R. Nakayama, S. Inoue, R. Kirisawa, and F. Masuoka, An accurate model of subbreakdown due to band-to-band tunneling and its application, in IEDM Tech. Dig., 1988, pp [9] T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, The impact of gate-induced drain leakage current on MOSFET scaling, in IEDM Tech. Dig., 1987, pp Jone F. Chen (S 93 M 98) received the B.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1990 and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1995 and 1998, respectively. Since 1999, he has been with the Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, where he is currently a Professor. He is also currently with the Advanced Optoelectronic Technology Center, National Cheng Kung University. His main research interests include the reliability of deep submicrometer and high-voltage metal oxide semiconductor devices.

6 6 IEEE TRANSACTIONS ON ELECTRON DEVICES Chin-Rung Yan was born in Kaoshiung, Taiwan, in He received the M.S. degree from National Cheng Kung University, Tainan, Taiwan, where he is currently working toward the Ph.D. degree with the Institute of Microelectronics, National Cheng Kung University. He is also currently with the Advanced Optoelectronic Technology Center, National Cheng Kung University, and with Powerchip Technology Corporation, Hsinchu, Taiwan, and with where he is focused on the development and optimization of periphery devices for 50-nm NAND Flash devices. Yin-Chia Lin received the M.S. degree in electrical engineering from Feng Chia University, Taichung, Taiwan, in In 1999, he was with the Process Integration Team, Worldwide Semiconductor Manufacturing Corporation, Hsinchu, Taiwan. Since 2001, he has been with the Logic Technology developing Team, Powerchip Technology Corporation, Hsinchu. His current research interests include NAND Flash device development. Sheng-Fu Yang was born in Tainan, Taiwan, in He received the B.S.E.E. and M.S.E.E degrees from I-Shou University, Kaohsiung, Taiwan, in 1999 and 2001, respectively. Since 2003, he has been with the Device Group, Powerchip Technology Company, Hsinchu, Taiwan, where he was engaged in the development and characterization of power devices. His current research interests include technology computer-aided design simulation of Si metal oxide semiconductor fieldeffect transistors and Flash memory devices. Wen-Chieh Shih was born in Pingtung, Taiwan, in He received the Ph.D. degree from National Tsing Hua University, Hsinchu, Taiwan, in Currently, he is with Powerchip Technology Company, Hsinchu. He has worked on nonvolatile memory devices including ferroelectric field-effect transistors, NAND Flash, resistive random access memory, and copper indium gallium selenide photovoltaic devices. His research interests include the physics of carrier transport in high-k oxides and solid-state devices. Jhen-Jhih Fan was born in Hsinchu, Taiwan, in He received the M.S. degree in photonics technologies from National Tsing Hua University, Hsinchu. Since 2006, he has been with the Powerchip Technology Corporation, Hsinchu. His main research interests include the development and optimization of periphery devices for 50-nm NAND Flash devices.