Gate Insulator Effects on the Electrical Performance of ZnO Thin Film Transistor on a Polyethersulphone Substrate

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1 Copyright 2012 American Scientific Publishers All rights reserved Printed in the United States of America Journal of Nanoscience and Nanotechnology Vol. 12, , 2012 Gate Insulator Effects on the Electrical Performance of ZnO Thin Film Transistor on a Polyethersulphone Substrate Jae-Kyu Lee and Duck-Kyun Choi Department of Materials Science and Engineering, Hanyang University, Seoul , Korea Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO 2, SiN x and SiO 2 /SiN x. The SiO 2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiN x /SiO 2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10 7,22cm 2 /Vs, 1.7 V and 0.4 V/decade, respectively. Keywords: Delivered ZnO, AOS by TFT, Publishing Flexible, Technology Transparent, to: PES. Hanyang University Library 1. INTRODUCTION Hydrogenated amorphous silicon has been extensively investigated as an active layer for TFT for flexible electronics such as flexible solar cell and flexible TFTs. 1 5 However, their performance is limited by the low mobility and degradation on exposing to air and light. In addition, the Si based devices are of less interest due to their opaque nature for the transparent electronics application. For such purpose, ZnO is attractive and promising due to its transparent nature in the visible range of light spectrum. It exhibits band gap about 3.37 ev. 6 7 Besides, one of the important factors that make ZnO a competitive candidate for transparent optoelectronic device is the easiness in growing polycrystalline film at room temperature. As far as ZnO based devices are concerned, most of the works has been focused on improving the quality of channel material. The use of single crystalline ZnO has been reported by few authors. 8 9 While high performance ZnO or doped ZnO TFTs with high field effect mobility ranging 1 80 cm 2 /Vs and high on/off ratio ranging have been reported by many authors. There have been few studies on low threshold voltage and Author to whom correspondence should be addressed. low operating voltage employing high-k dielectrics as a gate insulator On the basis of existing literature and considering the transparency and low temperature growth capability, ZnO is still an outstanding candidate for flexible and transparent electronics. Recently, it has been demonstrated that zinc tin oxide (ZTO) TFT exhibits mobility of 14 cm 2 /Vs and on/off current ratio of on a flexible polyimide substrate. On the other hand, the mobility of 7 cm 2 /Vs and on/off current ratio of 10 3 with indium gallium zinc oxide (IGZO) active layer and Y 2 O 3 gate oxide on the polyethylene terephthalate substrate has been reported. 16 Thus, it is emphasized that the fabrication of flexible TFT is rather a compromise between processing and device parameters. The additional factor that enters into this picture is the coefficient of thermal expansion. The difference between the coefficient of thermal expansion between oxide and organic substrate leads to damage and degradation of devices. Therefore, the establishment of fabrication process for the flexible electronics with better device parameters is a challenging task. In this investigation, attempts have been made to demonstrate the ZnO based TFT on a flexible PES substrate. Furthermore, process optimization of ZnO channel layer and gate insulator design have been carried out to secure reliable performance on the flexible substrate. J. Nanosci. Nanotechnol. 2012, Vol. 12, No /2012/12/5859/005 doi: /jnn

2 Fig. 1. Schematic cross section of a ZnO TFT. 2. EXPERIMENTAL DETAILS Fig. 3. Microstructure for the ZnO film on PES deposited at 20 W in Ar. Polyethersulfone film was preheated at 120 C for an hour in air ambient to minimize the shrinkage that might occur during subsequent processing. 50 nm thick SiO2 barrier All films exhibit (002) peak near 34. There is a tendency layer was deposited by PECVD at 140 C on top and in increase of crystallinity with RF power. However, it is bottom surfaces of substrate, which was followed by a also observed that the film deposited at the power of 40 W deposition of 100 nm thick Al bottom gate electrode using or beyond resulted in micro-cracks. The difference in therevaporator at room temperature. The SiO2 gate insulator mal expansion between ZnO and PES originated from the layer was deposited at 140 C using PECVD and an active temperature rise of substrate during deposition is likely layer of 100 nm thick ZnO was grown at room temperato cause such cracks. In order to preserve crack free film ture using RF magnetron sputter at powers from 20 W to when preparing ZnO thin film, judicious control in depo70 W and a working pressure about 20 mtorr. The drain sition power is suggested. and source contacts were obtained by depositing 100 nm It has been noticed that the crystallinity and the grain thick Al using shadow mask. The channel length and width size are affected by the gas ratio in deposition. The morfor the stated process were 50 and 2000 m, respectively. phology of ZnO surface on PES deposited in Ar at RF The schematic of cross Delivered sectional view of a TFT device is by Publishing Technology to: Hanyang Library power of 20 WUniversity was examined with FE-SEM and is shown provided in Figure 1. IP: On: Sat,in09Figure Mar :28:23 3. Publishers The surface morphology of ZnO Copyright film was American analyzed Scientific As explained earlier, the design of a gate insulator (GI) using AFM while the crystallinity of ZnO was charactercompatible with ZnO active layer is another concern to ized using XRD. The electrical performance of gate oxide secure good transistor performance. In this study, SiO2, and the device characteristics were evaluated using semisinx, and SiNx /SiO2 gate insulator structures have been conductor analyzer, HP5279B. investigated. The thickness of all the insulators was same and fixed to 200 nm. The MIM structure of Pt/GI/Pt was employed to evaluate the leakage current behavior for three 3. RESULTS AND DISCUSSION different gate insulators. It turned out that the minimum The XRD patterns for ZnO thin films deposited on a PES leakage current density was observed for SiNx /SiO2. The substrate with various RF powers are provided in Figure 2. performance of three gate insulators is shown in Figure 4. Fig. 2. XRD patterns for ZnO films deposited at various RF powers of (a) 20 W, (b) 30 W, (c) 40 W, (d) 50 W, (e) 60 W and (f) 70 W Fig. 4. Leakage current density for three different MIM capacitors. J. Nanosci. Nanotechnol. 12, , 2012

3 (a) (b) by J V 2. The decay in the leakage current density with field can also be attributed to the formation of space charges. Same behavior is also visible for SiNx /SiO2 stack while the MIM with SiO2 exhibits classical tunneling behavior. The SiNx insulator has sources of creating trap at the interface and in the bulk as well. The equilibrium defects in the bulk are mainly responsible for the formation of space charges. Moreover, the existence of defects leads to Frankel Poole mechanism contribution to the leakage current density. Finally, at high field, tunneling mechanism governs the leakage current. During the device fabrication process, any crack leads to a serious degradation and poor device performance. The choice of higher RF power during deposition leads to the crack formation and it apparently propagates into channel layer. In this investigation, in order to avoid the crack formation and to retain the mechanical stability of substrate, 50 nm thick SiO2 buffer layer has been deposited using PECVD. The degree of deformation after the completion of device fabrication with buffer layer and without buffer layer is compared in Figure 6. It can be seen that the deposition of buffer layer enhances the mechanical stability of the substrate. The polymer-ceramic interface formation at Delivered by Publishing Technology to: Hanyang University Library (c) Fig. 5. Various plots of leakage current for MIM structures with three different gate insulators of SiO2, SiNx and SiO2 /SiNx showing (a) J (Leakage current density) V 2, (b) Fowler Nordheim tunneling mechanism and (c) Frankel Poole mechanism. J. Nanosci. Nanotechnol. 12, , 2012 Fig. 6. Degree of deformation with and without buffer layer In order to understand the leakage current mechanism, the leakage currents for different specimen were drawn again in various ways and are given in Figures 5(a) (c). The leakage current density for investigated structure is comprised of space charge contribution, Frankel Poole and Fowler Nordheim tunneling through GI. At the low field in the SiNx and SiNx /SiO2 gate insulators, space charge contribution predominates. On the other hand, at higher field, tunneling mechanism predominates. From the figure, the current density for MIM containing SiNx gate insulator sharply increases and can be characterized

4 the devices fabricated, one with SiN x /SiO 2 exhibits the best performance. stacked gate Fig. 7. Transfer curves for ZnO-TFTs with three different gate insulators. elevated temperature seems to improve the thermal and mechanical stability of substrate. Thus, the substrate using buffer layer of 50 nm SiO 2 has been used for the processing of devices. The optimal RF power, buffer layer deposited substrate and three different gate insulators have been chosen to investigate the reliability of flexible backplane for the display and to determine the performance of ZnO-TFTs. The transfer curves for the ZnO-TFTs with SiO 2, SiN Delivered x and SiN by x /SiO Publishing 2 are presented Acknowledgments: This work was supported by a Technology to: Hanyang University Library in Figure 7. The device parameters IP: of interest for ZnO- Korea Science and Engineering Foundation grant funded On: Sat, 09 Mar :28:23 TFT are channel mobility, threshold voltage, Copyright subthreshold American Scientific by the Publishers Ministry of Education, Science, and Technol- swing and on/off current ratio and those for ZnO-TFTs with three different gate insulators are listed in Table I. It appears that the channel mobility of the ZnO TFT with SiO 2 gate insulator is the highest one. However, that number is overestimated and not meaningful because of the relatively high leakage current. In fact, the SiN x /SiO 2 stacked gate shows the highest and meaningful value. The threshold voltage for ZnO-TFT exhibits a significant variation as the gate insulator changes from SiO 2 to SiN x or stacked SiN x /SiO 2. Since the gate electrode for all three devices is same, the source for changing threshold voltage appears to be associated with the interfacial traps. Substantial amount of traps are existing at the interface created by equilibrium defect in gate insulator employing SiN x. The subthreshold swing for the three devices also agrees with the conclusion. It shows decreasing trend as the gate insulator changes from SiO 2 to SiN x /SiO 2 stack. Among Table I. Device parameters for the ZnO-TFT with three different gate insulators. Gate insulator On/off ratio SS (V/dec.) V th (V) FE (cm 2 /Vs) SiO SiN x SiN x /SiO Note: Apparent mobility (over estimated value). 4. CONCLUSIONS ZnO as an attractive alternative for transparent flexible electronic has been investigated. The process optimization of ZnO deposition on the flexible substrate has been established. The lower RF power, in this case 20 W has been observed to be the best choice for the ZnO deposition. Furthermore, the deposition of 50 nm thick SiO 2 buffer layer on both sides of the flexible substrate turned out to improve the mechanical and thermal stability. The gate leakage current has been observed to be lowest for the case of SiN x /SiO 2 stack structure which concludes a stack configuration can be a solution for gate insulator. Using the optimal parameter, the ZnO-TFT on the polymer (PES) substrate has been successfully fabricated and the device parameters have been evaluated. The highest field effect mobility of 22 cm 2 /Vs has been observed for the device with SiN x /SiO 2 stack gate. A reliable process for the fabrication of TFT on flexible substrate and improved device parameter, low temperature fabrication of ZnO-TFT has been established. ogy (No. R , SRC/ERC Program, CMPS) and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No ). References and Notes 1. C. R. Kagan and P. Andry (eds.), Thin Film Transistors, Marcel Dekker, New York (2003). 2. M. A. Quevedo-Lopez, W. T. Wondmagegn, H. N. Alshareef, R. Ramirez-Bon, and B. E. Gnade, J. Nanosci. Nanotechnol. 11, 5535 (2011). 3. C.-S. Yang, L. L. Smith, C. B. Arthur, and G. N. Parsons, J. Vac. Sci. Technol. B 18, 683 (2000). 4. P. G. Carey, P. M. Smith, S. D. Theiss, and P. Wickboldt, J. Vac. Sci. Technol. A 17, 1946 (2000). 5. S. C. Wang, C. F. Yeh, C. K. Huang, and Y. T. Dai, Jpn. J. Appl. Phys. 42, 1044 (2003). 6. A. Umar, A. A. Alharbi, P. Singh, and S. A. Al-Sayari, J. Nanosci. Nanotechnol. 11, 3560 (2011). 7. A. Mute, M. Peres, T. C. Peiris, A. C. Lourenço, R. Jensen Lars, and T. Monteiro, J. Nanosci. Nanotechnol. 10, 2669 (2011). 8. S. H. Park, S. I. Jun, K. S. Song, C. K. Kim, and D. K. Choi, Jpn. J. Appl. Phys. 38, L108 (1999). 9. D. Murley, N. Young, M. Trainor, and D. McCulloch, IEEE Trans. Electron Device 48, 1145 (2001). 10. J. Nishii, F. M. Hossain, T. Aita, Y. Ohmaki, S. Kishimoto, T. Fukumura, Y. Ohno, H. Ohno, S. Takagi, K. Saikusa, I. Ohkubo, A. Ohtomo, F. Matsukura, H. Koinuma, and M. Kawasaki, Jpn. J. Appl. Phys. 42, L347 (2003) J. Nanosci. Nanotechnol. 12, , 2012

5 11. K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, Science 300, 1269 (2003). 12. I. D. Kim, M. H. Lim, K. T. Kang, H. G. Kim, and S. Y. Choi, Appl. Phys. Lett. 89, (2006). 13. I. D. Kim, Y. W. Choi, and H. L. Tuller, Appl. Phys. Lett. 87, (2005). 14. G. Cramer, NNIN REU 2006 Research Accomplishment 34 (2006). 15. W. B. Jackson, R. L. Hoffman, and G. S. Herman, Appl. Phys. Lett. 87, (2006). 16. Y. J. Cho, J. H. Shin, S. M. Bobade, Y. B. Kim, and D. K. Choi, Thin Solid Films 517, 14 (2009). Received: 30 July Accepted: 16 February Delivered by Publishing Technology to: Hanyang University Library J. Nanosci. Nanotechnol. 12, ,