SNJB College of Engineering Department of Computer Engineering

Transcription

1 1. Intel s programmable device (8253) facilitates the generation of accurate time delays. a) counter b) timer c) both a & b d) none of these 2. The programmable timer device (8253) contains three independent bit counters. a) 8 b) 16 c) 20 d) The 8-bit data buffer interfaces internal circuit of 8253 to microprocessor systems bus. a) Unidirectional b) Single c) Bidirectional d) None of these 4. The three counters available in 8253 are independent of each other in operation, but they are to each other in organisation. a) Similar b) Opposite c) Identical d) Common 5. The speciality of the 8253 counters is that they can be easily read on line without disturbing the input to the counter. a) GATE b) CLK c) OUT d) WR

2 6. The GATE signal is and should be for normal counting. a) Active Low, Low b) Normal, Normal c) Active High, High d) None of the Above 7. When GATE goes low counting is terminated and the current count is till the GATE again goes high. a) Disturb b) Latched c) Decrease d) Increase 8. If N is loaded as the count value, then, after N pulses, the output becomes low only for clock cycle. a) One b) Zero c) N d) (N-1) 9. In this mode, the 8253 can be used as a wave rate generator. a) Sine wave b) Cosine wave c) Square wave d) All of these e) 10. When count is N loaded in, then for half of the count, the output remains high and for remaining half it remain low. a) Odd b) Even c) Even-even d) Odd-odd 11. If the count loaded is odd the first clock cycle pulse decrement by resulting in an even count value. a) 0 b) 1

3 c) -1 d) None of these 12. The processor 8085 had hardware interrupt pins. a) 4 b) 5 c) 6 d) The predecessor 8259 was designed to operate only with bit processors like a) 4 b) 8 c) 16 d) A modified version, was later introduced that is compatible with 8-bit as well as 16-bit. a) 8259 b) 8359 c) 8259A d) 8359A 15. stores all the interrupt requests in it in order to serve them one by one on the priority basis. a) IRR b) ISR c) IMR d) NMI

4 16. keeps a track of the requests being served. a) IRR b) ISR c) IMR d) NMI 17. stores the bits required to mask the interrupt input. a) IRR b) ISR c) IMR d) NMI 18. pin is an active low write enable input to 8259A a) WR b) WR c) Both a & b d) None of these 19. In Cascade Buffer/Comparator the same pins act as inputs when the 8259A is in a) Master b) Slave c) Master-Slave d) All of these 20. goes high whenever a valid interrupt request is asserted. a) INT pin b) NMI pin c) IRR pin d) ISR pin 21. as inputs to accept interrupt requests to the CPU. a) IR₀-IR₇ b) CR₀-CR₇ c) DR₀-DR₇ d) TS₀-TS₇

5 22. In an based system, A₁₅-A₈ of the interrupt vector address are the respective bits of ICW₂. a) 8008 b) 8080 c) 8085 d) In an 8086/88 based system of the interrupt vector address are inserted in place of T₇ -T₃ respectively. a) A₁₅-A₁₁ b) A₁₅-A₈ c) A₁₅-A₁₃ d) A₁₅-A₅ 24. Special fully nested mode is selected, if SFNM=. a) 0 b) -1 c) 1 d) None 25. If AEOI=, the automatic end of interrupt mode is selected. a) 1 b) 0 c) -1 d) None 26. is the default mode of operation of 8259A. a) Real mode b) AEOI (automatic end of interrupt mode) c) EOI(end of interrupt mode) d) Fully Nested mode ANSWER: d 27. If bit LTIM of ICW₁=0, they are triggered

6 a) Edge b) Level c) Both a & b d) None of these 28. The I/O section is enabled only if CS Is a) High b) Low c) Very high d) Very low 29. RD /WR input pins enable the data buffers to receive or send data over the bus. a) Address b) Data c) Both a & b d) None of these 30. are used to scan the key board matrix and display digits. a) SL₀-SL₃ b) RL₀-RL₃ c) CL₀-CL₃ d) All of these 31. O/P pin is used to blank the display during digit switching or by a blanking command. a) BD b) BS c) BD d) BS 32. Scanned Keyboard Mode in encoded scan keyboard or in decode scan a Keyboard can be interfaced. a) 8*8,4*8

7 b) 4*8,8*8 c) 4*4,8*8 d) 8*4,4*8 33. Scanned Keyboard Special Error Mode is valid only under the key rollover Mode. a) 1 b) 50 c) N-1 d) N ANSWER: d 34. The 8-byte FIFO RAM now acts as bit memory matrix. a) 4*4 b) 4*8 c) 8*8 d) 8*4 35. In the left entry mode, the data is entered from the side of display unit. a) Left b) Right c) Front d) Back 36. In the right entry mode, the data is entered from the side of display unit. a) Left b) Right c) Front d) Back 37. In mode, data is transmitted only in one direction over a single communication channel. a) Simplex b) Duplex c) Half duplex d) Half simplex

8 38. input pins, together with RD and WR inputs, informs the 8251A that the word on the data bus is either a data or control word/status information. a) C/D-control Word/Data b) C/D -control Word/Data c) C /D-control Word d) C /D -control Word/Data 39. A high on RESET input forces the 8251A into an state a) Wait b) Ready c) Idle d) Hold 40. input controls the rate at which the character is to be transmitted. a) System clock b) Transmitter clock c) Bus system clock d) Receiver clock 41. input controls the rate at which the character is to be received. a) System clock b) Transmitter clock c) Bus system clock d) Receiver clock ANSWER: d 42. may be used as a general purpose one bit inverting input port. a) DSR

9 b) DTR c) RTS d) CTS 43. may be used as a general purpose one bit inverting output port. a) DSR b) DTR c) RTS d) CTS 44. pin of 8251A receives a composite stream of the data to be received by 8251A a) RXD b) RXC c) RXRDY d) RD 45. When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial data bits, followed by optional parity bit and stop bits using the mode instruction control word format. a) Synchronous b) Asynchronous c) Both a & b d) None of the above 46. In the character synchronization can be achieved internally or externally. a) Synchronous b) Asynchronous c) Both a & b d) None of the above

10 47. Once the mode instruction has been written into 8251A and SYNC characters are inserted internally by 8251A, all the further control words written with will load command instruction. a) C/D=0 b) C/D=1 c) C /D=1 d) C/D =1 ANSWER: d 48. O/P also may be used as a general purpose one bit inverting O/P port that can be programmed low to indicate the modem. a) RTS b) DTR c) CTS d) All of the above 49. is used to generate internal device timings and normally connected to clock generator. a) CLK b) CLK reset c) CLK set d) None 50. is active low input to 8251A is used to inform it that the CPU is reading either data or status information from its internal register. a) RD b) BD c) CS d) WR