RL78 POC and LVD. Renesas Electronics Corporation A Renesas Electronics Corporation. All rights reserved.

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1 RL78 POC and LVD Renesas Electronics Corporation A

2 Introduction Purpose This course provides an introduction to the RL78 Power-On-Clear and Low Voltage Detector. Objective Learn about the RL78 POC and LVD features and its capabilities. Content 18 pages (including this page) Learning Time 20 minutes 2

3 POC Power-On-Clear 3

4 Power-On-Clear Circuit Functions Generates internal reset signal at power on Compares supply voltage V DD and detection voltage V POC V DD >= 1.51V ± 0.03V and generates internal reset signal when V DD < 1.50V ± 0.03V CPU can also be released by LVD, selectable by an option byte Current consumption already included in STOP mode current Block Diagram 4

5 Power-On-Clear Circuit Operation LVD is off V POC0 to V POC2 = 0x07 Undefined area The supply voltage enters the undefined area If this may happen in the system, the LVD must be used in combination. 5

6 LVD Low-Voltage-Detector 6

7 Low-Voltage-Detector Circuit Functions Compares the supply voltage V DD with detection voltage V LVIH, V LVIL and generates a reset or internal interrupt Detection voltage is selectable by option byte 14 levels (1.63V~4.06V) Three different operation modes available interrupt and reset mode Reset mode Interrupt mode Very low power consumption of only 0.1uA LVD is operating is STOP mode 7

8 Block diagram of LVD 8

9 Option byte for LVD Functions of this register Select base operation mode of the LVD Select voltage level of LVD Address : 000C1H/010C1H VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 VPOC2-0,LVIS0,1 Set detection voltage by combination LVIMDS1 LVIMDS0 selection LVD operation mode 0 0 Setting prohibited 0 1 Interrupt mode 1 0 interrupt & Reset mode 1 1 Reset mode 9

10 Low-Voltage Detector levels Detection voltage levels When used as reset mode, or interrupt mode Detection voltage (TYP.) When used as interrupt & reset mode Detection voltage (TYP.) 14 levels can be selected. 10

11 LVD control register LVIM Functions of this register Write enable for LVIS Status flags for LVD operation LVIM LVISEN LVIOMSK LVIF LVISEN Write enable for LVIS 0 Disabling rewriting to LVIS 1 Enabling rewriting to LVIS LVIOMSK Mask status flag of LVD detection 0 LVD operation enabled 1 LVD operation waiting LVIOMSK is set to 1 automatically after LVISEN =1. After rewriting LVIS, LVD detection needs stabilization. LVIOMSK =1 during rewriting LVIS and during stabilization. Therefore after clear LVISEN to 0, LVIOMSK is kept 1 during stabilization time of about 200us to 300us. LVIF voltage detection status flag 0 VLVI =< VDD 1 VDD =< VLVI 11

12 LVD control register LVIS Functions of this register Mode selection (LVIMD) Voltage level selection (LVILV) It is possible to write to LVIS register in interrupt & reset mode if LVISEN =1. In interrupt mode or reset mode it isn't possible to change the value of LVIS. Interrupt & reset mode Interrupt mode Address : FFFAAH After reset : 00H / 01H / 81H Reset mode Symbol LVIS LVIMD LVILV LVIMD Selection of LVD detection mode 0 Interrupt mode 1 Reset mode LVILV LVD detection voltage level 0 High-voltage detection level 1 Low-voltage detection level 12

13 Different LVD modes Different Objectives and the right LVD mode A Objective LVD should be used to substitute an external reset IC. RESET mode Mode to be used Reset generation at the preselected voltage. B C Switch device in secure state/standby in case of low voltage. Save important data before reset by low voltage detection. Interrupt mode Interrupt generation at the preselected voltage. Interrupt (detection notice) and reset mode Interrupt generation at the preselected voltage and finally reset generation at reset voltage. 13

14 Example A: external reset IC Supervise guaranteed voltage range of CPU To avoid operation outside specified area Operation condition frequency : HOCO 32MHz Voltage : 5V LVD setting Option byte 00C1H : B LVD detection voltage : VLVI5 (rise 2.81V(typ.) fall 2.70(min.)) LVD mode : reset mode LVD LVD reset release. and CPU start operation. 2.81V(typ.) Reset by LVD 2.7V(min.) CPU operable POR 1.51V CPU inoperable ->time CPU state POR reset LVD reset CPU operation LVD reset POR reset 14

15 Example B: Switch device to standby Supervise guaranteed voltage range of CPU and set device into standby to avoid operation outside specified area Operation condition frequency : HOCO 8MHz voltage : 3V LVD setting Option byte 00C1H : B LVD detection voltage : VLVI11 (rise 1.88V(typ.) fall 1.8V(min.)) LVD mode : interrupt mode LVD Reset release by LVD only rising supply voltage. and start operation CPU. 1.88V(typ.) Cause interrupt by LVD. then switching to standby by software. 1.80V(min.) CPU operable POR 1.51V Reset by POR. Stopped RTC CPU inoperable ->time CPU state POR reset LVD reset CPU operation STOP POR reset RTC state POR reset LVD reset RTC operation POR reset 15

16 Example C: Save data before reset Supervise guaranteed voltage range of CPU and save parameters before enter reset. Operation condition frequency : HOCO 8MHz voltage : 3V LVD setting Option byte 00C1H : B LVD detection voltage Reset release voltage : VLVI6 2.71V(typ.) Reset voltage : VLVI8 2.40V(min.) Interrupt voltage : VLVI6 2.60V(min.) LVD mode : interrupt (detection notice)& reset mode LVD LVD reset release and CPU operation start. LVD is set to interrupt 2.71V(typ.) Cause interrupt by LVD. Then switching LVD to reset automatically. saving important data by software. 2.60V(min.) Reset by LVD CPU operable 2.40V(min.) POR CPU inoperable ->time CPU state POR reset LVD reset CPU operation saving data LVD reset POR reset 16

17 Summary Power on Clear Functions Block Diagram Operation LVD Functions Block Diagram Option Bytes Registers Operation Modes For more information, visit: 17

18 Renesas Electronics Europe