Optimization of the fabrication condition of RF sputtered ZnO thin film transistors with high-k HfO2 gate dielectric

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1 The University of Toledo The University of Toledo Digital Repository Theses and Dissertations 2017 Optimization of the fabrication condition of RF sputtered ZnO thin film transistors with high-k HfO2 gate dielectric Prem Thapaliya University of Toledo Follow this and additional works at: Recommended Citation Thapaliya, Prem, "Optimization of the fabrication condition of RF sputtered ZnO thin film transistors with high-k HfO2 gate dielectric" (2017). Theses and Dissertations This Dissertation is brought to you for free and open access by The University of Toledo Digital Repository. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of The University of Toledo Digital Repository. For more information, please see the repository's About page.

2 A Dissertation entitled Optimization of The Fabrication Condition of RF Sputtered ZnO Thin Film Transistors with High-k HfO2 Gate Dielectric by Prem Thapaliya Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Doctor of Philosophy Degree in Engineering Dr. Rashmi Jha, Committee Chair Dr. Christopher Melkonian, Committee Member Dr. Mansoor Alam, Committee Member Dr. Nickolas Podraza, Committee Member Dr. Yanfa Yan, Committee Member Dr. Patricia R. Komuniecki, Dean, College of Graduate Studies The University of Toledo May 2016

3 Copyright 2016, Prem Thapaliya This document is copyrighted material. Under copyright law, no parts of this document may be reproduced without the expressed permission of the author

4 An Abstract of Optimization of The Fabrication Condition of RF Sputtered ZnO Thin Film Transistors with High-k HfO2 Gate Dielectric by Prem Thapaliya Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Doctor of Philosophy Degree in Engineering The University of Toledo May 2016 Conventional amorphous silicon based thin film transistors have been the most widely used ones for flat panel display application during the last two decades. However, the low mobility of less than 1 cm 2 /Vs and light induced instability of the amorphous silicon based thin film transistor make them unsuitable for high resolution displays. Oxide based thin film transistors have attracted a great deal of interest as an alternative to conventional amorphous silicon based thin film transistors for high resolution display applications. In particular, ZnO has gained considerable interest for the next generation transparent and flexible display due to its wide band gap of 3.37 ev, high electron mobility and low temperature deposition forming good quality of polycrystalline film even at room temperature. Consequently all the aforementioned features of ZnO make them promising channel material for the flexible and transparent TFTs. The electrical characteristics of ZnO based TFTs is greatly affected by the deposition condition and hence crystalline quality of channel layer, thickness of channel layer and quality of interface between the gate dielectric and the channel layer. Therefore, the deposition temperature and the thickness of the ZnO iii

5 channel needs to be optimized in order to achieve high performance ZnO TFTs. Moreover, the quality of interface between the ZnO channel layer and the gate dielectric is of vital importance to improve the performance of the TFTs. In this dissertation, we have fabricated and characterized RF sputtered ZnO based thin film transistor using high-k HfO2 gate dielectric. The transparent ZnO TFTs was realized using FTO as a transparent gate electrode as opposed to commonly used ITO gate electrode. It was found that TFTs fabricated using the FTO gate electrode showed lower mobility and on/off ratio compared to the TFTs with Ru as a gate on the Si substrate. This deterioration of TFTs performance with the use of FTO gate electrode was attributed to the degradation of HfO2 gate dielectric due to the diffusion of fluorine from the FTO into the HfO2 during its deposition at 300 o C. In order to minimize the interface trap density at the interface between the ZnO and HfO2, an interfacial layer of MgO with different thickness was investigated. It was found that 10 nm MgO is an optimum thickness that can reduce the interface trap density by almost one order of magnitude and hence exhibit the best TFTs performance with field effect mobility, threshold voltage, on/off ratio and subthreshold swing to be 0.3 cm 2 /V.s, 3.7 V, 10 6 and 1.35 V/decade respectively. The decrease in the interface trap density with the interfacial layer was attributed to the reduction of defects in the ZnO by the excess oxygen ions of MgO. Furthermore, the ZnO channel layer was deposited at different temperature including room temperature, 50 o C, 100 o C and 200 o C, to determine the optimum deposition temperature that can achieve high performance ZnO TFTs. It was found that ZnO deposited at 50 o C showed the best TFT performance with field effect mobility, threshold voltage, on off ratio and subthreshold swing 1.12 cm 2 /V.s, 5.8 V, , 1.35 V/decade respectively. The improvement in the performance of the iv

6 TFTs device with 50 o C ZnO was attributed to the low surface roughness of ZnO film, increased grain size and good polycrystalline quality which was confirmed with the help of XRD, AFM and SEM measurement of ZnO thin film deposited at different temperature. Likewise, once the optimum deposition temperature of ZnO was determined, the effect of ZnO thickness was investigated by depositing the ZnO with different thickness including 30 nm, 50 nm, 70 nm and 100 nm while maintaining the deposition temperature of ZnO to be at 50 o C. It was found that the TFTs device with 50 nm exhibit the superior performance over the other thicknesses of ZnO which was ascribed to the improved polycrystalline quality, low surface roughness of the 50 nm ZnO thin film. v

7 Acknowledgements First of all I would like to thank my advisor Dr. Rashmi Jha for providing me this wonderful opportunity to work with her on this interesting research project. This work would not have been possible without her constant guidance, support and encouragement throughout my PhD research work. Also, I would like to thank my dissertation committee members: Dr. Christopher Melkonian, Dr. Mansoor Alam, Dr. Nickolas Podraza and Dr. Yanfa Yan for their time and effort in reviewing my work and providing constructive feedback. I greatly appreciate Dr. David Strickler and Vikash Ranjan at Pilkington North America for the fruitful discussions and also for providing the FTO glass substrate. I want to thank Corey Rice for helping me with the AFM, SEM and XRD measurements. I sincerely thank my previous group members Branden Long, Saptarshi Mandal and Ammaarah Halee, Yash Bansal for useful discussion and training me on the RF magnetron sputtering and photolithography. I am also thankful to my current group members Wenchao Lu, Wenbo Chen and Yibo Li for their friendship and good times. Finally I would like to thank my family for their unconditional love and continuous support during my studies. vi

8 Table of Contents Abstract... iii Acknowledgements... vi List of Tables... xi List of Figures... xii 1. Introduction and Background Electronics Displays ZnO Properties Oxide based TFTs Thin Film Transistor History Current standing of ZnO TFTs High-k dielectric for thin film transistors Interface Charges Thin Film Transistor Structure and Principle of Operation TFTs Performance Parameters Threshold voltage vii

9 1.8.2 On /off ratio Mobility Subthreshold swing Thin Film Transistor Operating Principle Experimental Procedures and Characterization Methods Transmission Line Measurement X-Ray Diffraction Atomic Force Microscopy Scanning Electron Microscope Transmission Electron Microscope (TEM) RF Sputtering Photolithography Lift off Chapter Electrical Characteristics of RF Sputtered ZnO/HfO2 Interfaces in Transparent Thin Film Transistors Introduction Experimental Procedures Results and Discussions Conclusions viii

10 4: Understanding the Effect of MgO Interfacial Layer on ZnO/High-k/FTO Transparent Thin Film Transistors for Large-Area Transparent Electronics Applications Introduction Experimental Procedures Results and Discussions Conclusions : Effect of Deposition Temperature of ZnO Active Channel Layer on the Electrical Characteristics of ZnO TFTs Introduction Experimental Procedures Results and Discussion Conclusions : Effect of ZnO Channel Layer Thickness on the Electrical Characteristics of TFTs Introduction Experimental Procedures Results and Discussion Conclusions Chapter ix

11 7: Conclusions and Future Work Conclusions Future Work References Appendix A Fabrication Process Flows Appendix B Electrical Characterization of Mg/Zn3P2 Schottky Contact x

12 List of Tables Table 1: Physical properties of ZnO... 6 Table 2: Comparison of performance of different TFT technologies Table 3: Summary of ZnO based TFTs performance Table 4:ZnO TFTs performance summary with different MgO interfacial thickness Table 5: Electrical parameters extracted from C-V characteristics Table 6: Performance summary of ZnO TFTs with different ZnO deposition temperature Table 7: Performance summary of ZnO TFTs with different ZnO thickness xi

13 List of Figures Figure 1-1: Transparent display technology global market trend... 3 Figure 1-2.:ZnO Crystal Structure... 5 Figure 1-3:Oxide TFTs publications by year Figure 1-4: Band Gap versus dielectric constant for gate dielectric Figure 2-1:TLM structure showing metal contacts with different spacing Figure 2-2: Resistance versus metal contact spacing to extract sheet resistance Figure 2-3: C-V characteristics of MOS capacitor showing accumulation, depletion and inversion regime Figure 2-4: Crystal plane separated by distance d Figure 2-5: AFM working principle set up Figure 2-6: SEM working principle set up Figure 2-7: RF sputtering set up Figure 3-1: Schematic cross-section view of ZnO TFTs structure (a) sample A (b) Sample B (c) Sample C Figure 3-2: ID-VDS characteristics of samples A, B and C Figure 3-3:ID-VGS(transfer) characteristics of samples A, B and C Figure 3-4: C-V characteristics of samples A, B and C Figure 3-5: Gate leakage characteristics of samples A, B and C xii

14 Figure 3-6:Gp/ω as a function of radial frequency at different gate bias Figure3-7: Interface state density as a function of trap energy level for samples A, B and C Figure 4-1: Schematic cross section view of ZnO TFTs structure Figure 4-2: ID-VDS characteristics of samples A, B, C and D Figure 4-3: Gate leakage characteristics of samples A, B, C and D Figure 4-4: Transfer characteristics of samples A, B, C and D Figure 4-5: C-V characteristics of samples A, B, C and D at 1 MHz Figure 4-6: Gp/W as a function of bias for samples A, B, C and D Figure 4-7: Interface state density as a function of trap energy level Figure 5-1: Schematics of ZnO TFS with ZnO deposited at different temperature Figure 5-2: XRD pattern of ZnO deposited at different temperature on glass substrate.. 91 Figure 5-3: SEM image of ZnO deposited at different temperature (a) RT (b) 50 C (c) 100 C (d) 200 C Figure 5-4: AFM image of ZnO deposited at different temperature (a) RT (b) 50 C (c) 100 C (d) 200 C Figure 5-5: I-V characteristic on ZnO with different Al contact spacing Figure 5-6: Resistivity versus temperature plot for ZnO deposited at different temperature Figure 5-7: C-V characteristics of ZnO deposited at different temperature Figure 5-8: Carrier concentration versus ZnO deposition temperature plot Figure 5-9: ID-VDS characteristics of ZnO TFTs at different ZnO deposition temperature (a) RT (b) 50 C (c) 100 C (d) 200 C xiii

15 Figure 5-10: Transfer characteristics of ZnO deposited at different temperature Figure 6-1: Schematics of ZnO TFTs with different thickness of ZnO active layer Figure 6-2: AFM image of ZnO with different thickness (a) 30 nm (b) 50 nm (c) 70 nm (d) 100 nm Figure 6-3: XRD pattern of ZnO with different thickness Figure 6-4: TEM image of ZnO TFT with 50 nm of ZnO Figure 6-5: SEM image of ZnO with different thickness (a) 30 nm (b) 50 nm (c) 70 nm (d) 100 nm Figure 6-6:C-V characteristics of ZnO TFTs with different thicknesses of ZnO Figure 6-7: Gp/ω-ω characteristics of ZnO TFTs with different ZnO thicknesses xiv

16 Chapter 1 1. Introduction and Background 1.1 Electronics Displays Electronic displays are of great research interest to the scientist and engineers since early 1900s. The tremendous growth in computing technology over the past few decades has allowed the transfer of information through pervasive electronic and optical networks. This human/machine visual interaction is accomplished by electronic display. Displays are becoming ever more ubiquitous to everyday life. They have become the essential components of information system including computing and communication devices, consumer electronics, instrumentation and controls, industrial electronic and avionics systems. The invention of cathode ray tube (CRT) display opened up the new avenue for the electronic display and the further development of CRT is facilitated by the large scale production of monochrome CRT-based TV. However, the design of CRT based display had some serious issues such as its size, weight and high power consumption along with poor resolution and harmful radiation. CRT was replaced by amorphous silicon (a-si:h) thin film transistors (TFTs) driven Liquid Crystal Displays (LCDs) which proved to be the mainstream of next-generation display. The a-si:h TFTs has a field effect mobility (μeff < 1

17 1 cm 2 /V.s) which is too low for high speed or large-current applications, such as the driving circuit of the display or the pixel driving in the organic light emitting diode (OLED) display [1]. Furthermore a-si:h TFTs shows instability against electric stress and photoillumination [2]. Transparent electronics has emerged as one of the most promising technologies for the next generation of optoelectronic devices, away from the traditional silicon technology. It is essential for touch display panels, solar cells, LEDs and antistatic coatings. Though transparent display is at its early stage of its commercialization and debut the market for the first time in 2012, the last available display market forecasted by Displaybank seems to be very promising which has been shown in Fig 1-1[3] 2

18 Figure 1-1: Transparent display technology global market trend Transparent devices could add an interesting features in transparent display. For instance, transparent display may appear as an ordinary window when it is switched off and can be used to display information on demand. In order to realize fully transparent devices, one must have optically transparent thin film transistors. The main challenge of the transparent electronics is the requirement of a material which is not only fully transparent to the visible light but also have good carrier mobility. The coexistence of the transparency and the conductivity seem contradictory from the standard solid-state physics concepts, since large band gap material is required for the transparency which suggest the material to be insulator type. While semiconductors and metals show good conductivity, 3

19 they are not transparent to visible light as they absorb most frequencies of visible light. Transparent oxide semiconductors are very interesting materials because they combine simultaneously high/low conductivity with high visual transparency and have been widely used in a variety of applications (transparent conductive oxide is a special class of materials which possesses both transparency and good conductivity. Oxide semiconductors such as ZnO, are considered to be promising for thin film transistor applications due to its high optical transparency, high electron mobility, low temperature deposition and excellent environmental stability [4]. Therefore, ZnO is considered to be an ideal material for serving as the channel layer in transparent and flexible TFTs. 1.2 ZnO Properties ZnO is a wide band gap optoelectronic materials which belongs to II-VI n type compound semiconductor oxide and exhibit the unique dual properties of semiconducting and the piezo electronics [5]. ZnO is one of the most widely studied transparent conducting oxide for a variety of applications including thin film transistors for display applications, solar cells, laser diodes, ultraviolet lasers, light emitting diodes, gas sensors, high radiation resistant devices for space- and nuclear-electronics due to the feasibility of wet chemical etching, high radiation resistance, low material cost and availability of large area ZnO substrate [6]. ZnO has a direct band gap of 3.37 ev and exciton binding energy of 60 mev which makes ZnO attractive for the wide range of optoelectronic applications [7]. ZnO thin films have been deposited using a number of methods, hydrothermal method, RF sputtering, ion beam, molecular beam epitaxy, pulsed laser deposition, spray pyrolysis, metalorganic chemical vapor deposition (MOCVD), sol gel spin coating, chemical bath 4

20 deposition and atomic layer deposition [6]. Among these methods, RF magnetron sputtering is preferred due to its several advantages over the other deposition technique including high deposition rate, low substrate temperature, good surface flatness, transparency and the dense layer formation and uniformity over large surface area, good growth control of the thickness and composition of the thin films [7]. Generally, ZnO crystallizes in three main types, wurtzite (B4), zinc blende (B3), and rocksalt (B1), the schematic of which are shown in Fig However the most stable phase of ZnO at ambient condition is wurtzite. In wurtzite hexagonal crystal structure, zinc and oxygen planes are alternately stacked along the c-axis direction where each Zn ion is surrounded by tetrahedral of O ions, and vice-versa [8]. The lattice parameters of the hexagonal unit cell are a=3.25 Å, c=5.12 Å, and the density is gcm -3 [9]. Figure 1-2.:ZnO Crystal Structure ZnO is inherently n type due to the native defects such as oxygen vacancies and zinc interstitials. This defect- or impurity-dominated conductivity is a consequence of the large 5

21 band gap (3.37 ev at room temperature) combined with the unavoidable presence of electrically active native defects and impurities with donor ionization energies typically mev at concentrations typically cm -3 [10]. However, p-type doping of ZnO with a reliable method and high quality p-type ZnO is still a challenge which hinders the possibility of a ZnO p-n homojunction devices. The reported electron Hall mobility of ZnO at room temperature for the n type conductivity of ZnO is 200 cm 2 /Vs while the low p type conductivity is 5-50 cm 2 /Vs [11]. The large band gap of ZnO make them highly transparent in the visible and near infrared region of electromagnetic spectrum and have low resistivity which makes it a promising candidate for transparent electronics applications. The basic physical properties of the bulk ZnO has been given in the table 1[12, 13]. Table 1: Physical properties of ZnO Properties Value a nm c nm Density gm/cm 3 Melting point 2248 K Relative dielectric constant 8.66 Bandgap 3.37 ev, direct Exciton binding energy 60 mev Electron effective mass 0.24 Hole effective mass 0.59 Electron mobility 200 cm 2 /V.s Hole mobility 5-50 cm 2 /V.s 6

22 1.3 Oxide based TFTs Oxide semiconductors have attracted significant interest in recent years for transparent and flexible electronics. They are considered to be the promising channel materials for TFTs due to the high transparency in the visible region and ability to deposit at low process temperature on the flexible substrate [14]. In addition, they have high electron mobility and excellent uniformity over large area substrate, good thermal and environment stability and low manufacturing cost [15-16]. Furthermore, oxide based TFTs can be fabricated at room temperature with good performance. Oxide based TFTs have shown great promise as a next candidate for high performance display in the last few years due to the significant progress in fabrication techniques and availability of wide range of oxide semiconductors. Transparent electronics has gained significant attention in recent years for fully transparent display and has shown great promise for next generation of flat panel display technology [17]. The TFTs have been commonly used as a switch that control the brightness of each pixel in display application. Amorphous Si (a-si) and polycrystalline-si (poly-si) have been commonly used as a switching transistors in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) display. However, a- Si exhibit low mobility of less than 1 cm 2 /V.s which is too low for a driving circuit for the next generation of display [18]. This low field effect mobility is enough for LC display, which is typically operated at 120 Hz or less [19]. Also, light induced instability and opacity of a-si based TFTs is of major issue for transparent display applications. On the other hand, polycrystalline silicon (poly-si) requires hightemperature fabrication processes (>500 C) which makes them unsuitable for flexible electronics. Also, the low uniformity of poly Si based TFTs is of concern for large area 7

23 displays [20]. However, the next generation display demands larger size (60 inch), high resolution (200 pixels per inch), and high frame rate (120 Hz) [21]. In order to achieve such requirement for next generation of display and active matrix organic light-emitting displays (AMOLEDs), carrier mobility of 5-10 cm 2 /V.s is required [22]. Furthermore, the high temperature required for intentional crystallization during the deposition of a -Si and poly Si based TFTs make them unsuitable for the integration onto the flexible plastics substrates; and also adds to production cost [23]. Also, thin film transistors based on a-si:h technology suffers from light sensitivity and light induced degradation of the performance of the TFTs due to the large leakage current [24]. Organic based TFTs has been considered as an alternative to traditional Si based TFTs due to their capability of deposition at low temperature by solution processing techniques such as spin coating, inkjet printing or casting making roll-to-roll production possible for low cost and large area flexible TFTs [25]. However, the organic based TFTs have really low mobility comparable to a-si which limits its use in TFTs for active matrix backplanes for displays [26]. Moreover, organic based TFTs faces the severe problem of reliability issue due to their poor stability in the air degrading their performance. Also, the mobility of organic based TFTs is low to drive the next generation high performance AM-LCD and AM-OLED backplanes with a large size, high solution, and high frame rate. Oxide semiconductor are composed of heavy post transition metal cations with an electronic configuration (n-1)d 10 ns o, where n 4 [27]. Several oxide semiconductors such as ZTO, InGaZnO, InZnO and HfInZnO, IZO, and GIZO, IGZO have been explored for the channel materials in the thin film structure. Such oxide semiconductors are considered to be promising as they are transparent due to their large band gap, high mobility despite 8

24 being amorphous in nature and low temperature deposition. Due to their high bandgap >3 ev, the performance of the transparent TFTs don t degrade on exposure to the visible light. Among various amorphous oxide semiconductors, in particular IGZO appears to be one of the promising TCO channel material for the high performance TFTs required for the next generation displays. The performance of the IGZO based TFTs have been improved continuously with considerably superior performance compared to a-si:h or organic TFTs, such as mobilities above 76 cm 2 V 1 s 1, turn-on voltages close to 0.5 V, on/off ratio exceeding 10 5 and subthreshold swing of 0.12 V dec 1 [28]. Amorphous InGaZnO TFTs as an active matrix backplane has been demonstrated by successful fabrication of flat panel displays such as 12.1 in. AMOLED and 15 in. AMLCD [29]. However, In being a scarce and expensive element make InGaZnO TFTs unsuitable candidate to be used as a backplane device in the mass production of flat panel displays such as AMLCD or AMOLED. Table 2 shows the comparison of different TFTs technologies that are already commercialized or in the process of commercialization [30]. Oxide semiconductors are intrinsically n type due to native shallow defects including either oxygen vacancies, cation interstitials, or substitutional or interstitial hydrogen. Oxide semiconductors exhibit much higher electrical conductivities (10 2 Ω 1 cm 1 to 10 2 Ω 1 cm 1 ) compared to wide gap metal oxide materials due to inherent high levels of n-type conductivity [31]. Therefore oxide semiconductors exhibit high mobility even when deposited at room temperature making them promising materials for various electronics applications including solar cells, light emitting diode, LCD. In these metal oxide semiconductors, the conduction band minima is dominated by the metal s-states, which are insensitive to the angular distortion and hence retain a high mobility. The high mobility of oxide semiconductor is due to the 9

25 strong iconicity [32]. Also, the conduction band minimum and valence band maximum are formed of different ionic species in which charge transfer takes place from metal to oxygen atoms. The conduction band minimum (CBM) of oxides are made of spherically extended orbitals of metal cations, which overlaps with neighboring metal orbitals without any alteration by disordered amorphous structures. Hence electronic levels of CBM are insensitive to local strained bonds and structural randomness resulting in no effect on electron transport. The electronic structure formed by these ions is stabilized by the Madelung potential formed by these ions which raises electronic levels in cations and lowers the levels in anions [33]. This is the reason why oxide semiconductors exhibit large electron mobilities even in amorphous structures. Furthermore, the large band gap and the transparency of such amorphous oxide is due to the large Madelung potential. Table 2: Comparison of performance of different TFT technologies TFT Properties Oxide semiconductors a-si Low-T poly-si Organic semiconductors Carrier max mobility(cm 2 /V.s) Switching (V/dec) Manufacturing low low high low cost Process RT <500 RT Temperature ( 0 C) Long term TFT high low high low reliability Yield high high medium high 10

26 1.4 Thin Film Transistor History TFT was invented in early 1920s and was patented by J.E. Lilienfeld and O. Heil in 1930s [34]. Since there was little understanding about semiconductor materials and the deposition technique to produce thin film, realization of TFT couldn t be achieved during that time. However, Lilienfeld s patient described the basic principle of the metal semiconductor field effect transistor (MESFET) on which TFT works. The first functional working TFT was achieved by Weimer at the RCA Laboratories in 1962 [35]. He used polycrystalline cadmium sulfide (CdS) deposited by evaporation technique as a semiconductor layer and silicon monoxide as an insulator. This opened up the new avenue for TFTs. Soon after, Klasens and Koelmans proposed TFTs using evaporated SnO2 on glass, anodized Al2O3 gate dielectric and aluminum as source-drain electrodes [36]. The SnO2 TFT exhibited poor electrical performance, including lack of saturation, positive curvature of the output characteristics, an almost negligible amount of transfer curve, and the inability to turn the device off. ZnO TFTs was first reported in 1968, by Boesen and Jacob and they use lithium doped ZnO single crystal semiconductor and evaporated SiOX as a gate dielectric [37]. The TFTs showed poor performance with very low drain current and no current saturation. Since then, metal oxide TFTs have been continually improved, so that they now exhibit desired characteristics. Following the first report on ZnO TFTs, several other oxide such as In2O3, SnO2 were explored for the TFTs fabrication. However, the poor performance of such oxide totally disappoint the scientific community. Several semiconductor materials such as CdSe, Te, InSb and Ge were investigated for TFTs but the emergence of the metal oxide semiconductor field effect transistor (MOSFET) based on the crystalline silicon technology put the research and development of TFT under 11

27 shadow by the end of 1960s. Despite the successful demonstration of functional TFTs based on CdSe, the commercialization of TFTs in LCD applications didn t take momentum until the report on the feasibility of doping amorphous silicon (a-si:h) by the glow discharge technique. It was only in 1979, when Spear and Le Comber achieved breakthrough in the TFT made from hydrogenated amorphous silicon (a-si:h) with a silicon nitride gate dielectric layer which accelerated the research and development of a-si TFTs [38]. Although a-si:h TFT attracts much attention due to its capability to drive LCDs, the low electron mobility limits its applications in high-speed or large-current applications, such as the driving circuit of the display or the pixel driving in the organic light emitting diode (OLED) display. Oxide semiconductor as a channel layer regained its interest in 1996 when Prins et al reported SnO2: Sb TFTs combined with a ferroelectric gate [39]. The research and development of oxide TFT received much attention by both industry and academia community when Hoffman et al reported transparent TFT using ZnO [40] and Nomura et al demonstrated TFT using InGaZnO4 with good device performance in 2003 [41]. Oxide semiconductor TFTs have emerged as promising electronic devices only after 2004 and have been studied extensively bringing different innovation to improve the device performance. Following the successful demonstration of high performances TFTs by Hoffman et al, with mobility as high as 2.5 cm 2/ V.s., which exhibited better performance compared to a-si and organic TFTs, ZnO based TFTs has attracted significant interest both in academia and industry [42]. Since then several oxide semiconductors have been studied extensively as a channel materials flexible and transparent TFT based electronic devices. 12

28 It can be seen that in fig 1-3, the number of publications of ZnO based TFTs has increased tremendously over the last decade. Interestingly, the number of publication has increased exponentially from 30 in 2005 to more than 140 in the year 2008 [43]. Figure 1-3:Oxide TFTs publications by year 1.5 Current standing of ZnO TFTs Kang et al demonstrated ZnO TFTs using Mg doped Ba0.6Sr0.4TiO3 as gate dielectric on the plastic substrate with all the layers deposited at room temperature [44]. The TFTs exhibited a high field-effect mobility of 16.3 cm 2 /V s and a current on/off ratio of Chang et al reported the transparent ZnO TFT with multilayered gate dielectric 13

29 with HfO2 layer sandwiched by Al2O3 layers. They found that by employing Al2O3 between the ZnO and HfO2, hysteresis characteristics can be dramatically suppressed due to the prevention of charge trapping at the interface [45]. The saturation mobility, on-to-off ratio, threshold voltage, and subthreshold swing was found to be 12 cm 2 /V s, , 1.24 V, and 0.52 V/decade, respectively. Zhang et al demonstrated ZnO TFTs using Ta2O5 as a gate dielectric deposited at room temperature [46]. The device showed a field effect mobility of 60.4 cm 2 /V s, a threshold voltage of 1.1 V, an on/off ratio of , and a subthreshold swing of 0.23 V/decade. They attributed the high field effect mobility to fringing-electricfield effect due to the undefined active layer and low trap state densities in the insulator/channel interface. Nilsen et al fabricated the ZnO TFTs using ZnO and Ta2O5 as a high k dielectric by RF sputtering at room temperature. The devices showed saturation mobility values over 50 cm 2 /Vs, an on/off ratio of greater than 10 5, and a subthreshold voltage swing of 0.29 V/decade at a low operating voltage of 4 V [47]. Chen et al fabricated ZnO TFTs using MgO gate dielectric with and without introduction of oxygen during MgO deposition [48]. The TFTs device with oxygen-introduced MgO showed field effect mobility as high as 78.3 cm 2 /V.s. The improvement in the mobility was attributed to excess oxygen in MgO increasing the alignment of the ZnO channel layer along the (002) planes, which leads to the reduction of grain boundaries in ZnO. Remashan et al reported ZnO TFTs with ZnO channel layer and gate dielectric Si3N4 grown by MOCVD [49]. They found that by employing thin layer of MgZnO between ZnO and Si3N4, the device exhibited high performance field-effect mobility of 9.1 cm 2 /V s, a subthreshold slope of 0.38 V/dec, an on/off current ratio of , and a turn-on voltage of 2.75 V as compared to 2.3 cm 2 /V s, 0.78 V/dec, , and 6.75 V for the device without MgZnO layer. They 14

30 attributed the large grain of the ZnO film to the improved performance of the TFTs. Lin et al fabricated flexible TFTs on plastic with double stack of gate dielectric Al2O3/HfO2 and ZnO channel layer deposited by atomic layer deposition [50]. The TFTs exhibit excellent device performance with high stability and flexibility: field-effect mobility >20 cm 2 V 1 s 1, subthreshold swing < 0.4 V decade 1. Adamopoulos et al reported low voltage ZnO TFTs with Y2O3 as a gate dielectric deposited by spray pyrolysis [51]. The device exhibited low leakage currents, and hysteresis-free operation with a maximum electron mobility of 34 cm 2 /V s and current on/off ratio on the order of Esro et al fabricated TFTs with ZnO and HfO2 fabricated using solution processed spray pyrolysis technique [52]. Thin film transistors based on HfO2 /ZnO stacks exhibit excellent electron transport characteristics with low operating voltages ( 6 V), high on/off current modulation ratio ( 10 7 ) and electron mobility in excess of 40 cm 2 V 1 s 1. Chen et al developed self-aligned top-gate zinc oxide (ZnO) thin film transistors (TFTs) utilizing high-k Al2O3 thin film [53]. The resulting transistor exhibits a field effect mobility of 27 cm 2 /V s, a threshold voltage of 0.5 V, a subthreshold swing of 0.12 V/decade and an on/off current ratio of High-k dielectric for thin film transistors The performance of the CMOS devices have been improved during the past four decades achieved through the downscaling of gate length which leads to an increase in number of transistor on a chip following the trend as predicted by Gorden. E. Moore [54]. As the gate length is scaled down, the other parameters have to be scaled down 15

31 correspondingly in order to keep the internal electric field same and hence avoiding the short channel effects. Practically, the scaling of power supply voltages is not possible. The scaling of gate length demands a corresponding decrease in the dielectric film in order to increase the gate oxide capacitance. SiO2 has been widely used as a gate dielectric material. The thickness of SiO2 has already reached to its fundamental physical limit of below 1 nm and cannot be further thinned down due to the limitation of lithography and the availability of sufficiently small wavelengths of light to pattern the minimum feature size. In addition, such thickness of SiO2, the gate leakage current becomes intolerably high which causes problems such as increased standby power consumption, deteriorated reliability and device lifetime, and can degrade the device performance [55, 56]. For instance, the SiO2 of 1.5 nm, the gate leakage current is as high as 100 A/cm 2 which is tremendously high for low power applications and can severely impact the device performance [57]. Therefore SiO2 needs to be replaced with a thicker gate dielectric material which can maintain the gate leakage current density at low level while achieving high capacitance. In this regard, high k dielectrics are commonly used which shows high capacitance while keeping the gate leakage current density within the acceptable limit with the thicker oxide. The capacitance of the field effect transistor devices can be increased either by increasing the dielectric constant k value or reducing the oxide thickness as given by the equation below: ka C (1) t 16

32 That is equivalent thickness of SiO2 giving the same capacitance as of the high-k gate dielectric with thickness thigh-k and dielectric constant khigh-k is known an equivalent oxide thickness which can be expressed as t EOT k k SiO high k 2 t (2) high k The gate leakage current can be maintained low by replacing the SiO2 with thicker oxide. However, the thick oxide results in the decrease in the capacitance. There are a number of high k dielectrics such as Ta2O5, La2O3, Al2O3, HfO2, ZrO2 that have been used to replace the SiO2 [58]. It has always been a great challenge to find the suitable dielectric materials for a given channel materials in thin film transistors. A number of factors need to be considered when using a high k dielectric as an alternative to SiO2 for the high performance device such as high dielectric constant and wide band gap, good interface with semiconductor with low interface density, low fixed charge density, reasonable valence band offset and conduction band offset between the gate dielectric and semiconductor leading to high breakdown voltage and low gate leakage current [59, 60]. The use of a gate dielectric with an increased k allows a reduction in driving voltage of a transistor or an increase in dielectric film thickness while maintaining the same gate capacitance, thus suppressing the gate leakage current due to electron tunneling. 17

33 Figure 1-4: Band Gap versus dielectric constant for gate dielectric The high k dielectrics generally have a low band gap since gate oxide s k value tends to vary inversely with the band gap as can be seen in figure 1-4 [61]. Also, the high k oxide have high electron affinity which results in small conduction band continuity. This could lead to a low breakdown voltage and high leakage current. Therefore it is imperative to find the suitable dielectric material for a given semiconductor channel layer which could not only give high coupling of gate electrode to the channel layer but also reasonable band offset with channel and hence showing low leakage current and high breakdown voltage. The gate insulator not plays an important role in governing the performance of the TFTs but also the stability of the device under bias/illumination stresses. The high k dielectric reduces the threshold voltage by increasing the capacitive coupling between the gate electrode and active channel layer caused by the accumulation of more number of electrons [62]. Furthermore, the subthreshold swing of the TFTs get reduced with the use 18

34 of high k dielectric. It is commonly observed that MOSFETs with high-k gate dielectrics show degraded mobility compared to Si MOSFETs with SiO2 gate oxide. Coulombic scattering from the fixed oxide charges in the high-k layer or at the interfaces, remote phonon scattering, remote surface roughness scattering, and crystallization are some of the possible sources behind the mobility degradation [63, 64]. Moreover, the use of high- k may introduces issues such as the ability to continue scaling to lower EOTs, loss of carrier mobility in the Si, shifts of the gate voltage threshold, and finally instabilities caused by the high concentration of electronic defects in the oxides [65] Among the several high-k dielectrics, HfO2 is one of the most promising materials due to its remarkable properties highlighting (i) high dielectric constant 25, (ii) relatively low leakage current, (iii) low synthesis temperature (iv) large band gap 5.68 ev and sufficient to yield a positive band offset with respect to ZnO, and (v) high transparency over a wide spectral range extending from the ultraviolet to the mid infrared [66, 67]. 1.7 Interface Charges Due to the presence of various kind of unavoidable charges within the oxide and at oxide-semiconductor interface, the ideal characteristics of the MOS structure is affected. The different charges found in MOS capacitor system has been shown schematically in the fig 1-5. It should be noted that all of these four different kind of charges greatly depends on the fabrication condition and the environment. Fixed oxide charges are located at or near the semiconductor/dielectric interface. Fixed oxide charges are formed due to the structural defects such as incompletely oxidized silicon. The fixed oxide charge depends on the oxidation rate, annealing condition and 19

35 crystal orientation. For Si-SiO2 interface, the typical value of Qf is about charge/cm 2. A positive Qf results in a negative VFB shift and a negative Qf results in a positive VFB shift. Figure 1-5: An interface of Si-SiO2 showing various types of interface charges Also, this fixed oxide charge tends to scatter the carriers at the semiconductor/dielectric interface by Coulombic scattering mechanism and hence degrade the carrier mobility. Oxide trapped charges are located inside the bulk of the oxide layer which could be produced due to the energetic radiation or hot electron injection. Moreover, the defects in the bulk of the oxide layer also accounts for the oxide trapped charge. Mobile 20

36 ionic charge is due to the alkali metal ions particularly Na + contamination during the oxide growth or subsequent processing steps. They are unintentionally introduced during the process of fabrication and can be reduced by the proper care during the device fabrication. Unlike fixed oxide charges and trapped charges, mobile ionic charge are mobile within the oxide which introduces positive charge in the oxide which in turn induces negative charges in the semiconductor. Mobile ionic charge can change the threshold voltage since they are mobile and can drift in an applied electric field resulting in gate bias instability. In addition to oxide charge, there exists interface states within the forbidden gap due to the termination of semiconductor periodic crystal lattice at the oxide/semiconductor interface, excess oxygen or impurities. The interface states are usually located at or close to the oxide/semiconductor interface as shown in fig 1-6. Unlike fixed oxide charge, interface charge can flow between the semiconductor and interface-states. Therefore, the performance of the electronic devices consisting of oxide/semiconductor interface is greatly influenced by the amount of interface trap and its distribution within the band gap of the semiconductor. The net charge in the interface states is a function of the position of the Fermi level in the band gap which depends on the applied bias. An interface trap could acts as a donor if it is neutral when occupied by an electron and can donate an electron and thereby becoming positively charged. Similarly it is considered as an acceptor if it is neutral when empty and can accept an electron turning itself into negatively charged entity [68]. The distribution function for the donor FSD (Et) and acceptor interface FSA (Et) trap can be given by the following set of equations [68]: 21

37 F F SD SA 1 ( Et ) 1 g exp[ (3) D E E / kt F E E / kt t 1 ( Et ) (4) 1 g exp[ A t F Where Et is the energy of the interface traps, gd is the ground-state degeneracy for donor and is equal to 2, ga is the ground degeneracy for acceptor and is equal to 4. It should be noted that for any oxide/semiconductor interface, there exist both kind of traps. Therefore the interface state density distribution represents the sum of these two types of interface states such that states above the charge neutrality level ECNL represents the acceptor type while the states below ECNL are of donor type as shown in the fig 1-7 EC Interface States Efm Metal Oxide Semiconductor EV Figure 1-6: Distribution of interface states within the band gap of semiconductor in MOS structure 22

38 EC Acceptor States ECNL Donor States Oxide Semiconductor EV Figure 1-7: Oxide/semiconductor interface showing acceptor states and donor states Interface states at the oxide/semiconductor interface is usually quantized by interface state density. The interface state density is denoted with Dit and is measured in ev -1 cm -2 units. There are several techniques including subthreshold slope technique, conductance method, and high-low frequency C-V technique to measure the interface states. Among them, Conductance method is one of the most widely used method of interface state density characterization in MOS type structure due to its high sensitivity and 23

39 accuracy [69, 70]. This method is based on the measurement of the loss caused by trapping and detrapping of carriers between the conduction band and interface trap levels when the ac signal is applied. A small signal ac voltage is superimposed over the applied dc bias which causes the Fermi level at the interface to oscillate about a mean position. As a result, the interface states at or near the Fermi level changes their occupancy which results in the phase lag between the applied ac signal and frequency response of the interface states [71]. The equivalent circuit which includes the interface trap effect is shown in the fig. 1-8 where Ci and CD are the insulator capacitance and the semiconductor depletion layer capacitance; Cit and Rit are the capacitance and resistance associated with the interface traps. The interface trap density (Dit) is related to the interface trap capacitance by [68] Cit qd it (5) where q is the elementary charge and the interface lifetime τit is given by it C it R (6) it which determines the frequency behavior of the interface traps. The equivalent circuit in the fig 1-8 (a) can be converted into a frequency dependent capacitance Cp in parallel with a frequency dependent conductance Gp as shown in fig. 1-8 (b) where Cp and Gp/ω are given by: 24

40 Figure 1-8: Equivalent circuits including interface trap states, Cit and Rit C P C C (7) S it it G P C it it 2 2 (8) 1 it The measured admittance can be converted to the conductance of the interface of the interface trap arm given by the following equation [68] G p qad it it 2 2 ln(1 it ) (9) 2 it Where Dit is the density of interface states, ω is the angular frequency, τit is the time constant of interface states. The circuit in fig 1-8 (b) can be converted to the equivalent circuit consisting of measured capacitance (Cm) and the conductance (Gm) by the impedance meters as shown in fig 1-8 (c). After the correction of series resistance, the parallel conductance can be written in terms of the measured capacitance, Cm and measured conductance Gm using eq [69,70].: 25

41 Gp G 2 m 2 GmCox 2 ( C Cm ) ox 2 (10) where Gm is the measured conductance, Cm is the measured capacitance, and Cox is the interfacial oxide layer capacitance resulting from process induced incomplete covalent bonds and chemical reaction between metal and semiconductor. A plot of Gp/ω versus ω gives rise to a peak for each gate bias in the depletion regions. The peak in Gp/ω- log (f) plot shows a maximum value at ωτ = 1.98 which indicates the maximum loss when the interface traps are in resonance with the applied ac signal and substituting this value in Eq. 10, the interface state density can be determined from the following equation D it 2.5 (Gp ω ) max Aq (11) Where q is the electronic charge, Gp/ω max is the peak loss value and A is the area 1.7 Thin Film Transistor Structure and Principle of Operation There are four possible device structure that are widely adopted in the fabrication of amorphous oxide based TFTs. Depending on the position of source/drain and insulator with respect to semiconductor layer, the structure can be categorized as staggered or coplanar [72]. In staggered structure, the source/drain and the insulator are on the opposite sides of the semiconductor while they are on the same sides of the semiconductor in coplanar structure. Each of these structure could be bottom gate or top gate structure depending on if the gate electrode is on the top or at the bottom of the structure. Each of these structures has their advantages and disadvantages which is dictated by the processing conditions of the materials used in the TFTs. 26

42 Figure 1-9: Schematics showing different TFTs structure (a) staggered bottom-gate; (b) coplanar bottom-gate; (c) staggered top-gate and (d) coplanar top-gate In a bottom gate TFTs structure as shown in figure 1-9, the gate insulator and the gate electrode are located underneath the semiconductor layer. Therefore, there is a high risk of semiconductor being exposed to atmosphere which can degrade the TFTs performance. However, on the other hand, bottom gate TFTs structure can provide the opportunities of modifying the semiconductor properties by several surface treatments such as annealing and oxygen plasm treatment in order to improve the performance of the TFTs. Furthermore, the plasma induced damage to the semiconductor layer during the deposition of gate insulator by RF sputtering or plasma enhanced chemical vapor deposition (PECVD) can be minimized since the semiconductor layer is deposited on the top of gate insulator. The bottom gate structure is usually preferred when the semiconductor deposition temperature is low and hence the properties of the underneath layers and its interface could not be degraded. The staggered bottom gate structure is widely employed for a-si based TFTs since the bottom metal gate electrode protect the light sensitive a-si from the effect of back light in LCDs. On the other hand, in the top gate structure, the semiconductor layer 27

43 is covered by the gate insulator and the metal gate which could act as a passivation layer protecting the semiconductor from external damage. Top gate TFTs structure is usually preferred for TFTs which requires high deposition temperature for semiconductor layer. The idea behind this is to protect the properties of subsequent layers. 1.8 TFTs Performance Parameters The electrical characteristics of the TFTs which determines the performance are evaluated in terms of figure of merit such as threshold voltage, mobility, subthreshold swing, on/off ratio Threshold voltage It is an important TFTs parameter that corresponds to the gate voltage for which accumulation layer is formed between the source and drain and hence TFTs device starts to switch on from the off state. When VGS is less than VT, there is very low current that flow between the source and drain and thus TFTs device is in off state. However increasing VGS above VT, the channel conductance increases due to the increase in the channel charge density and the TFT is turned on. The n channel TFTs could have positive or negative threshold voltage depending on whether TFTs is working in enhancement or depletion mode operation. In enhancement mode, the device is normally off under zero gate bias and a gate voltage should be applied in order form a conductive channel between source and drain. On the other hand, in the depletion mode, device is normally on with zero gate bias and a gate bias is required to turn the transistor off. Enhancement mode is generally preferred since no gate voltage is required to turn off the transistor which greatly simplifies the circuit design and minimize the power dissipation [73]. Typically the 28

44 threshold voltage for the depletion mode TFT is negative for the n channel while it is positive for the enhancement mode. VT can be estimated from the linear extrapolation of ID-VG curve for low VD while square root of ID-VG for high value of VD [74] On /off ratio The on/off ratio is an important TFT figure of merit for switching application which is simply the ratio of maximum drain current at above threshold region to minimum drain current when the device is in off state. The on current is largely dependent on the semiconductor material and effectiveness of the capacitive coupling of the gate electrode to the channel layer. While the off current is dependent on the quality of gate dielectric. The on/off ratio characterize the ability of TFT to switch from on state to off state for switching. A large value of on current is preferred since higher resolution displays requires TFTs with large on current in order to drive imaging pixels while low off current is desired for minimizing the power consumption. Therefore high value of on /off ratio usually above 10 5 is desired [75] Mobility Mobility is another important figure of merit for TFTs which is a measure of the effectiveness of the carrier transport in the channel layer. Mobility is directly related to the maximum drain current and the operating frequency of the TFTs devices. The mobility of the carrier in the channel layer is governed by several scattering mechanisms including phonon scattering, remote charge scattering, surface roughness, grain boundaries and other surface defects. Furthermore, in addition to the aforementioned surface scattering mechanism, the mobility in the channel is influenced by the Coulombic scattering from the 29

45 dielectric charges and the interface states as well as fixed oxide charge which limits the drive current of TFTs [76, 77]. The mobility of the TFTs can be calculated by the different method as described below: Effective mobility: It is an estimate of average mobility at low drain voltage and is extracted from the drain conductance (gd) measured in the linear regime of operation can be calculated using the following equation g d I D W Cox ( VGS VT ) (12) V L DS g d eff (13) W Cox ( VGS VT ) L Where Cox is the oxide capacitance, W and L are the channel width and length, VT is the threshold voltage. Field effect mobility: It can be obtained from the transconductance (gm) at low VD using the following equation: g m I W D Cox VDS (14) VGS L C m FE (15) ox g W V L DS 30

46 Saturation mobility: It is calculated from the saturation region of the ID-VGS curve with high VD using the following equation: d I d 1 sat dv W (16) GS Cox L As it can be seen from the above equation, the saturation mobility can be calculated from the slope of ID versus VGS curve in the saturation regime. Each of the method explained defined above for the calculation of mobility has its own advantages and disadvantage. Field effect mobility and saturation mobility are the most commonly used to calculate mobility as they don t require VT and can be easily calculated from the derivative of the transfer characteristics Subthreshold swing Another important figure of merit of TFT which is defined as the gate voltage required to increase the drain current by one order of magnitude in the subthreshold region. The SS is a measure of the effectiveness of the gate voltage in reducing the drain current to zero. The small value of SS is desirable which corresponds to a very sharp transition from on to off state. This results in higher speeds and lower power consumption [75]. The SS is a measure of how fast the device switch between the on and off states. It is dependent on the quality of the interface of the semiconductor channel layer and the gate dielectric and can be used to determine the interface trap density using the following equation: 31

47 SS dv GS (17) d log I D SS SS e Ci N log( ) max 1 (18) ( kt ) q q Clearly, the lower is the SS slope, the faster the device can be switched between the on and off states over a small change in the applied gate voltage. Also, from the eq 18, it can be inferred that SS depends on the oxide capacitance, temperature and depletion layer capacitance. The high value of SS indicates the larger amount of interface trap density at the semiconductor gate dielectric interface. The TFTs is a special kind of three terminal field effect devices whose principle of operation is same as MOSFET [78]. It comprises three components namely semiconductor layer, insulator and source and drain as an electrical contacts. The TFTs comprises a dielectric between the active semiconductor and the gate electrode. The conductance of the channel between the source and drain electrode is modulated by the applied gate voltage caused by the capacitive coupling of carriers close to the dielectric semiconductor interface. However, it differs from MOSFET in several ways. As can be seen in the fig 1-9, TFTs use insulating substrate such as glass, plastic while MOSFET use silicon as both substrate and the channel layer. MOSFET use single crystalline semiconductor channel layer which requires high processing temperature. While TFTs employs thin film as a channel layer which can be fabricated at low temperature and hence making TFTs fabrication possible on plastic substrate for flexible and transparent electronics applications. In addition, TFTs doesn t have p-n junction at the source and drain regions unlike in MOSFET. Also, even 32

48 though TFTs and MOSFET works on the same principle of field effect in which channel conductance is controlled by the gate voltage, this is achieved by accumulation of majority carriers at the gate dielectric and channel interface in TFTs whereas inversion layer of minority carriers at the semiconductor/ gate dielectric interface constitutes the channel conductance in MOSFET. 1.9 Thin Film Transistor Operating Principle Fig 1-10 shows the energy band diagram of n- channel TFTs for the ideal condition of same metal and semiconductor work function. The energy band is flat (flat band condition) when the applied gate bias is zero. This is the ideal case when no charge is present at the insulator or at the insulator/semiconductor interface. When a positive gate voltage is applied with respect to the grounded source, the mobile electrons are attracted towards the semiconductor-insulator interface and the conduction band edge bends downwards near the surface and gets closer to the Fermi level as shown in the fig As a result, the electrons are attracted towards the interface of gate dielectric and semiconductor forming a channel between the source and drain known as accumulation layer. If a positive voltage is applied to the drain electrode, the electron flows from the source to the drain which constitutes the drain current. The magnitude of drain current can be modulated by varying the gate voltage. On the other hand, when a negative voltage is applied, the mobile electrons are repelled from the channel layer and the conduction band edge bends upwards. This causes the channel to deplete from electron and is known as depletion. When the negative voltage is increased beyond a certain value, maximum depletion layer thickness is reached after which the minority carrier (holes) exceeds the electron and constitutes the conductive channel at the semiconductor/insulator interface. 33

49 Figure 1-10: Energy band diagram showing accumulation, depletion and inversion regime The operation of TFTs can be explained with the help of three different regime namely cut off, linear and saturation. When the applied gate voltage is less than the threshold voltage, there is no channel induced between the source and drain resulting in no conduction as seen in fig However, due to the thermal energy, some of the energetic electron at the source is capable of entering the channel and flow to the drain. This constitutes the subthreshold current which is an exponential function of gate source voltage. 34

50 Figure 1-11: Channel formation in NMOS transistor (a) cut off region (b) linear region (c) triode region (d) saturation region When the applied voltage is greater than threshold voltage, accumulation of majority carriers is induced in the channel at the semiconductor and gate dielectric interface. The device behave like a resistor initially since the channel current increases with the applied drain bias as seen in fig This mode of operation of device is said to be in linear regime. As the magnitude of drain voltage is increased and reaches to VDS=VGS-VT, the region near the drain end is depleted of majority charge carriers due to the reduction in effective voltage between the gate and the drain, and channel pinch off is said to have occurred. W 1 2 I DS Cox V GS VT V DS VDS L forvds VGS VT (19) 2 35

51 I DS 1 W C 2 ox VGS V for V T DS VGS VT (20) 2 L Figure 1-12: Different region of operation of TFTs The voltage at which the region near the drain end is depleted of charge carriers is known as pinch off voltage. Once the drain bias is above the pinch off voltage, the drain current remains essentially constant with the further increase in drain voltage and the device is said to be operating in saturation regime. Depending on whether the gate voltage is required to induce the channel, the operation of TFTs can be classified as depletion mode or enhancement mode. In case of enhancement mode, channel conductance is low when no gate voltage is applied. 36

52 Therefore, a gate voltage is required to enhance the conductive channel between the source and drain. Such devices are normally off devices. While, in depletion mode TFTs, a conductive channel is already present even for the zero gate bias. Thus, a gate voltage has to be applied to deplete the channel and turn the device off and generally known as normally on devices. It should be noted that depending on the polarity of the gate voltage, an applied voltage could either enhance or deplete the concentration of the carrier in the channel region. Enhancement mode TFTs are usually preferred since no gate voltage is required to turn the device off which greatly simplifies the circuit design and minimize the power dissipation. Considering TFT in an ideal condition with no traps, the TFT would operate in depletion mode since there are bulk carriers available for conduction even at zero bias. However, in real case there are always empty traps which need to be filled with carriers before an accumulation layer is formed and hence giving rise to enhancementmode operation of the TFT. 37

53 Chapter 2 2. Experimental Procedures and Characterization Methods 2.1 Transmission Line Measurement Transmission line measurement (TLM) is one of the most widely used method for determining the Ohmic contact resistance and sheet resistance which is based on the measurement of the resistance between two adjacent pads of width W separated by a varying distance d1, d2, d3 etc [79]. Figure 2-1:TLM structure showing metal contacts with different spacing 38

54 Figure 2-2: Resistance versus metal contact spacing to extract sheet resistance From fig 2-1, the resistance between the two adjacent pads is given by R T 2 R R (21) C semi Where RC is the contact resistance, RSemi is the resistance due to the semiconductor material which can be given by L RSemi R (22) S W RS is the resistivity of the semiconductor material. The contact resistance and the sheet resistance of the semiconductor material can be extracted from the y intercept and slope of the linear fit of equation Capacitance-Voltage Characteristics C-V analysis is considered as one of the important electrical characterization technique for metal-oxide-semiconductor (MOS) systems. The shape of a typical C-V characteristics of a MOS capacitor depends on the type of substrate. One can extract several 39

55 parameters such as gate oxide thickness, substrate doping concentration, fixed oxide charge, interface trap density, threshold voltage, and flat band voltage. Figure 2-3: C-V characteristics of MOS capacitor showing accumulation, depletion and inversion regime The C-V measurement is done by superimposing a small amplitude ac voltage v on the dc bias V. The ac voltage is a small sinusoidal signal with frequency typically 10 KHz to 1 MHz and 10 to 20 mv amplitude. The capacitance of the MOS structure depends upon the voltage applied on the gate with respect to the semiconductor and the frequency. A typical C-V characteristics of the n type MOS capacitor comprises three operation regime namely accumulation, depletion and inversion. In accumulation region, the carriers of same 40

56 type as the body accumulates at the interface of the oxide and semiconductor [68]. For n type body, electrons are accumulated at the surface and the MOS structure behaves like a parallel plate capacitor with the capacitance being at the maximum value and gives the oxide capacitance (COX) which can be written as A C ox t (23) From the above equation, the oxide thickness for a relatively thick oxide greater than 50 Å can be extracted. However for a thin oxide less than 50 Å, the C-V curve doesn t flatten out in the accumulation region and hence actual and the measured capacitance differs resulting in the inaccuracy in the oxide thickness. Also, the equivalent oxide thickness can be calculated from the accumulation capacitance. The equivalent oxide thickness of a given dielectric is defined as the thickness of SiO2 layer that would be required to achieve the same capacitance as the high k dielectric under consideration. It can be expressed by the following equation t EOT k k SiO high k 2 t (24) high k EOT is most commonly used to describe the performance of the high k dielectric compared to silicon dioxide. When the gate voltage decreases, the surface become depleted of carriers leaving only a space charge or depletion layer. In this case, the total capacitance of the MOS is due to the depletion layer capacitance, CD and the oxide capacitance COX which is given by the following equation [68]: 41

57 C ox D (25) C C ox C C D As the gate voltage is decreased below the flat band voltage, more electrons are pushed away from the surface exposing more fixed positive ions leading to a positive charge being induced at the semiconductor and oxide interface. The thickness of such depletion layer increases with the decrease in gate voltage since more electrons will be pushed away creating thicker depletion layer. Therefore the capacitance decreases as the gate voltage is decreased. The flat band voltage separate the accumulation regime from the depletion and is defined as the voltage there is no band bending and no charge on the plates of the capacitor resulting in zero electric field across the oxide. The flat band voltage, VFB can be expressed as [68, 80] V FB Q i ms (26) Cox Where Фms is the work function difference between the metal and semiconductor and Qi the interface charge. As the thickness of depletion layer increases, the depletion capacitance decreases leading to the total capacitance decrease with the decrease in the gate voltage. The capacitance decreases until it reached inversion at which the concentration of hole in the surface becomes so large such that it exceed the concentration of electrons in the bulk of semiconductor. As a result, the conductivity of semiconductor surface is inverted. The voltage at which depletion regime changes to inversion regime is known as threshold voltage. The VT can be given by the following equation [80]: 42

58 V T Q Q (27) i d ms 2 Cox Cox F It should be noted that at the onset of inversion, the depletion layer thickness reaches its maximum value, WDM and hence the capacitance is minimum which can be expressed as C i s min (28) sd iwdm Once the MOS capacitor has reached at its inversion operation regime, the total capacitance is the series combination of oxide capacitance and series capacitance. After inversion, the capacitance depends on the frequency of measurement if they are made at high frequency (typically 1MHz) or low (1-100Hz). At low frequency, there is enough time for the minority carrier generation and could form the inversion layer. Therefore the total capacitance increases due to the increase in inversion charge and reaches back to the maximum value of the capacitance [80]. On the other hand, when the measurement is done at high frequency, the minority carriers in the inversion layer cannot follow the ac response and hence doesn t contribute to the total capacitance. As a result, the capacitance is at its minimum value corresponding to a maximum depletion width and stays constant even if the gate voltage is further decreased [80]. The substrate doping concentration, N, can be determined from the slope of the 1/C 2 vs V using the following equation [68,80]: 43

59 N 2 2 (29) 2 1/ C q s A d( ) dv Where A is the area, q is the electronic charge. The VFB can be determined from the C-V curve. The real value of the flatband capacitance can be calculated using the following equation: C FB i s (30) kt d s s i 2 N q A Once the CFB is known, VFB can be easily found by looking for the VGS that corresponds to CFB. The main drawback of this method is that this method becomes invalid when the Dit is very large ev -1 cm -2. Flat band voltage can be obtained from the intercept of the 1/C 2 vs V plot on the x axis. Structural Characterization 2.2 X-Ray Diffraction XRD is one of the most commonly used structural characterization technique used for phase identification of a crystalline materials including the lattice parameters, grain size, preferred crystal orientation, residual stress based on their diffraction pattern. The XRD technique is based on the constructive interference of the X-rays diffracted by a crystals. 44

60 When an incident parallel beam of X-ray impinges on the crystalline plane separate by a distance d at an angle θ as shown in fig 2-4, the diffracted ray produces constructive interference when the conditions satisfy Bragg s law 2 dsin n (31) where θ is the incident angle between the incident X- rays and the atomic plane, n is an integer and λ is the wavelength of X-rays. Figure 2-4: Bragg s law reflection: The Bragg s law relates the wavelength of the incident x-rays to the angle of diffraction and the lattice spacing. These diffracted rays are detected, processed and counted which results in a peak in the diffraction intensity pattern. All the possible diffraction direction of the lattice is needed which depend on the size and the shape of the unit cell of the material. Since the diffraction pattern can be converted to d spacing which is unique for a given crystalline materials and hence helps in the identification of the materials. 45

61 The conventional XRD measurement also called Bragg-Brentano (also called θ-2θ) scanning method, the X-ray incidence angle equals the angle of the diffracted beam with respect to the inspected sample surface. In this method, the penetration depth of the x-ray is much greater than film thickness. Therefore this conventional XRD θ-2θ scanning method is convenient to use for the film with a thickness of the order of 5-10 µm. The conventional XRD measurement also called Bragg-Brentano (also called θ-2θ) scanning method is usually not suitable for the thin film since this method generally produces a weak signal from the film and the intense signal from the substrate [81]. Such limitation of the Bragg-Brentano scanning is overcome by using grazing incidence XRD configuration. In this configuration, the incidence angle is kept fixed at a small angle which is slightly above the critical angle for the total internal reflection of the film material and the angle between the incident beam and the diffracted beam is varied by moving the detector arm. The typical value of incidence angle 1 and 3 o [81]. The idea behind using the fixed and small incident angle is to increase the path length of the X-ray beam through the film which in turn increases the diffracted intensity while at the same time reduces the signal from the substrate due to the small angle of incidence. As a result, there is a dramatic increase in the film signal to the background ratio making possible for the XRD measurement of the thin film. The crystalline grain size is calculated using the Scherrer formula given in Eq. 32 [82]: 0.94 D (32) cos 1/ 2 B 46

62 where D is the crystallite grain size, λ the X-ray wavelength, θ the Bragg diffraction angle, and β1/2 the peak width at half maximum (FWHM). In this study, the crystallinity and orientation of ZnO thin film were studied by glancing incidence XRD using a Rigaku Ultima III x-ray diffractometer. 2.3 Atomic Force Microscopy AFM is one of the powerful structural techniques that can analyze the surface topography of the sample with very high resolution within the atomic limit. In addition to surface image, AFM can also be used to analyze the surface parameters such as surface roughness, grain size. Unlike other electron microscope, AFM can be used for imaging wide variety of samples including biological, samples in aqueous medium. Figure 2-5: AFM working principle set up The operating principle of AFM is based on the measurement of the force between the probe and the sample. When a cantilever tip is brought close to a sample surface, the 47

63 attractive force between the tip and the surface causes the deflection of the cantilever given by the Hook s law, F=-Kx, where K is the spring constant and x is the deflection of the cantilever. The deflection of the cantilever is measured by pointing the laser at the tip which is reflected and get collected into the array of photodiodes as shown in fig 2-5. This information of the cantilever deflection is used to recreate an image of the surface [83]. The AFM can be operated in a number of modes such as contact, tapping and non-contact depending upon the applications and samples type. In contact mode, the cantilever tip makes a soft contact with the sample and the feedback loop is used to maintain the cantilever deflection constant by adjusting the voltage applied to the scanner. The contact mode has the advantage of high scan speed, however, it can damage the samples. In tapping mode, the cantilever tip is alternately in contact with the surface to provide high resolution image and then lifted the tip off the surface to avoid the sample surface damage. Tapping mode is the most commonly used since it provides high resolution image without damaging the surface. In non-contact mode, the cantilever doesn t make any contact with the sample surface, however the tip hovers angstrom above the sample surface. In this work the surface morphology and the surface roughness of the ZnO was studied by AFM in tapping mode using a Veeco Nanoscope V. 2.4 Scanning Electron Microscope SEM is a technique for a high resolution imaging of the surfaces by scanning with focused beam of high energy electron in a raster pattern. When an incident beam of electrons strike the samples, a variety of signals including secondary electrons, backscattered electrons, diffracted backscattered electrons and X-rays are generated due to 48

64 elastic and inelastic scattering. It is the secondary electrons which are ejected from the atoms on the surface upon the electron beam incidence, produces the image of the surface. Figure 2-6: SEM working principle set up While the backscattered electron are the electron reflected from the sample surface and diffracted backscattered electrons contain the information about distribution of different element in the sample along with the crystal structures and orientation. Similarly, the incident electron beam can remove the inner shell electron of atoms in the sample which 49

65 is filled by outer shell high energy electrons resulting in the emission of X-rays. These emitted X-rays are characteristics of a given element and therefore it can provide quantitative analysis of a sample [84]. 2.5 Transmission Electron Microscope (TEM) TEM is another type of electron microscope in which a beam of electrons is transmitted through very thin specimen carries the information about the information about the structure of the specimen [85, 86]. The interaction between electron beam and thin sample produces secondary electrons and backscattered electrons produces an image which is magnified and focused onto an imaging devices such as fluorescent screen or detected by the sensor such as CCD camera. TEM provides a high resolution image of the microstructure of a thin sample due to the small de Broglie wavelength of the electrons. The de Broglie wavelength of an electron accelerated under the applied field V is given by [85, 86] h (33) E 2m0E(1 ) 2 2m c 0 Where h is Planck s constant, m0 is the rest mass of an electron and E is the energy of the accelerated electron. In order to achieve the high resolution TEM images, the samples need to be thin enough on the order of few hundred of nanometer so that significant number of electrons can pass through the sample. The thinning of the sample was accomplished by ion milling process in focused ion beam (FIB). 50

66 2.6 RF Sputtering Sputtering deposition is a type of physical vapor deposition method for the thin film deposition. This method is based upon the bombardment of the target with high energetic species such as argon which leads to the deposition of thin film of target material on the substrate. Sputtering is one of the most widely used method for thin film deposition due to the several features including better step coverage, better adhesion on the substrate, high deposition rate, excellent uniformity on large area substrates, low temperature deposition [87,88]. In dc sputtering, the sputtering target is the cathode electrode while the substrate is placed on the anode which is often at ground potential. The applied potential appears across a region very near the cathode, and the plasma generation region is near the cathode surface. The cathode in dc discharge must be an electrical conductor, since an insulating surface will develop a surface charge that will prevent ion bombardment of the surface [89]. Figure 2-7: RF sputtering set up 51

67 This condition implies that dc sputtering must be used to sputter simple electrically conductive materials such as metals, although the process is rather slow and expensive compared to vacuum deposition. An advantage of dc sputtering is that the plasma can be established uniformly over a large area, so that a solid large-area vaporization source can be established. On the other hand, in dc sputtering the electrons that are ejected from the cathode are accelerated away from the cathode and are not efficiently used for sustaining the discharge. To avoid this effect, a magnetic field is added to the dc sputtering system that can deflect the electrons to near the target surface, and with appropriate arrangement of the magnets, the electrons can be made to circulate on a closed path on the target surface. The principle is that the cathode surface is immersed in a magnetic field such that electron traps are created so that E x B drift currents close in on themselves. This high current of electrons creates high-density plasma and hence increase the probability of an ionizing electron collision occurring-atom number of electrons that can take part in the ionization of Ar, from which ions can be extracted to sputter the target material, producing a magnetron sputter configuration [90]. This lead to the higher deposition rate on the substrate even at the lower pressure (typically, 10~3 mbar, compared to 10~2 mbar) and lower operating voltage ( V as compared with several kv). RF sputtering technique provides deposition of high quality thin films of various metals, insulators and semiconductors [90]. RF sputtering allows the deposition of compounds thin film of insulators such as SiO2, HfO2 etc by a technique known as reactive sputtering in which the chemical reaction between the target material and reactive gases such as O2, N2 takes place in the presence of Ar at a certain temperature. The reactive sputtering is mainly used for the deposition of 52

68 oxide, nitride and carbide thin film and the stoichiometry of such film is controlled by optimizing the several deposition parameters including RF power, pressure, temperature and reactive gases flow. 2.7 Photolithography It is the process of transferring the pattern on the mask to the surface of substrate using the ultraviolet light. It involves a series of steps which are described below: 1) Substrate cleaning: The substrate needs to be cleaned in order to remove organic or inorganic contaminants. Typically cleaning is performed by wet chemical treatment with acetone, methanol followed by rinsing with DI water. The substrate is then heated on the hot plate at 115 o C for 5 minutes to drive off any moisture that may be presented on the substrate surface. 2) HMDS priming: Before coating the photoresist, the adhesion promoter such as HMDS is applied either by vapor priming or liquid priming to improve the adhesion of the photoresist to the substrate. 3) Photoresist coating: The photoresist is applied on the substrate by spin coating which produces the uniform thin layer of 1-3 µm depending on the spinning speed and the percentage solid content of the photoresist. The photoresist coated wafer is then soft bake at o C on a hot plate for 60 seconds in order to drive off excess solvent from the resist. 4) Exposure and developing: Once the substrate has been coated with the resist, the substrate is exposed through the pattern on the mask with a high intensity ultraviolet light. This exposure causes a chemical change in the resist. After exposure, the substrate is immersed in a developer solution which dissolves areas of the 53

69 photoresist that were exposed to light for the photoresist while the unexposed areas are dissolved for the negative photoresist. 5) Hard bake: after development, the substrate is hard baked in an oven or hot plate at o C for minutes in order to solidify the remaining resist and drive off the solvent from the substrate surface. 2.7 Lift off It is the most common and easy method of patterning deposited films when the etching is not preferred due to the poor selectivity between the mask and the deposited film. This process is usually the subsequent process step after photolithography. In this process, a pattern is defined on the substrate using the photoresist and standard photolithography process such that photoresist can be removed from the area in which metal is to be deposited while the other area is covered with the photoresist. Next, the metal is deposited over entire surface of the substrate using evaporation or sputtering. The substrate is then immersed in the solvent usually acetone or PG remover in ultrasonic bath which remove the photoresist along with the metal leaving only the film which was deposited directly on the substrate. It should be noted that only film which can be deposited at temperature below the temperature at which photoresist get burned can be patterned by lift off. 54

70 Chapter 3 3. Electrical Characteristics of RF Sputtered ZnO/HfO2 Interfaces in Transparent Thin Film Transistors 3.1 Introduction ZnO based thin film transistors (TFTs) have received much attention due to wide direct band gap of 3.37 ev, high electron mobility, high transparency in the visible range ( nm), low temperature synthesis and thermal stability [87, 88]. In the past few years, much of the research efforts have been inclined towards the integration of high-k gate dielectric material in ZnO TFTs in an attempt to improve the carrier mobility, decrease the gate leakage current, and improve the overall device performance. Among several highk dielectrics, HfO2 is promising due to its high dielectric constant (20-25), wide band gap (5.6 ev), and reasonable band-offset with ZnO. However, the performance of the TFTs is largely limited by the quality of the gate dielectric and high interface trap density at the interfaces between HfO2 and ZnO layer [89]. Therefore, the study of the interface properties between ZnO and high-k dielectrics such as HfO2 is essential to improve the TFT performance. To reduce trap density, a thin MgO interfacial layer between HfO2 and ZnO is studied. MgO is a high-k dielectric (k = ) with wide band gap (7.7 ev) and 55

71 good chemical stability [90]. It is reported to reduce the grain boundaries in the ZnO film due to excess oxygen ions [90]. In addition, MgO has a high tolerance for plasma ion bombardment which can effectively minimize the defect density in the ZnO layer during depositions using sputtering. Since the 1960s, ITO has dominated as the key transparent electrode for display technologies such as LCD, OLED, plasma, electroluminescent, and electrochromatic displays, as well as in a number of touch screen technologies. However indium being a rare earth metal make ITO expensive which demands to look for an alternative to ITO which is low cost and abundant. Fluorine doped tin oxide (FTO) is considered as a potential alternative to ITO since it is cheaper as well as chemically and thermally stable. Moreover, unlike ITO, FTO can retain its optoelectronics properties even at high temperature Though there have been previous studies of ZnO/HfO2 TFT fabricated using a combination of Atomic Layer Deposition (ALD), Pulsed layer Deposition (PLD), and other techniques [91, 92], our knowledge on the characteristic of interfaces formed between ZnO and HfO2 when both materials are sputtered is limited. It should be noted that sputtering technique offers advantages in terms of ability to deposit materials at lowtemperature on desired substrate such as glass and plastics, and large-area scalability. However, low-temperature deposition can also introduce unique defects in high-k and ZnO and their interface which needs to be better understood. In this work, we have studied the interface properties of the RF sputtered ZnO (sputtered at room temperature) with HfO2 (reactively sputtered at 300 O C) using electrical characterization techniques including dc current-voltage, capacitance-voltage (C-V) and 56

72 admittance spectroscopy (Gp/ω vs. ω ) measurements in thin film transistors (TFTs) structures. Also, to minimize the interface the interface trap density, a thin layer of MgO between ZnO and HfO2 has been studied. 3.2 Experimental Procedures Figure 3-1: Schematic cross-section view of ZnO TFTs structure (a) sample A (b) Sample B (c) Sample C The schematic diagram of the fabricated bottom gate TFT device structure is shown in figure 3-1. Three samples with 50 nm ZnO channel layer and HfO2 gate dielectric on Si substrate (sample A), on fluorine doped tin oxide (FTO ) substrate (sample B) and 10 nm MgO interfacial layer between ZnO and HfO2 layers (sample C) were fabricated. To realize transparent ZnO TFTs, FTO was chosen as opposed to commonly used indium tin oxide (ITO) as a gate electrode. The motivation behind choosing FTO is due to its cost effectiveness, stability, and scalability for large area transparent electronics applications. To fabricate sample A, first, a 3 nm Ti layer was deposited on Si as an adhesion layer followed by the deposition of 100 nm of Ru as a bottom gate contact. Next, 100 nm HfO2 was deposited using Hf target at 100 W by reactive sputtering of Hf in 20 % oxygen at C. Thereafter, ZnO channel layer was deposited using a ZnO target at 100 W at room 57

73 temperature. Finally, 100 nm Al capped with 70 nm W as a source and drain electrode were deposited and defined by photolithography and lift-off patterning. The channel width and length of the device were 200 μm and 10 μm respectively. To fabricate sample B, HfO2 was deposited as sample A, however, on FTO glass substrates obtained from Pilkington North America. All others layers are deposited as in sample A. Likewise, sample C was fabricated same as sample B except for the MgO layer which was deposited by reactive sputtering of Mg in 20 % oxygen at C. The electrical characterization was done on LakeShore probe station using Keithley 4200 semiconductor characterization system. 3.3 Results and Discussions Fig 3-2 shows the IDS-VDS characteristics of the samples A, B and C respectively. It can be observed that for a given gate bias, the drain current IDS increases with the VDS which indicates TFTs device exhibit n-channel enhancement mode characteristics. The transfer characteristics (drain current (IDS) vs. gate voltage (VGS)) of the sample A, B and C are shown in the figure 3-3. The extracted field effect mobility, threshold voltage, on-off ratio and subthreshold swing from the transfer curve have been presented in table 3 for samples A, B and C. The maximum density of interface states (N SS max ) at ZnO and gate dielectric interface can be estimated from the subthreshold swing (S) using equation (30): 58

74 SS N max S log (e) = [ ( kt 1] C ox q) q (34) Where Cox is the oxide capacitance per unit area and is determined from the maximum accumulation capacitance from the measured C-V (shown in figure 3-4). 59

75 Sample A I D (A) V 10 V 12 V 14 V V (V) DS Sample B I D (A) V 4 V 5 V 6 V 7 V V DS (V) 60

76 Sample C I D (A) V DS (V) 4 V 6 V 8 V 10 V 12 V Figure 3-2: ID-VDS characteristics of samples A, B and C I D (A) Sample A V =4 V D V (V) G 61

77 V D =4 V Sample B I D (A) V G (V) I D (A) Sample C V =4 V D V (V) G Figure 3-3:ID-VGS(transfer) characteristics of samples A, B and C 62

78 Table 3: Summary of ZnO based TFTs performance Sample Vth(V) μ(cm 2 V -1 s -1 On-off SS(V/decade SS N max NGB ) ratio ) (ev- 1 cm -2 ) (cm -2 ) A B C SS The N max was found to be ev -1 cm -2 for sample A while it was ev -1 cm -2 for sample B and ev -1 cm -2 for sample C. Again, one can observe SS a high N max for all samples, which could be due to poor quality of ZnO due to sputter deposition at room temperature. Also, the grain boundaries within the bulk ZnO layer or at ZnO/gate dielectric interface contribute to the interface trap states. The NGB can be determined from Levinson s model using the plot of ln (IDS/VGS) as a function of 1/VGS from the following equation [93] N GB = ( C ox ) slope (35) q The NGB was found to be cm -2 for sample A as compared to cm -2 for sample B. While the sample C had the least NGB of cm -2 indicating insertion of MgO layer between ZnO and HfO2 layers helps in reduction of grain boundaries in the ZnO film. This can be attributed to compensation of defects such as 63

79 oxygen vacancies in ZnO film with MgO excess oxygen ions as reported in the literature. From table 3, it can be observed that mobility decreases by introducing FTO as gate electrode over Ru possibly due to diffusion of fluorine into HfO2 degrading the quality of gate dielectric and generating more interface states and bulk defects. This is further supported by increase in gate leakage current (IG) in sample B as compared to sample A (shown in figure 3-5). Furthermore, on FTO electrodes, mobility was observed to be lower with MgO which could be due to the accumulation of more electrons at ZnO/MgO interface as suggested by the least Vth for sample C, increasing the scattering of electrons in the MgO layer or at interfaces. Also, this mobility degradation can be possibly due to remote surface roughness scattering. The on/off ratio was improved in sample C which could be SS attributed to reduced N max and gate leakage current. Figure 3-4 shows C-V responses between gate and source/drain electrode measured at 1 MHz. A well behaved C-V was observed for all three samples indicating n-type characteristics of ZnO. From accumulation region of C-V, an effective oxide thickness (EOT) of ~17.59 nm can be calculated for samples A and B, and ~23 nm for sample C. 64

80 Capacitance (F) 9 x x x x x Sample A Sample B sample C 4 x Voltage(V) Figure 3-4: C-V characteristics of samples A, B and C I G (A) 1 x x x x x 10-8 V D =4 V 1 x 10-9 Sample A 1 x Sample B Sample C 1 x V G (V) Figure 3-5: Gate leakage characteristics of samples A, B and C In order to characterize Dit, frequency dependent conductance method was employed. In this technique, conductance was measured as a function of bias voltage and frequency by applying bias on the gate and grounding the source in two terminal metal- 65

81 oxide-semiconductors (MOS) configuration. The equivalent parallel conductance (Gp) can be written in terms of measured capacitance Cm and conductance Gm as [94]: G p ω = ω 2 C 2 ox G m (36) G 2 m +ω 2 (C ox C m ) 2 Where ω is 2πf, f is measurement frequency, Cox is gate oxide capacitance. Figure 3-6 shows Gp/ω as a function of frequency plot for different gate bias. 66

82 Gp/ 5 x x x x x Sample A Frequency (Hz) 9 V 8.9 V 8.8 V 8.7 V 8.6 V 8.5 V 8.4 V Gp/ 2.5 x x x x x Sample B Frequency(Hz) 3 V 2.75 V 2.5 V 2.25 V 2 V 1.75 V 1.5 V Sample C 1.5 x G p / 1 x x Frequency (Hz) 1 V 1.25 V 1.5 V 1.75 V 2 V 2.25 V 2.5 V 2.75 V 3 V Figure 3-6:Gp/ω as a function of radial frequency at different gate bias. As can be seen in figure 3-6, the plot gives rise to a peak for each bias which shifts to higher frequency with bias voltage. The origin of this peak can be ascribed to presence of uniformly distributed interface charge at the interface of ZnO layer and gate dielectric and its shifting with voltage bias indicates the movement of Fermi level across the band gap. The peak in Gp/ω- log (f) plot shows a maximum value at ωτ = 1.98 and substituting this value in Eq. 36, Dit can be determined from equation: 67

83 D it 2.5 (Gp ω ) max Aq (37) Where q is the electronic charge, Gp/ω max is the peak loss value and A is the area. The relationship between the frequency f at which Gp /ω peaks and the characteristic time constant of the trap is used to determine Dit distribution (energy with respect to the majority carrier band edge) of Dit. The energy level ΔE (EC-ET) of the traps below the ZnO conduction band edge (Ec) is related to frequency by Shockley Read Hall statistics of capture and emission rates expressed as [95]: D it (ev -1 cm -2 ) 8 x x x x x x x x Sample C Sample A Sample B E -E (ev) C T Figure3-7: Interface state density as a function of trap energy level for samples A, B and C 68

84 f = 1 = V thσn exp [ ΔE 2πτ 2π k B T ] (38) Where Vth is average thermal velocity of majority carriers, N the effective density of states in ZnO conduction band, σ the capture cross section of trap state, kb the Boltzmann constant and T the temperature. The Dit value from equation 37 was used to determine distribution of Dit as a function of ΔE. By assigning T=300 K, Vth= cms -1, σ= cm -2 [96], and N= cm -3, Dit for the energy level ev below ZnO EC was estimated as shown in figure 3-7. It can be seen that Dit decreases with energy below EC. The Dit for sample B is greater than sample A even though both the samples have same stack except for gate electrode. This could possibly be due to the diffusion of fluorine from FTO into the HfO2 during its deposition at 300 o C. It can be observed that with addition of MgO interfacial layer between HfO2 and ZnO layers in sample C, there is a reduction of Dit by almost one order of magnitude compared to sample B which could be attributed to compensation of defects in ZnO layer. 3.4 Conclusions In conclusions, Dit and its distribution with the trap energy level was estimated using the admittance spectroscopy technique. The Dit at ZnO/HfO2 interface determined from Gp/ω-ω plot was found to be on the order ev -1 cm -2 which is in close agreement with the value extracted from subthreshold behavior of the TFTs. The interfacial layer of MgO between ZnO and HfO2 tends to reduce Dit by almost one order of magnitude which could be attributed to compensation of defects by excess oxygen in MgO layer. The 69

85 defect states within the grain boundary of the polycrystalline ZnO is calculated using the subthreshold behavior. Energy distribution of Dit indicated a decreasing trend away from conduction band edge. 70

86 Chapter 4 4: Understanding the Effect of MgO Interfacial Layer on ZnO/High-k/FTO Transparent Thin Film Transistors for Large-Area Transparent Electronics Applications 4.1 Introduction ZnO based thin film transistors have attracted considerable attention due to its high mobility, high transparency in visible range, high stability, low temperature synthesis making it compatible for flexible substrates. In order to improve the performance of the ZnO based TFTs, several high-k dielectric has been investigated. The high-k dielectric reduces the operating voltage due to improved capacitive coupling of gate electrode to channel resulting in accumulation of sufficient number of charges in the channel layer. HfO2 is one of the most promising high-k dielectric due to its high dielectric constant (20-25), large band gap (5.68 ev) and reasonable positive band offset with ZnO. However, integration of high-k dielectric in ZnO TFTs suffers from high interface state density and large leakage current density. Chang et al reported improved device performance of ZnO 71

87 TFTs by inserting Al2O3 interfacial layer at ZnO/HfO2 interface [88]. They attributed the suppression of interface trap density for the improvement in TFTs performance. Similarly Su et al employed thin layer of SiO2 between HfO2 and a-igzo to reduce the interface trap density and hence improve the device performance [96]. Motivated by this, we used MgO interfacial layer between ZnO and HfO2 in an attempt to reduce the interface trap density and improve the device performance. MgO is a high-k dielectric (k = ) with band gap of 7.7 ev and good chemical stability. MgO is reported to reduce defects such as oxygen vacancies in the ZnO layer due to its excess oxygen ions [90]. Moreover, MgO has a high tolerance for plasma ion bombardment which can effectively reduce the damage to the channel-insulator interface during the deposition of the ZnO film. A moderate thickness of MgO can effectively reduce the interface trap density and can improve the channel/dielectric interface. In this work, we have investigated the different thickness of MgO interfacial layer between ZnO/HfO2 in order to minimize the interface trap density. ZnO based TFTs have been widely studied for transparent electronics applications. However, majority of the previous work have evaluated the performance of TFT using Indium Tin Oxide (ITO) as transparent gate electrodes which is expensive and may not be sustainable for large-area transparent electronics applications, such as transparent electronics integrated glass windows and glass walls in building. In addition, replacing ITO with low-cost and scalable material such as Fluorine-Doped Tin Oxide (FTO) coated glass substrates also has potential to reduce the cost of displays in consumer electronic devices. Towards addressing this issue and extending the application of ZnO-TFTs in large-area transparent electronics that is cost-effective and sustainable, we have evaluated the performance of ZnO TFTs with commercially available FTO as gate. 72

88 4.2 Experimental Procedures The schematic diagram of the bottom gate TFT fabricated on FTO glass substrate has been shown in figure 4-1. Firstly FTO glass substrate was cleaned in acetone, isopropanol and DI water in ultrasonic bath. A 100 nm of HfO2 was deposited using Hf target at input power of 100 W by reactive sputtering of Hf in 20 % oxygen at C. Thereafter, MgO interfacial layer was deposited on top of HfO2 at 50 W by reactive sputtering of Mg in 20 % oxygen at C. The MgO interfacial layer thickness were 5 nm (sample A), 10 nm (sample B), 15 nm (sample C) and 20 nm (sample D). ZnO channel layer was deposited using a ZnO target at 100 W at room temperature. Finally, 100 nm Al capped with 70 nm W as a source and drain electrode were deposited and defined by photolithography and lift-off patterning. The channel width and length of the device were 200 μm and 10 μm respectively. The electrical characterization of the so fabricated samples was done on LakeShore probe station and the data were collected using Keithley 4200 semiconductor characterization system. 73

89 Figure 4-1: Schematic cross section view of ZnO TFTs structure 4.3 Results and Discussions Figure 4-2 shows the output characteristics of the TFTs with different thickness of MgO interfacial layer. It can be observed that TFTs device exhibit n-channel enhancement mode characteristics. Good current saturation with source to drain current IDS=1.17, 20, 0.96, 0.19 μa at gate voltage VGS=12 V and VDS=5 V were obtained for samples A, B, C and D respectively. 74

90 1.5 x 10-6 Sample A I DS (A) 1 x x V 8 V 10 V 12 V 14 V V DS (V) Sample B I DS (A) V 6 V V 10 V 12 V V DS (V) 75

91 1.2 x 10-6 Sample C 1 x 10-6 I DS (A) 8 x x x V 8 V 10 V 12 V 14 V 2 x V DS (V) I DS (A) 3.5 x x x x x x x 10-8 Sample D V DS (V) 6 V 8 V 10 V 12 V 14 V Figure 4-2: ID-VDS characteristics of samples A, B, C and D Figure 4-3 shows the gate leakage characteristics of the samples A, B, C and D at VDS=4 V. The leakage current densities of samples A, B, C and D are , , and A at 10 V respectively. It can be observed that leakage current decreases with MgO interfacial layer thickness when we consider sample A, C and D. However it can be seen that sample B showed the least leakage current suggesting that 10 nm of MgO interfacial layer is the optimum thickness that could effectively suppress 76

92 pinholes within the film and at the ZnO/HfO2 interface. Also, there is a rapid increase of gate leakage current with the applied bias when the MgO interfacial layer gets thicker. This could possibly due to the generation of more defects within the bulk of MgO with increasing thickness. IG(A) 1 x x x x x x x Sample A Sample B Sample C Sample D 1 x VG(V) Figure 4-3: Gate leakage characteristics of samples A, B, C and D ID(A) Sample B 10-6 Sample A Sample C 10-7 Sample D VG(V) Figure 4-4: Transfer characteristics of samples A, B, C and D 77

93 Figure 4-4 shows the transfer characteristics of ZnO TFTs with different MgO interfacial layer thickness at VDS=4 V. The operation of TFTs in the saturation region can be modeled by the equation: I DS W C 2L i 2 ( VGS VTH ) V for DS VGS VTH [39] Where W is the channel width, L is the channel length, μ is the field effect mobility, Ci is the gate insulator capacitance per unit area, VTH is the threshold voltage. The threshold voltage can be extracted from the x-axis intercept while the field effect mobility can be obtained from the slope of square root of IDS vs VGS plot. The subthreshold voltage swing (SS) can be defined as the gate voltage required to increase the drain current by a factor of 10 and can be determined from the transfer characteristics using the relation: dvgs SS d(logi DS ) [40] The electrical performance of all the fabricated samples has been summarized in table 4. One can observe that sample B shows improved mobility and threshold voltage 78

94 compared to sample A which could be attributed to improved interface between ZnO and MgO. This can be explained by the fact that 5 nm MgO interfacial layer in sample A is too thin to effectively reduce the defects within the bulk of MgO and at ZnO/HfO2 interface. Furthermore, the larger off current in sample B compared to sample A as seen in figure 4-3 implies that interface properties has been improved. The high threshold voltage and low field effect mobility in sample D compared to sample C further indicates that interface properties of MgO/ZnO get deteriorated with increase in MgO thickness. In addition, this could be attributed to more fixed oxide charge with greater thickness of MgO interfacial layer. Moreover, the increasing thickness of MgO might have resulted in increased roughness inducing high interface defects and surface scattering. The sample B shows the highest on/off ratio of 10 6 while sample A and C has the same values of The highest on/off ratio in sample B could be attributed to low gate leakage current. The least on/off ratio of was observed in sample D which is caused by the reduced on current as seen in figure 4-4 due to decrease in capacitance. Table 4:ZnO TFTs performance summary with different MgO interfacial thickness Samples Vth(V) μ (cm 2 /V.s) On/off ratio SS (V/decade) A B C D

95 Fig 4-5 shows the C-V response between the gate and source/drain electrode of samples A, B C and D measured at 1 MHZ frequency. A well behaved C-V characteristic with accumulation in positive gate bias was obtained indicating the n channel behavior of ZnO. Capacitance (F) 1 x x x x x x x Sample A Sample B Sample C Sample D 3 x Voltage(V) Figure 4-5: C-V characteristics of samples A, B, C and D at 1 MHz An effective oxide thickness (EOT) was extracted from the accumulation capacitance and has been given in table 5. Also, the flat band voltage (VFB) can be extracted from the x intercept of 1/C 2 vs V plot measured at high frequency. The VFB for samples A, B, C and D has been given in table 5. The VFB was found to be decreasing with MgO interfacial layer thickness. Also one can observe that the C-V curve shifts to more positive bias voltage with increase in MgO interfacial layer thickness which implies the existence of negative fixed charge within the MgO and near ZnO/MgO interface. The physical origin of this negative fixed oxide charge could be attributed to excess oxygen at ZnO/MgO interface. 80

96 Table 5: Electrical parameters extracted from C-V characteristics Samples EOT (nm) VFB(V) A B C D In order to quantize interface trap density and its distribution, conductance method was employed. This method is based on analyzing the loss that is caused by the change in the trap level charge state. Figure 4-6 shows the Gp/ω vs f plot as a function of gate bias in the depletion regime and frequency for samples A, B, C and D. As can be seen in the figure, the plot gives rise to a Gp/ω peak for each gate bias which can be attributed to the presence of uniformly distributed interface charge at the interface of ZnO layer and gate dielectric. Also, the position of Gp/ω peak shifts as the gate bias changes which indicates that Fermi level moves efficiently between conduction band edge and midgap of ZnO. As it can be seen in the figure 4-6, there is a strong increase in conductance for frequencies greater than 10 KHz for thicker MgO interfacial layer which indicates that interface trap density increases with MgO thickness. 81

97 Gp/ 1.4 x 10-9 Sample A 1.2 x x x x x x Frequency (Hz) 2 V 2.25 V 2.5 V 2.75 V 3 V 3.25 V 3.5 V 3.75 V 4 V 2.5 x Sample B G p / 2 x x x x V 4.25 V 4.5 V 4.75 V 5 V 5.25 V 5.5 V 5.75 V 6 V Frequency (Hz) 82

98 Gp/ 8 x Sample C 7 x x x x x x x Frequency (Hz) 6 V 6.25 V 6.5 V 6.75 V 7 V 7.25 V 7.5 V 7.75 V 8 V 1 x 10-9 Sample D Gp/ 8 x x x x Frequency (Hz) 4 V 4.25 V 4.5 V 4.75 V 5 V 5.25 V 5.5 V 5.75 V 6 V Figure 4-6: Gp/W as a function of bias for samples A, B, C and D The energy level of the trap with respect to conduction band edge can be calculated from Shockley Read Hall statistics of capture and emission rates given by f 1 vth N E exp[ ] 2 2 k T B [41] Where f is the frequency at which Gp/ω peak occurs, τ is the characteristics time constant of the trap, vth is the average thermal velocity of majority carriers, N is the 83

99 effective density of states of majority carrier band, σ is the capture cross section of trap state, kb is the Boltzmann s constant and T is the temperature. By taking values T=300 K, vth= cms -1, σ= cm -2, and N= cm -3, Dit for the energy level ev below ZnO conduction band edge, EC was estimated as shown in figure 4-7. It can be observed that Dit decreases with energy below the conduction band edge. Furthermore it was found that Dit in sample B is reduced by almost one order of magnitude compared to sample C and D. However, there is no significant change in Dit for samples A, C and D. This further supports that a moderate thickness of MgO is able to suppress the defects within the bulk of MgO and at ZnO/HfO2 interface. However, with increase in MgO thickness, there are more defects in bulk which could easily propagate to the ZnO/MgO interface contributing to Dit. 84

100 D it (ev -1 cm -2 ) 3 x x x x x x Sample A Sample C Sample D Sample B E C -E T (ev) Figure 4-7: Interface state density as a function of trap energy level 4.4 Conclusions In conclusions, ZnO TFTs with HfO2 gate dielectric on FTO glass substrate were fabricated and characterized. The best device performance with field effect mobility of 0.3 cm 2 V -1 s -1, threshold voltage of 3.7 V and on/off ratio of 10 6 was obtained with 10 nm of MgO interfacial layer. These indicates that 10 nm of MgO interfacial layer between ZnO and HfO2 is the optimum thickness that could effectively suppress the defects within the MgO bulk and at ZnO/HfO2 interface for the conditions explored in this work. This optimum interfacial layer thickness can change as HfO2 or ZnO thickness or composition changes. The interface trap density determined from the conductance method was found to be on the order of ev -1 cm -2 in 10 nm MgO interfacial layer sample which is almost 85

101 one order of magnitude lower than other thicknesses of MgO interfacial layer. The interface state energy distribution ev below the conduction band edge of ZnO was also determined which showed decreasing trend of interface trap density away from conduction band edge. However, even with 10nm MgO, Dit is much higher than the desired values (<10 10 ev -1 cm -2 ). 86

102 Chapter 5 5: Effect of Deposition Temperature of ZnO Active Channel Layer on the Electrical Characteristics of ZnO TFTs 5.1 Introduction ZnO has been long considered as a promising materials for transparent electronics applications due to its wide band gap (3.37 ev), low processing temperature, and high transparency in the visible region. In addition, it has a high stability and can be grown as polycrystalline film even at room temperature on various substrates including plastics. All these aforementioned properties make ZnO as a promising active channel layer in transparent and flexible TFTs. In the past few years, the performance of ZnO based TFTs has improved significantly with field effect mobility and on/off ratio as high as 10 8 and 80 cm 2 V -1 s -1 respectively with the use of high-k dielectrics and novel TFTs device structure. Furthermore, the high-k dielectric reduce the operating voltage of ZnO TFTs due to the accumulation of sufficient number of charges in the channel caused by the enhanced capacitive coupling between the gate electrode and channel layer. Among several high-k dielectric, HfO2 is a promising one due to its high dielectric constant, large band gap with reasonable positive band offset with respect to ZnO conduction band edge, and high transparency in visible range and low leakage current. The performance of the ZnO based 87

103 TFTs is governed by several factors including the quality of gate dielectric and channel layer, interface between gate dielectric and channel. Among the several factors, the performance of the ZnO TFTs is heavily dependent on deposition temperature of channel layer. The electrical characteristics of TFTs is greatly influenced by the large number of grain boundaries due to the small grains of ZnO film. These grain boundary formed in the ZnO has the tendency to hinder the flow of carrier from grain to grain caused by its localized potential barriers. Therefore, it can be undoubtedly said that the microstructure of channel layer plays an important role in realizing high performance ZnO based TFTs. The performance of the TFTs could be improved by using good quality of polycrystalline ZnO film with a large grain size ZnO which is controlled by the deposition temperature of ZnO. Also, the carrier concentration of ZnO film which can be effectively controlled by deposition temperature, is a critical factor in determining the TFTs device characteristics. Furthermore, the intermixing could occur at the ZnO and gate dielectric interface during the deposition of ZnO film at different temperature and can degrade the quality of gate dielectric and channel layer interface and hence affect the performance of TFTs. with large grain size show reduced grain boundaries and can improve the device performance. Therefore, it is very much important to optimize the deposition temperature of ZnO that could achieve the high performance ZnO based TFTs. Although there have been previous studies which investigate the effect of deposition temperature of ZnO TFTs performance using other gate dielectrics, no systematic study have been done for ZnO TFTs when a high k gate dielectric HfO2 is used. In this work, we have investigated the effect of channel layer deposition temperature on microstructure of ZnO by different structural characterization techniques including AFM, XRD, and SEM. Also a 50 nm ZnO was 88

104 deposited at different temperature ranging from room temperature to 200 o C and the performance of ZnO based TFTs with respect to channel layer deposition temperature was studied in order to find out the optimum deposition temperature of active layer for high performance ZnO based TFTs with HfO2 as a high-k gate dielectric. 5.2 Experimental Procedures A bottom gate structure as shown in figure 5-1 was employed for TFTs fabrication. All the layers were deposited by RF sputtering. A 3nm of Ti adhesion promoting layer was deposited on the Si substrate followed by deposition of 100 nm Ru as a back gate electrode. Thereafter, 100 nm thick HfO2 gate insulator was deposited from Hf target by reactive sputtering Hf in presence of 20% oxygen at RF power of 100 W and temperature of 300 o C. A 50 nm ZnO active channel layer on the top of the gate insulator was deposited from ZnO target with a purity of % in pure ambient of argon at different temperature including RT, 50 o C, 100 o C and 200 o C. 89

105 Figure 5-1: Schematics of ZnO TFS with ZnO deposited at different temperature The RF power, working pressure and Ar flow during the deposition process was maintained at 100 W, 8 mtorr and 12 sccm respectively. Finally a 100 nm Al source drain electrode capped with W was deposited and defined photolithography and by lift off patterning. The channel length and width of the fabricated TFTs devices were 200 µm and 5 µm respectively. The crystallinity and orientation of ZnO thin film was studied by glancing angle XRD and the surface morphology and microstructure of ZnO thin film was investigated by scanning electron microscope (SEM). Furthermore, the surface roughness of ZnO thin film was studied by atomic force microscopy (AFM). The electrical characterization of the fabricated TFTs devices were done on probe station equipped with Keithley 4200 SCS semiconductor parameter analyzer system. 5.3 Results and Discussion 90

106 Fig 5-2 shows the XRD pattern of the ZnO thin film deposited at different temperature. It can be seen that the pattern exhibit diffraction peak at 34.5 o, 47 o, and 58 o corresponding to (002), (102) and (103) planes of ZnO respectively. Furthermore, it is observed that there is a strong peak at 34.5 o for all the films which corresponds to (002) plane indicating the preferential c-axis orientation perpendicular to the substrate and polycrystalline nature of ZnO thin films. Intensity (a.u.) (002) ZnO XRD RT 50 C 100 C 200 C 500 (102) (103) (degrees) Figure 5-2: XRD pattern of ZnO deposited at different temperature on glass substrate 91

107 The ZnO thin film deposited at RT shows the highest (002) diffraction peak intensity followed by the 200 o C deposited film. However, there is no significant change in the intensity of (002) peak with increase in deposition temperature suggesting that ZnO has a natural tendency to form quality of polycrystalline films even at low deposition temperature. It is found that the intensity of (102) peak increases with increasing deposition temperature. The crystallite size of the ZnO thin film was calculated by using Debye- Scherrer formula k D cos (41) Where k is the Scherrer constant which depends on the peak width, crystallite shape and crystallite size distribution, D is the crystallite size, λ is the wavelength of the incident X-rays (λ= Å for Cu target), β is the full width at half maximum and θ is the Bragg s angle. By using the Eq 41, the crystallite size of the ZnO deposited at RT, 50 o C, C and 200 o C was found to be 65.63, 56.49, and nm respectively. Thus the ZnO deposited at 200 o C shows the largest grain size which is in well agreement with SEM imaging results. It should be noted that the grain size calculated from AFM is much larger than the values calculated from XRD data. This discrepancy in the crystallite size calculated from AFM and XRD is possibly due to the grain size measured from the AFM is the aggregate of smaller crystallites. Fig 5-3 shows the surface SEM images of ZnO thin film at deposited at different temperature. It can be seen that all the ZnO thin film displayed homogeneous and densely 92

108 packed polycrystalline morphology. From the SEM image, it is evident that the crystallite size tend to grow bigger with deposition temperature. 93

109 94

110 Figure 5-3: SEM image of ZnO deposited at different temperature (a) RT (b) 50 C (c) 100 C (d) 200 C Fig 5-4 shows the AFM images of ZnO thin film deposited on glass substrate at different temperature. A uniform and dense film of ZnO with fine grain of ZnO can be observed which tends to increase in size with deposition temperature. Furthermore, the ZnO thin film deposited at 50 0 C shows smooth, dense and compact film with uniform grain in comparison to the film deposited at other temperature. 95

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114 Figure 5-4: AFM image of ZnO deposited at different temperature (a) RT (b) 50 C (c) 100 C (d) 200 C At higher deposition temperature, the grain of ZnO are separated by voids which is due to the grain coalescence. The average grain size of the ZnO was estimated to be 62.5 nm, 74 nm, 60 nm and 62 nm at RT, 50 0 C, C and C respectively. The rms roughness of the film deposited at RT, 50 0 C, C and C was found to be 3.17, 3.55, 5.50 and 6.65 nm respectively. It clearly indicates the rms roughness of the film increases slightly with deposition temperature at first and increased almost by two times at C. This could be explained by the fact that increase in deposition temperature causes an increase in kinetic energy of the sputtered target atoms and high thermal stress at higher deposition temperature which results in higher surface roughness for the ZnO deposited at higher temperature. 99

115 Current (A) 4 x x x x x x x um 10 um 30 um 50 um ZnO 50 C -4 x Voltage(V) 3 x C ZnO Current (A) 2 x x x x um 10 um 30 um 50 um -3 x Voltage(V) 100

116 6 x 10-8 ZnO 200 C 4 x 10-8 Current (A) 2 x x x x um 10 um 30 um 50 um -8 x Voltage (V) Figure 5-5: I-V characteristic on ZnO with different Al contact spacing In order to find the sheet resistance of the ZnO thin film deposited at different temperature, transmission line measurement method was used. Fig 5-5 shows the I-V characteristics of the ZnO thin film deposited at different temperature for different spacing of metal contacts. As it can be observed that the linear characteristics which indicates the Ohmic character of Al on the ZnO thin film. The I-V characteristics of the ZnO thin film deposited at room temperature has not been shown due to the highly resistive ZnO film and hence the reading was close to the noise level of the probes. From the measured I-V characteristics, the resistance between the adjacent pairs of metal contact was plotted as a function of spacing as shown in the fig 5-5. The sheet resistance was obtained by 101

117 multiplying the width of the contact with slope of the plot. The resistivity was found simply by multiplying the sheet resistance with the thickness of the ZnO film. The resistivity of the ZnO was film deposited at 50 o C, C and 200 o C was found to be 1.82, 1.24 and Ω.cm respectively. It can be observed that the resistivity of the ZnO film decreases with the deposition temperature in figure Resistivity vs temperature Resistivity (Ohm.cm) Deposition temperature (C) Figure 5-6: Resistivity versus temperature plot for ZnO deposited at different temperature temperature. Fig 5-7 shows the C-V characteristics of the ZnO deposited at different 102

118 Capacitance (F) 1 x x x x x RT 50 C 100 C 200 C C-V Voltage(V) Figure 5-7: C-V characteristics of ZnO deposited at different temperature A well behaved C-V characteristics was observed for all the ZnO indicating accumulation, depletion and inversion region. The carrier concentration of ZnO at deposited at different temperature was determined from the 1/C 2 vs V voltage plot. 103

119 1 x Doping Concentration vs deposition temperature N(cm -3 ) 1 x Deposition temperature( 0 C) Figure 5-8: Carrier concentration versus ZnO deposition temperature plot Fig 5-8 shows the carrier concentration of ZnO deposited at different temperature. Interestingly, it was observed that the carrier concentration increases with the deposition temperature at first and then decreases and again increases with temperature. Furthermore it was found that the carrier concentration of all the ZnO is on the order of cm -3 and doesn t change significantly with the deposition temperature. Such level of carrier concentration make the ZnO resistive which is usually desired for ZnO TFTs device to operate in enhanced mode. It should be noted that high carrier concentration in ZnO pushes the TFTs device to operate in depletion mode resulting in high gate leakage current and hence increase in power dissipation. 104

120 Fig 5-9 shows the output characteristics IDS as a function of VDS for different gate voltage for the ZnO thin film transistors with ZnO deposited at different temperature. It can be observed that a well behaved typical TFTs output characteristics was obtained for all the TFTs with ZnO deposited at different temperature. The increase of channel conductivity with increase of gate voltage (VGS) indicates that ZnO TFTs operate in n- channel enhancement mode. The saturation drain current IDS was found to be , , , and A at a drain bias of 6 V and gate bias of 10 V for the TFTs with ZnO deposited at RT, 50 o C, 100 o C and 200 o C respectively. 2 x 10-6 ZnO-RT-TFT-25-Device x 10-6 I D (A) 1 x V 8 V 10 V 12 V 5 x V DS (V) 5 x 10-5 ZnO 50 C-TFT-25-Device 6 4 x 10-5 I D (A) 3 x x V 8 V 10 V 1 x V DS (V) 105

121 I D (A) 3.5 x x x x x x x c ZnO-TFT-25-Device 6 6 V 8 V 10 V 12 V V DS (V) I D (A) 4 x x x x x x x x C-50 nm ZnO-TFT-25-Device 2 8 V 10 V 12 V 14 V V DS (V) Figure 5-9: ID-VDS characteristics of ZnO TFTs at different ZnO deposition temperature (a) RT (b) 50 C (c) 100 C (d) 200 C These results indicate that channel conductance increases with ZnO deposition temperature for a given gate bias. Furthermore, it can be observed that ZnO deposited at RT, 50 o C, 100 o C, exhibit a clear pinch-off and saturation region while ZnO deposited at 200 o C doesn t. This can be explained by the fact as the ZnO deposition temperature rises, the carrier concentration increases which results in increase in channel conductance with 106

122 corresponding increase in off-current leakage. As a result, ZnO channel cannot be depleted of free electrons. Fig 5-10 shows the ID-VGS transfer characteristics of ZnO deposited at different temperature at drain bias (VDS) of 4 V. The threshold voltage (VTH) and saturation mobility µsat can be calculated by fitting straight line into the plots of square root of IDS versus VGS of the TFTs operating in the saturation region given by the following equation: I DS Ci satw ( V 2L GS V TH ) 2 for V DS V GS V TH (42) Where W and L are the channel width and length respectively, Ci is the gate oxide capacitance per unit area and µsat is the saturation mobility. 107

123 I D (A) x x x x x x x ZnO TFTs with different deposition temperature RT 50 C 100 C 200 C 1 x V GS (V) Figure 5-10: Transfer characteristics of ZnO deposited at different temperature The VT of ZnO TFTs with a channel deposited at RT, 50 o C, 100 o C, and 200 o C was found to be 9, 5.8, 7 and 3.7 V respectively. The least value of Vth of 3.7 V was found for ZnO TFTs with a channel deposited at 200 o C which could be attributed to the higher carrier concentration. Interestingly, the field effect mobility was found to be increasing with ZnO deposition temperature initially giving the best value of 1.12 cm 2 V -1 s -1 at 50 o C and then decreases with deposition temperature. The field effect mobility is degraded when the ZnO is deposited at the higher temperature. It can be explained by the fact that grain size for the ZnO deposited at 50 o C shows larger grain size which could cause a reduction in grain boundary density. Furthermore this could be attributed to the increased roughness of ZnO film with deposition temperature as suggested by AFM results. It is more likely 108

124 that there is a higher amount of interface trap density induced at the ZnO/HfO2 interface at high deposition temperature. The on/off ratio for all the ZnO TFTs was found to be more than 10 5 with the least value of 10 5 for ZnO deposited at 200 o C which could be due the increase in off-current leakage. The subthreshold voltage can be defined as the gate voltage required to increase the drain current by a factor of 10 and can be used to determine the maximum density of interface states at the channel/gate dielectric interface using equation 16. The SS of ZnO TFTs with ZnO deposited at different deposition temperature has been given in the table. The NSS was calculated from equation 3 using the estimated value of SS and was found to be , , , ev -1 cm -2 for the ZnO TFTs with active layer ZnO deposited at RT, 50 o C, 100 o C and 200 o C respectively. The least value of NSS was found for ZnO deposited at 50 o C while ZnO deposited at 200 o C exhibited the maximum value of NSS. It suggests that ZnO deposited at higher temperature degrades the interface of ZnO and HfO2 which could be possibly be due to the interdifussion of Zn and Hf atom at the interface and thereby deteriorating the quality of gate dielectric and channel layer. Therefore, deposition of channel layer at higher temperature could severely impact the performance of TFTs. 5.4 Conclusions ZnO TFTs using HfO2 high k dielectric with different deposition temperature of active layer ZnO were fabricated and characterized. The XRD patterns of ZnO suggested high quality polycrystalline ZnO thin film with preferential c-axis orientation can be obtained even at room temperature. The surface morphology of ZnO thin film is significantly affected by the deposition temperature which in turn can severely impact the 109

125 electrical characteristics of ZnO TFTs. It was found that ZnO TFTs with active layer deposited at 50 o C exhibited the best performance with field effect mobility of 1.12 cm 2 V - 1 s -1, threshold voltage of 5.8 V, on/off ratio of and subthreshold swing of 1.35 V/decade. The improved performance of the device was attributed to the large grain size and low surface roughness of the ZnO film deposited at 50 o C along with low amount of interface trap density at ZnO/HfO2 interface. Therefore, there is an optimum deposition temperature of active layer ZnO which is crucial in achieving high performance of ZnO based TFTs. Table 6: Performance summary of ZnO TFTs with different ZnO deposition temperature ZnO deposition µ(cm 2 /V.s) Vth (V) On/off ratio SS(V/decade) Nss(eV- 1cm-2) temperature(c) RT

126 Chapter 6 6: Effect of ZnO Channel Layer Thickness on the Electrical Characteristics of TFTs 6.1 Introduction The electrical performance of the ZnO TFTs are governed by the several parameters including polycrystalline quality of the active layer, carrier concentration and hence resistivity, the interface properties between ZnO layer and the dielectric layer, quality of gate dielectric and others. The thickness of the ZnO plays an important role in achieving high performance ZnO based TFTs. It is well known that in order to use ZnO as a channel layer in TFTs, highly resistive ZnO film with resistivity ranging from 10 5 Ω-cm to10 8 Ω- cm is required [97, 98]. Not to mention, the resistivity of ZnO is greatly controlled by its carrier concentration. However, the conductivity of the ZnO channel layer is also dependent on the channel thickness. The electrical properties of the ZnO TFTs have been found to be strongly dependent on the ZnO active layer thickness. In order to use ZnO TFTs for high resolution displays application, a large on/off ratio and hence low gate leakage current is desired. In order to achieve high value of on off ratio, an optimum thickness of the channel is needed. Moreover, the threshold voltage, mobility and subthreshold swing of the TFTs are dependent on the active layer thickness. Therefore, it 111

127 is important to optimize the thickness of the ZnO active channel layer for the high performance TFTs. Several groups have reported that channel layer thickness is one of the important factors that can strongly influence the performance of the TFTs [99, 100,101]. 6.2 Experimental Procedures A bottom gate structure as shown in figure 6-1 was employed for TFTs fabrication. All the layers were deposited by RF sputtering. A 3nm of Ti adhesion promoting layer was deposited on the Si substrate followed by deposition of 100 nm Ru as a back gate electrode. Thereafter, 100 nm thick HfO2 gate insulator was deposited from Hf target by reactive sputtering Hf in presence of 20% oxygen at RF power of 100 W and temperature of 300 o C. A ZnO active channel layer on the top of the gate insulator was deposited from ZnO target with a purity of % in pure ambient of argon at 50 o C, with different thickness of 30, 50, 70 and 100 nm. The RF power, working pressure and Ar flow during the deposition process was maintained at 100 W, 8 mtorr and 12 sccm respectively. Finally a 100 nm Al source drain electrode capped with W was deposited and defined photolithography and by lift off patterning. 112

128 Figure 6-1: Schematics of ZnO TFTs with different thickness of ZnO active layer The channel length and width of the fabricated TFTs devices were 200 µm and 5 µm respectively. The crystallinity and orientation of ZnO thin film was studied by glancing angle XRD and the surface morphology and microstructure of ZnO thin film was investigated by scanning electron microscope (SEM). Furthermore, the surface roughness of ZnO thin film was studied by atomic force microscopy (AFM). The electrical characterization of the fabricated TFTs devices were done on probe station equipped with Keithley 4200 SCS semiconductor parameter analyzer system. 6.3 Results and Discussion Fig 6-2 show the AFM images of the surface morphology of different thickness of ZnO deposited on the glass substrate. The rms roughness was found to be 1.18, 1.21, 1.54 and 1.72 nm for the ZnO film with the thicknesses 30, 50, 70 and 100 nm respectively. This indicates that the surface quality of the ZnO film gets deteriorated with the increase in the thickness. The increase in the surface roughness of the ZnO film is most likely due 113

129 to the formation of larger grain by coalescence of the smaller grain with the increase in thickness along with the increase in the porosity of the ZnO film with higher thickness. Also it could be observed that thicker film have large number of voids. 114

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132 Figure 6-2: AFM image of ZnO with different thickness (a) 30 nm (b) 50 nm (c) 70 nm (d) 100 nm Fig 6-3 shows the XRD pattern of the ZnO thin film with different thickness. It can be observed that all the samples exhibit the peaks at 34.2 o, 48 o and 58 o which corresponds to the plane (002), (102) and (110) respectively. The sharp peak corresponding to (002) plane at 34.2 o implies that all the ZnO films exhibit (002) preferential orientation with the c-axis perpendicular to the substrate. The film with thickness 70 and 100 nm exhibit the strong (002) diffraction peak. Furthermore it could be seen that the intensity of (002) peak increases with thickness which indicates that polycrystalline quality of the ZnO film enhanced with the thickness of the film. Also, it can be seen that only the only the intensity of (002) plane was increased as increasing film thickness, while there was no significant difference in intensity for other patterns, irrespective of film thickness. Therefore, it can 117

133 be said that thickness of ZnO is an important parameter that determines the crystalline quality of the film. The improvement in the crystallinity of the ZnO film with the increase in the thickness could be due to the thicker film exhibiting the bulk material properties as more atoms are allowed to move freely toward the favorable energy position forming the free surface giving rise to the wurtzite structure. The broad peak at 22 o is due to the glass substrate and intensity of such peak decreases with increase in the film thickness. Moreover, there is a broadening of the (002) diffraction peak and hence increase of the full width of their half maxima (FWHM) with the decrease in the ZnO which can be used to determine the crystallite size using the Scherer s equation Where k is the Scherrer constant (the shape factor of the average crystallite and can be considered k = 0.94; λ = nm is the wavelength of the incident Cu Kα radiation; β2θ represents the full-width at half-maximum of the respective peak and θ is the Bragg diffraction angle. 118

134 ZnO thickness Intensity (a.u.) nm 50 nm 70 nm 100 nm Figure 6-3: XRD pattern of ZnO with different thickness Fig 6-4 shows the cross sectional TEM image of the bottom gate ZnO TFTs with 100 nm HfO2 gate dielectric and 50 nm ZnO channel layer. It can be observed that the interface between the ZnO and HfO2 is smooth which is required for efficient transport of carriers in the channel between the source and drain. 119

135 W Al ZnO HfO 2 Ru Ti Figure 6-4: TEM image of ZnO TFT with 50 nm of ZnO Fig 6-5 shows the SEM images of the different thicknesses of ZnO deposited on the glass substrate. All the films showed uniform and densely packed film with welldefined crystallites. It can be observed the size of crystallite increases with the film thickness at first for the thickness up to 50 nm and thereafter, no significant change in the crystallite size was seen. Furthermore, it can be seen that thicker ZnO film with thicknesses 70 nm and 100 nm are rougher with non-uniform crystallite size compared to 30 and 50 nm ZnO. 120

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137 Figure 6-5: SEM image of ZnO with different thickness (a) 30 nm (b) 50 nm (c) 70 nm (d) 100 nm 122