Copy of: Proc. IEEE 1998 Int. Conference on Microelectronic Test Structures, Vol.11, March 1998

Transcription

1 Copy of: Proc. IEEE 998 It. Coferece o Microelectroic Test Structures, Vol., March 998 Wafer Level efect esity istributio Usig Checkerboard Test Structures Christopher Hess, Larg H. Weilad Istitute of Computer esig ad Fault Tolerace (Prof. r.. Schmid) Uiversity of Karlsruhe, P. O. Box 6980, 7628 Karlsruhe, Germay Phoe: , FAX: , Abstract - efect desity distributios play a importat role i process cotrol ad yield predictio. To improve the accuracy i modelig defect desity distributios we preset a wafer level methodology to aalyze defect data measured aywhere o a wafer. So, the ispected area may be limited to test structures that just cover a fractio of each wafer. For that, imagiary wafermaps are geerated for a variety of differet chip areas to calculate a yield-to-area depedecy. Based o these calculatios a Micro esity istributio (M) will be determied for each wafer that reflects the degree of defect clusterig. The sigle Ms per wafer may be summarized to also provide a Geeral efect esity istributio per lot or ay other sample size. INTROUCTION OAY S complexity of itegrated circuits requires more T ad more coductig backed layers to coect all circuit cells ad devices. Udesiged layout objects (defects) ca occur durig the maufacturig process. epedet o the layout, defects ca become the cause of electrically measurable faults which are resposible for maufacturig related malfuctios of chips. So, defect desity distributios are importat for yield predictio ad to cotrol quality of process steps ad product chips. For each wafer, a sigle defect desity value will be determied as the total umber of defects o the wafer divided by the total area of the wafer. To determie a defect desity distributio, may wafers have to be ivestigated. So, a defect desity distributio reflects the wafer to wafer desity variatios or the lot to lot desity variatios, respectively. Especially i yield modelig also chip to chip desity variatios are discussed - better kow as defect clusterig. For that, more tha just oe defect desity value per wafer is required. So, the total wafer area has to be divided i area segmets each providig a idividual defect desity value. To get area segmets that are early idepedet of kow defect cluster effects, we have developed a methodology to calculate a wafer level Micro esity istributio (M). To determie wafer level defect desity distributios, it is ecessary to locate each detected defect o the wafer. Optical defect ispectio systems provide such data but, oly electrically based data represet those defects that are large eough to impact yield. For that Sectio 2 briefly describes the Checkerboard Test Structure desig. Sectio 3 itroduces yieldto-area calculatios to obtai a segmetatio of the wafer area. Sectios 4 ad 5 preset a ovel methodology to calculate ad model wafer level defect desity distributios. Fially we preset some experimetal results ad coclude our approach. 2 CHECKERBOAR TEST STRUCTURE To get defect desities, simple test structures of comb ad serpetie lies are commoly used [Bueh83], [LYWM86]. But, simple test structures do ot provide ay defect localizatio iside large chip areas, which are required to detect defects eve if the average defect desity is low. Usig the Checkerboard Test Structure (CTS) itroduced by [Hess94], [HeSt94], [HeWe95b] guaratees a large defect sesitive area iside a give pad frame. kts.wpg;a-kts Fig. : Checkerboard Test Structure cotaiig 870 subchips.

2 To eable precise defect localizatio, the Checkerboard Test Structure divides the total chip area ito a large umber of electrically distiguishable subchips. If a fault will be measured betwee 2 pads, algorithms clearly provide the subchip cotaiig the defect that has caused the measured fault. Figure shows a CTS cotaiig 870 subchips. 3 YIEL-TO-AREA CALCULATIONS A Checkerboard Test Structure (CTS) provides a list of defect positios. Based o a kow wafermap each chip ca be marked as "pass" or "fail" depedat o the absolute positio of a defect. A chip is marked as "fail", if at least oe defect is detected iside the chip boudaries. For a specific wafermap a yield value Y ca be calculated usig the followig Equatio: Y umber of pass chips total umber of chips mm97l0.wpg;a-map () By geeratig a imagiary wafermap based o a give chip area A ad projectig it o the origial wafer, we ca agai calculate a yield value usig the same defect list give by the data of the CTS. The Figures 2 ad 3 show two differet imagiary wafermaps. I each wafermap, black symbols mark the defects detected iside the Checkerboard Test Structures. For a series of imagiary wafermaps, the yield will be determied depedet o the chip area. This results i a Yield-to-Area Curve as ca be see i the followig Figure. mm97l34.eps;a?,0 yield area [mm²] Fig. 4: Yield-to-area curve of electrically detected defects o a wafer. 4 MICRO ENSITY ISTRIBUTION (M) Based o a give imagiary chip area A a defect desity value ca be calculated usig the followig Equatio: Y A Y : yield A : area of a sigle imagiary chip : defect desity (2) Fig. 2: Imagiary wafermap cotaiig 648 chips. mm97l4.wpg;a-map2 This Equatio assumes that the wafer area is completely covered by defect sesitive test structures. But, if test structures are combied with product chips or placed iside the sawig lies they just cover a fractio of the complete wafer area. So, there will be a ifluece o the calculatio of the defect desity values. For example, the followig Figure shows a map of 4 by 4 reticles just cotaiig a limited test chip area beside product chips. The black boxes iside the test chips mark detected defects. Assumig that the test chip area is cm² we ca determie a defect desity value usig Equatio (2) which yields =0.25. icmt8l0.eps;a? space for other desigs test chip defect reticle Fig. 3: Imagiary wafermap cotaiig 29 chips. Fig. 5: ividig reticles ito test chip area ad product chip area.

3 We ow geerate four differet imagiary wafermaps as ca be see i the followig Figure. icmt8l02.eps;a? Geerally, the yield based o differet imagiary wafermaps will decrease by icreasig the imagiary chip area. This may have a detrimetal ifluece o Equatio (3) which will be ivestigated regardig the followig Figure cotaiig two differet maps with differet chip areas. icmt8l04.eps;a? a) b) a) b) Fig. 7: ifferet imagiary wafermaps. defect c) d) pass chip Fig. 6: ifferet imagiary wafermaps. fail chip Based o these wafermaps Equatio (2) results i the followig four defect desity values: The imagiary wafermap (a) has 256 chips with a chip area of 0.5²cm which yields a defect desity of =0,0625. The imagiary wafermap (b) has 64 chips with a chip area of.0²cm which yields a defect desity of =0,0625. The imagiary wafermap (c) has 6 chips with a chip area of 2.0²cm which yields a defect desity of =0,0625. The imagiary wafermap (d) has 4 chips with a chip area of 4.0²cm which yields a defect desity of =0,0625. It is obvious that these defect desity values are too small, because they are based o defect data that were measured o just /4 of the reticle area. To get accurate defect desity values a area factor γ has to be added to the defect desity Equatio (2). The factor γ represets the area covered by defect sesitive test structures i compariso to the complete reticle area. Y γ A I our example we just ispected a quarter of the reticle area (γ=0.25), so that the defect desity value will be =0.25 which correspods to the measured defect desity value withi the origial wafermap. (3) The defect desity calculated by Equatio (3) will remai true as log as o more tha oe defect will be i a "fail" chip as ca be see o the left side of the Figure. The right side of the Figure shows chips cotaiig more tha oe defect. I this case, defects are hidde so that Equatio (3) yields defect desity values that are too small. To prevet this detrimetal effect, the chip area of the imagiary wafermaps has to be limited, so that a "fail" chip does ot cotai more tha oe defect. For that, the average defect desity of calculated values i has to be withi the limit of approximatio (4). The factor ε has to be selected depedet o the average umber of defects per wafer. A high umber of defects requires a low ε value. γ A < ε where: 0.5 ε<.0 where: i i A : chip area correspodig to defect desity To get a set of defect desity values per wafer, it is importat to start calculatig the defect desity i withi the yield-to-area curve for the smallest available chip area A. The the chip area has to be icreased as log as the fail chips just cotai oe defect (ref. Equatio (4)). So, it is possible to determie the so called Micro esity istributio (M) by coutig the occurrece of defect desity values i per desity iterval which ca be see i the followig Figure 8. To get comparable defect desity distributios withi differet layers o a wafer, we use the probability desity of defects by ormalizig the curve which meas that the sum of all occurrece values has to be set to "". I additio to that, we also determie the overall defect desity o a wafer as the total umber of defects o a wafer divided by the total ispected area of the wafer. Figure 8 cotais this value as additioal small vertical peak. (4)

4 mm97l33.eps;a-mm97l33.eps 0,6 probability desity of defects 0,5 0,4 0,3 0,2 0, 0,0 0,0 defect desity [/cm²] Fig. 8: Micro esity istributio of electrically detected defects o a wafer. 5 GENERAL ENSITY ISTRIBUTION (G) To get a Geeral esity istributio (G) of all wafers i a lot, we have to summarize the sigle Ms per wafer. Equatio (5) will be used to obtai such a G. s h x h s x,i i (5) h x : probability desity value of the defect desity iterval x of the Geeral esity istributio h x,i : probability desity value of the defect desity iterval x of the M of wafer i s : umber of wafers This results i a ormalized G over all wafers of a lot where the sum of all probability values h x is. 6 EXPERIMENTAL RESULTS At Elmos, Elektroik i MOS-Techologie GmbH i ortmud, Germay several Checkerboard Test Structures (CTS) were desiged to cotrol defect appearace iside the itercoectio layers. The CTS covers /6 of the reticle area. To verify the procedure to determie a M based Geeral esity istributio we first divided a wafermap ito ceter ad boudary reticles as ca be see i the followig Figure. icmt8l05.eps;a? The wafermap also cotais all defects marked as "X" that occurred withi a complete lot. Now, we separately determied the Ms of all wafers for the ceter reticles ad the boudary reticles. Summarizig the sigle Ms to a G results i the bars of the followig Figure. icmt8l.eps;a? probability desity 0,32 0,28 0,24 0,20 0,6 0,2 0,08 0,04 0,00 0,0 0,4 0,8,2,6 2,0 2,4 2,8 3,2 Fig. 0: defect desity ceter reticles M boudary reticles M ceter reticles GF boudary reticles GF Compariso of M based Gs of ceter ad boudary reticles icludig the modeled GFs. The chart also icludes modeled Gs usig the Gamma istributio Fuctio (GF) as described i the Appedix. The wafermap shows that we have a cocetratio of defects i the ceter of the wafer. As expected we get a higher defect desity for the ceter reticle Gs. I a secod experimet we looked to sets of reticles that early cotai the same umber of defects per set. Therefore we partitioed all reticles ito a checkered arragemet which ca be see as grey ad white reticles i Figure. icmt8l07.eps;a? Fig. : Checkered arragemet of reticles o a wafermap icludig all defects of a complete lot. Fig. 9: Arragemet of reticles ito ceter (grey) ad boudary reticles (white) o a wafermap icludig all defects of a complete lot. Agai, we determied the sigle Ms for each wafer. The G ad also the modeled Gamma istributio Fuctio ca be see i Figure 2.

5 icmt8l0.eps;a? probability desity 0,20 0,6 0,2 0,08 0,04 checkered "white" M checkered "grey" M checkered "white" GF checkered "grey" GF APPENIX MOELING EFECT ENSITY ISTRIBUTIONS The most popular fuctio for modelig defect desity distributios proposed by [OkNS72] ad [Stap73] is the Gamma istributio Fuctio (GF). The form of f() is f() Γ(α) β α (α ) e β (6) 0,00 0,0 0,4 0,8,2,6 2,0 2,4 2,8 3,2 Fig. 2: defect desity Compariso of M based Gs of checkered reticles icludig the modeled GFs. As expected, the Gs are early uiform. Fially, the followig Figure compares all four Gamma istributio Fuctios. It ca be see that the M based G detects clustered defects. So, the defect desity distributio withi the boudary reticles is below average while the defect desity distributio withi the ceter reticles is above average. icmt8l2.eps;a? probability desity 0,32 0,28 0,24 0,20 0,6 0,2 0,08 0,04 0,00 0,0 0,4 0,8,2,6 2,0 2,4 2,8 3,2 defect desity checkered "grey" GF checkered "white" GF ceter reticles GF boudary reticles GF Fig. 3: Compariso of gamma distributio fuctios (GF). The parameter α is related to the variace σ² of the defect desity. The coefficiet β has bee iterpreted [Ferr89] as the couplig coefficiet of the occurrece of the defects. The parameters α ad β ca be calculated usig the followig two Equatios: α β 2 0 σ² σ² 0 The average defect desity is calculated by: 0 i i : defect desity value of imagiary wafermap i : umber of imagiary wafermaps Ad fially the variace σ² ca be calculated usig the followig equatio: σ² i ² 0 ² (7) (8) (9) (0) The GF should be ormalized by solvig the gamma fuctio Γ(α) 7CONCLUSION The described method to obtai several defect desity values per wafer eables the determiatio of a sigle wafer defect desity distributio called Micro esity istributio (M). So, chip to chip variatios of clustered defect will be evaluated, eve if defects will be ispected withi test structures that just cover a fractio of the complete wafer area. Γ(α) x α e x dx 0 so that the area uder the GF is. f() 0 () (2) Furthermore, all Ms may be summarized to ivestigate wafer to wafer ad lot to lot variatios. A M based defect desity distributio is sesitive to ay defect clusterig. The high umber of defect desity values improves the sigificace of defect desity distributio modelig for yield predictio. The methodology is also applicable to defects detected by optical measuremets, but electrically detected defects are more related to product chip yield. ACKNOWLEGMENT Parts of this research were supported by eutsche Forschugsgemeischaft (FG), Schm623/3. The authors thak R. Borefeld, M. Prott ad C. Strauch (ELMOS, ortmud, Germay) for advice ad assistace with maufacturig ad testig procedures.

6 REFERENCES [Bueh83] Buehler, M. G. Microelectroic Test Chips for VLSI Electroics VLSI Electroics Microstructure Sciece, pp , Vol 9, Chap.9, Academic Press, 983 [Ferr89] Ferris-Prabhu, A. V. efects, Faults ad Semicoductor Yield efect ad Fault Tolerace i VLSI Systems, Vol., pp I. Kore, ed. Pleum Press, New York, 989 [Hess94] Hess, C. Strategy to Optimize the evelopmet, Use, ad imesio of Test Structures to Cotrol efect Appearace i Backed Process Steps Proc. Advaced Semicoductor Maufacturig Coferece (ASMC), pp , Bosto (USA), 994 [HeSt94] Hess, C., Ströle, A. Modelig of Real efect Outlies ad efect Parameter Extractio Usig a Checkerboard Test Structure to Localize efects IEEE Trasactios o Semicoductor Maufacturig, pp , Vol. 7, No. 3, 994 [HeWe95b] Hess, C., Weilad, L. H. efect Parameter Extractio i Backed Process Steps usig a Multilayer Checkerboard Test Structure Proc. Iteratioal Coferece o Microelectroic Test Structures (ICMTS), pp. 5-56, Nara (Japa), 995 [LYWM86] Lukaszek, W., Yarbrough, W., Walker, T., Meidl J. CMOS Test Chip esig for Process Problem ebuggig ad Yield Predictio Experimets Solid State Techology, pp , March 986 [OkNS72] Okabe, T. Nagata, M., Shimada, S. Aalysis of Yield of Itegrated Circuits ad a New Expressio of the Yield Electrical Egeeerig i Japa, pp. 35-4, Vol. 92, ec. 972 [Stap73] Stapper, C. H. efect esity istributio for LSI Yield Calculatios IEEE Trasactios o Electro evices, July 973