Adaptive Mode Control: A Static-Power-Efficient Cache Design

Transcription

1 Adaptive Mode Control: A Static-Power-Efficient Cache Design Huiyang Zhou, Mark Toburen, Eric Rotenberg, Tom Conte Center for Embedded Systems Research (CESR) Department of Electrical & Computer Engineering North Carolina State University

2 Trends Technology Trends Lower threshold voltages in deep sub-micron technologies u increases leakage current (sub-threshold current) u increases static power dissipation Large fraction of die area occupied by on-chip caches 60% of StrongARM die area is cache 2

3 Circuit-level solution Circuit Support SRAM cells with low-leakage operating modes Insert transistors between V dd and Gnd rails Isolating cells from power rails puts them in sleep mode (reduces leakage current) 3

4 Architectural Support Circuit-level technique must be controlled at the architecture level Data stored in sleeping cell is unreliable or lost Maximize number of sleep-mode lines while preserving performance Caches tradeoff efficiency for robustness Deactivate (put into sleep mode) unused cache lines 4

5 Methods for Dynamically Deactivating Cache Lines Related Work DRI Cache [S-H Yang, et. al.] Deactivate large groups of cache lines Miss rate periodically compared to statically preset miss bound Cache Line Decay [S. Kaxiras, et. al.] Deactivate individual lines after a preset decay time Per-application profiling required to determine best miss bound and decay time 5

6 The Need for Adaptivity Per-benchmark cache line decay times, tuned to reduce performance by no more than 4% decay time (x 1024 cycles) comp gcc go jpeg li best decay time m88k perl vortex Adaptive extensions to cache line decay Exploiting generational behavior [S. Kaxiras, et. al.] Adaptive mode control (our approach) 6

7 Key idea Adaptive Mode Control (AMC) Tags are always kept active Know what miss rate could be with all cache lines active Actual miss rate can be made to precisely track hypothetical miss rate 7

8 Adaptive Mode Control (AMC) Can distinguish between two types of misses Ideal miss Tag miss Would have occurred in conventional cache Sleep miss Tag hit, cache line in sleep mode Extra miss introduced by sleep mode Control turn-off interval based on ratio of sleep misses to ideal misses Increase turn-off interval if ratio too high Decrease turn-off interval if ratio too low Keep turn-off interval the same if ratio reasonable 8

9 Outline á Introduction AMC cache architecture Adaptive mechanism (control system) Simulation methodology Results Conclusions 9

10 AMC Cache Architecture Tag Index Block Offset LIC Update Interval Control Register (GCR) row select mode control row decoder Line Tag Store Idle Mode Counter Control (LIC) Logic Data Store tag mode (MCL) Block Offset tag match & mode check row select mode control word select MUX hit/miss adaptive mechanism data word 10

11 Significance of Turn-off Interval (GCR) first access last access evicted Too small: Prematurely de-activate lines, extra sleep misses Too large: Don t de-activate lines before eviction, lost power-savings opportunity Good 11

12 Adaptive Mechanism Tag store hit/miss active/sleep status ideal miss counter end of sense interval? performance factor sleep miss counter GCR update logic increase/decrease no_update <<1 >>1 G C R 12

13 How the control system works number of misses 0.5*PF*(ideal misses) target error = PF*(ideal misses) increase GCR decrease GCR error > 1.5*PF*(ideal misses) {increase GCR} error < 1.5*PF*(ideal misses) error > 0.5*PF*(ideal misses) {no change to GCR} error < 0.5*PF*(ideal misses) {decrease GCR} ideal misses time 13

14 GCR Update Algorithm Performance factor (PF): target ratio of sleep misses to ideal misses Determines how many additional misses can be tolerated in exchange for static power savings Algorithm if ((sleep misses) < ((ideal misses)*0.5*pf)) { decrease GCR: shift GCR right by one bit } else if ((sleep misses) > ((ideal misses)*1.5*pf)) { increase GCR: shift GCR left by one bit } else { do not change GCR } 14

15 Simulation Methodology A MIPS R10000-like, dynamically scheduled, 4-way issue superscalar processor Instruction and data caches 16 KB/32 KB/64 KB Direct-mapped and 4-way set-associative 64-byte blocks I-cache hit time = 1 cycle; miss penalty 12 cycles D-cache hit time = 2 cycles; miss penalty 14 cycles AMC PF = ½ Sense interval = 1 million cycles LIC update interval = 2048 cycles 15

16 AMC I-Cache Results 16 vortex H. Mean 16k-DM 32k-DM 64k-DM 16k-4way 32k-4way 64k-4way go jpeg li m88k perl gcc comp % IPC degradation

17 AMC I-Cache Results (cont.) 16k-DM 32k-DM 64k-DM 16k-4way 32k-4way 64k-4way 17 gcc go jpeg li m88k perl vortex A. Mean comp Cache Line Turn-off Ratio

18 AMC D-Cache Results 16k-DM 32k-DM 64k-DM 16k-4way 32k-4way 64k-4way 18 vortex H. Mean go jpeg li m88k perl gcc comp % IPC degradation

19 AMC D-Cache Results (cont.) 16k-DM 32k-DM 64k-DM 16k-4way 32k-4way 64k-4way 19 gcc go jpeg li m88k perl vortex A_mean comp Cache Line Turn-off Ratio

20 AMC I-Cache and D-Cache Results AMC can be applied simultaneously to both the instruction cache and data cache 64kB 2-way I-cache and 64kB 4-way D-cache Turn-off ratios of 73% and 56% for I-cache and D- cache, respectively Performance degradation is only 1.8% 20

21 Conclusion Key idea: The tag store is always kept active Enables hypothetical performance without sleep mode to be determined and used to control real performance Improvement over setting arbitrary and static performance targets Proposed a control system that keeps the number of sleep misses within a certain factor of ideal misses AMC is an effective means for improving staticpower-efficiency in caches while maintaining good performance Uncovered interesting trends, e.g., higher associativity yields lower turn-off ratios 21

22 Power Analysis See companion technical report for detailed power analysis EDP and other metrics Static and dynamic power analysis, including dynamic overhead for additional L2 requests and dynamic plus static overhead of LIC counters We used Compaq 0.35µm I-cache technology [H. Zhou, et. al., Technical Report, NCSU, Nov. 2000] 22

23 Future Work Power analysis using projected technology data Compare with generational cache line decay approach Reducing power dissipation further Keep only partial tags active Increase static power savings Exploit non-destructive sleep-mode circuit design [K. Noii, et. al., ISPLED, 1998] Eliminate dynamic power increase due to refreshing sleep-mode data from L2 cache Eliminate dynamic power increase due to writing dirty data to L2 before deactivating cache line 23

24 Contact Information Huiyang Zhou Mark Toburen Eric Rotenberg Tom Conte North Carolina State University 24