Solutions to Technical Challenges for WLBI Steve Steps

Solutions to Technical Challenges for WLBI Steve Steps

Major Technical Challenges Only three major challenges Thermal Mechanical Electrical June 9, 2002, Page 2

Major Thermal Challenges Adding heat or usually removing heat in the order of hundreds of watts June 9, 2002, Page 3

Thermal Chuck Uniform wafer temperature Independent of yield up to 150 C Dissipates high power per wafer Simple, air cooled design June 9, 2002, Page 4

Major Thermal Challenges Adding heat or usually removing heat in the order of hundreds of watts Maintaining constant temperature across wafer June 9, 2002, Page 5

Thermal Chuck ~4º C Range June 9, 2002, Page 6

Chuck With Optimizing Heaters ~2º C Range June 9, 2002, Page 7

Major Thermal Challenges (cont.) Maintaining constant temperature across wafer Adding heat or usually removing heat in the order of hundreds of watts Coefficient of thermal expansion mis-match 8 Si wafer edges expand from wafer center by over 50 microns from 25 to 150 degrees C. PC board will expand about 250 microns over same range. June 9, 2002, Page 8

Interconnect Substrate Functions like a PC board CTE matched with wafer Contactor also CTE matched to wafer June 9, 2002, Page 9

Mechanical Challenges Aligning wafer to contactor June 9, 2002, Page 10

WaferPak Alignment Station Loads and unloads wafers between WaferPak and cassette Aligns the wafer to the probe/contactor using both upward and downward cameras June 9, 2002, Page 11

Mechanical Challenges (cont.) Aligning wafer to contactor Cost effective June 9, 2002, Page 12

WaferPak Modular Components Cartridge based solution simplifies hardware Loaded WaferPak is like a Burn In Board One Alignment Station per customer site versus per wafer System Connectors Signal Distribution Top plate Contactor Thermal chuck June 9, 2002, Page 13

Mechanical Challenges (cont.) Aligning wafer to contactor Cost effective design High contact pressures 8 SDRAM wafer with 50 pads/die, 500 die requires 25,000 pin contactor At 10 grams per pin about 250 kg required Maintain planarity to microns at these forces June 9, 2002, Page 14

Thermal Chuck Flatness Test Results Thermal chuck analyzed and designed to provide a very flat surface in contact with the wafer Used Cosmos Finite Element Analysis tools June 9, 2002, Page 15

Mechanical Challenges (cont.) Aligning wafer to contactor Cost effective design High contact pressures 8 SDRAM wafer with 50 pads/die, 500 die requires 25,000 pin contactor At 10 grams per pin about 250 kg required Maintain planarity to microns at these forces How to generate and control such high forces June 9, 2002, Page 16

Contactor Force Control Pressure based versus Vacuum based Not limited to one atmosphere More precise, uniform control of force Any leaks drive away contamination Can control location of force Probe to force versus to position Required for most contactor technologies Compensates for non-planarity Full wafer contact produces on-axis forces June 9, 2002, Page 17

Mechanical Challenges (cont.) Aligning wafer to contactor Cost effective design High contact pressures 8 SDRAM wafer with 50 pads/die, 500 die requires 25,000 pin contactor At 10 grams per pin about 250 kg required Maintain planarity to microns at these forces How to generate and control such high forces Best contactor varies per application June 9, 2002, Page 18

Contactor Choices Highly modular system supports multiple contactor technologies for Au, Al, Cu, UBM or solder balls Consumable Sheet Lower NRE Micro pogo spring High touchdown life Great for relocated pads Ultra fine pitch June 9, 2002, Page 19

Sheet Based Z-axis Contactor Available in single-use or many-use sheets Interconnect board precisely aligned to wafer If sheet pattern is regular, then sheet position can be random If sheet is patterned, then must be aligned June 9, 2002, Page 20

Micro Pogo Spring Contactor High touchdown life High compliance Works with most pad metallurgies Multiple pitches available June 9, 2002, Page 21

Micro Pogo Spring Close-up June 9, 2002, Page 22

NanoSpring Contactor Contactor Array 80 micron pads June 9, 2002, Page 23

Major Electrical Challenges How to deal with 25,000 or more signal lines Cannot remove bad die How to deal with signal line shorts How to deal with die power shorts June 9, 2002, Page 24

System Electronics Leverage experience in parallel test design Signal lines and data lines are paralleled to vastly reduce total interconnect count between wafer and system electronics Individual die power lines prevent shorted die from interfering with good die Capability to control & monitor power on individual die basis June 9, 2002, Page 25

Does It Really Work? Is Full Wafer Contact really possible? June 9, 2002, Page 26

SDRAM Wafer Map June 9, 2002, Page 27

Does It Really Work? Is Full Wafer Contact really possible? Is the contact reliable? June 9, 2002, Page 28

Per Touchdown Resistance 0.7 0.6 0.5 Resistence (ohms) 0.4 0.3 Average Std. Dev. 0.2 0.1 0 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97 100 Touchdown Number June 9, 2002, Page 29

Does It Really Work? Is Full Wafer Contact really possible? Is the contact reliable? Can it scale? Across varying wafer CTE? Across varying wafer sizes? Across nearly 3 orders of magnitude in force? June 9, 2002, Page 30

Laser Diode Burn-In Current per VCSEL 0.02 0.018 0.016 Bottom Right Quarter Top Right Quarter Top Left Quarter Bottm Left Quarter 0.014 0.012 Current (amps) 0.01 0.008 0.006 0.004 0.002 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 Row Number June 9, 2002, Page 31

Full Wafer Burn & Test Status Took longer than expected Many technical barriers Has been demonstrated across Wafer sizes from 2 to 8 (300mm shortly) Different wafer types (CTE) SDRAMs to VCSELs (Laser Diode) Different pad metallurgies Widely varying contactor technologies June 9, 2002, Page 32

Full Wafer Burn & Test Has Arrived June 9, 2002, Page 33