Optimal Precoding and MMSE Receiver Designs for MIMO WCDMA

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1 Optimal Precoing an MMSE Receiver Designs for MIMO WCDMA Shakti Prasa Shenoy, Irfan Ghauri, Dirk T.M. Slock Infineon Technologies France SAS, GAIA, 26 Route es Crêtes, 656 Sophia Antipolis Cee, France Mobile Communications Department, Institut Eurécom, 2229 Route es Crêtes, 694 Sophia Antipolis Cee, France Abstract 2 2 unitary precoing base on receiver feeback is applie alongsie spatial multipleing at the base station in HSDPA D-TAA when the mobile terminal supports MIMO transmissios []. This precoing will influence achievable sumrate of the MIMO channel if it influences the Signal-to- Interference-plus-Noise Ratio SINR of streams at the receiver RX output. We propose a set of MIMO HSDPA receivers, all base upon a MMSE chip-level matri filter equalizer front en, an introuce the notion of joint bias for the MIMO chip equalizer. Statistical properties of the spatial moel thus obtaine are eploite to analyze the performance of propose MIMO receivers. It is shown that precoing choice epens upon the MIMO receiver an the etent of its impact epens on the MIMO RX. I. INTRODUCTION 3GPP has introuce a variant of Per-Antenna Rate-Control PARC, namely D-TAA for Dual-stream Transmit Diversity for Multi-Input Multi-Output MIMO transmissions [] in UMTS WCDMA. Coe reuse is mae across the two streams an the scrambling sequence is also common to both transmit TX streams. All 5 spreaing coes are allocate to the same user in the HSDPA MIMO contet. In general, all UEs serve by a BS fee an SINRbase or base on some other appropriate measure Channel Quality Inicator CQI back to the BS. In aition, the UE also computes an fees back the weighting vectors that woul ieally provie the best instantaneous rate for the net time slot. Together, these feebacks translate into a specific transport block size an a specific Moulation an Coing Scheme MCS for each UE. Base on this information, the BS is capable of maimizing the ownlink throughput for each transmission time-interval. MIMO has largely been iscusse in the contet of frequency nonselective OFDM case, where optimal joint-stream MAP etection can be employe. In CDMA, on the other han, multipath mies signals up in space an time calling for alternative reception strategies. Proposals for receiver RX solutions inclue chip-level equalization an epreaing followe by joint etection of the ata streams at symbol level [2]. More generally, a two stage approach is consiere where the first stage is the chip-equalizer correlator followe by some kin of joint processing or ecision-feeback approach [3]. In practice, the symbol-level spatial channel can now be seen as a per-coe spatial miture. Alternatively, more general FIR channel shortening can be consiere [3] leaing asymptotically in SNR introucing MIMO spatial joint channel which can inee be followe up by a CDMA coecorrelator an per-coe symbol-level multi-stream MAP etector. Other receiver options with varying egrees of compleity coul also be consiere, e.g., a symbol-level MMSE, which is the true linear MMSE receiver for the symbol sequence but is time-varying ue to the aperioic scrambler an b non-linear turbo-iterate serial an/or parallel SIC/PIC interference canceler for all user coes. In general, all attempts to simplify processing fall well short of optimal time-varying symbol-level processing. For D-TAA with unitary precoing, there eists an optimal choice of the precoing matri that woul maimize the sum rate across the two streams. In principle, the receiver can evaluate the SINR corresponing to all precoing choices an request the application of the SINR-maimizing weights for the net TX frame. The receiver further signals a CQI for each stream that can be mappe to a particular MCS. The ata packet size associate with a particular MCS can then be mappe to obtain the supporte throughput for each stream for a certain pre-efine Packet-Error Rate PER. The mapping strategy has been subject to significant simulation stuy see e.g., [4] an SINR CQI PER throughput relationship has been agree to, appearing as CQI to MCS tables in the 3GPP stanar ocument []. In this paper, we analyze performance of a variety of simple receivers for unitary precoe D-TAA MIMO in the HSDPA contet. We propose several receiver structures an erive SINR epressions per stream for each of them. We then compare their performance in terms of their sum-rate capacity which can be interprete as upper boun for achievable rates. II. MIMO SIGNA MODE For the spatial multipleing case in MIMO HDSPA, Fig. illustrates the equivalent baseban ownlink signal moel. The receive a [n] a K [n] a 2 [n] a 2K [n] Fig.. c [j] c K [j] c [j] c K [j] s[j] b [j] s[j] b 2 [j] W [j] Hz MIMO signal moel with precoing. v[j] signal vector chip-rate at the UE can be moele as = Hz [j] v[j]. 2m 2m In this moel, j is the chip ine, Hz is the frequency selective MIMO channel the output of which is sample m times per chip an v[j] represents the vector of noise samples that are zero-mean circular Gaussian ranom variables. The sequence [j] introuce into the channel is itself a linear combination D-TAA see [] of the two steams an is epresse as K [j] = W 2 2 b[j] =W k= s[j]c k [j mo ]a k [n] b k [j] /8/$ IEEE 893

2 k is the coe ine, p is the ine of the symbol on coe k given by n = j, is the spreaing factor =6for HSDPA, W = [w w 2] is the 2 2 precoing matri with w =[ 2 w] T an w 2 =[ 2 w] T. The symbol vector a k [n] =[a k [n] a 2k [n]] T represents two inepenent symbol streams, c k =[c k []... c k [ ]] T,wherec T i c j = δ ij are unit-norm spreaing coes common to the two streams, an s[j] the common scrambling sequence element at chip time j, which is zero-mean i.i.. with elements from 2 {±± j}. III. MIMO HSDPA RECEIVER STRUCTURES A. Receiver : MMSE Chip Equalizer-Correlator In the spatial multipleing contet, the MMSE equalization tries not only to suppress all Inter-Chip Interference ICI but also all Inter-Stream Interference ISI. The 2 2 linear FIR MMSE chiplevel equalizer is F = RyR yy see fig. 2. We can write the equalizer output as the sum of an arbitrarily scale esire term an an error term [j] =[j] [j]. 3 The error [j] is a zero-mean comple normal ranom variable. The error covariance matri is enote by R. In 3, an estimate of the chip sequence can be obtaine after a further stage of processing where the precoing is unone to separate streams. The latter represente by W H is a linear operation an can be carrie out before or after espreaing the latter case is shown in fig. 2. represents the equalization elay in chips. m [j ] s [j ] [j] z [n] W H c H k z k [n ] W H â k [n ] Fig. 2. MMSE equalizer an correlator. The secon figure is a simplifie representation use as chip-equalizer /correlator front-en stage for other receiver structures. After espreaing for the kth coe the 2 signal at the symbol level is written as =Wa k [n] =BW a k [n]. 4 In this epression, B is the MMSE joint bias at the output of the chip-equalizer/correlator see appeni A, an by consequence the quantity therefore contains no esire symbol contribution. Note that in this RX structure we assume W H to be the ecision statistic. Estimation of R z z : Uner the assumption of a FIR signal moel, the estimation error covariance matrices R chip-level an R z z symbol-level are erive in appeni A. 2 Output SINR: From analysis of R z z, it can be shown that the SINR for the ith stream at the output of the output of the MMSE chip equalizer/correlator is given by SINR i = 2 W H B R z z B H W. 5 ii Taking epectation over the time-varying ranom scrambling sequence as is customary, the bias term can be consiere to be constant at the equalizer/correlator output. Once MIMO joint bias is properly taken into account see appeni A, the epression for the MMSE chip equalizer output SINR is eact. The situation is ifferent at the symbol-level where the bias, in practice, varies over time. However, this issue is beyon the scope of this paper an will be iscusse elsewhere. The per-coe capacity of the ith ata stream therefore correspons to C i = logsinr i 2 C i = log MMSE i Our objective is to choose the precoing matri W to maimize the sum-capacity of two streams. This boils own to the following optimization problem: W opt =argma W [ log σ 4 a MMSE MMSE 2 6 ]. 7 The optimum precoing matri can be seen to minimize the prouct of MMSEs of the streams. By eploiting the structure of the matrices in the unitary coebook specifie in the HSDPA stanar [], the optimum precoing matri W opt maimizes R wr 2, wherer 2 is efine in appeni A as the off-iagonal term of the error covariance matri R z z. In other wors, the W opt attempts to maimize the SINR ifference between the two streams. B. Receiver 2: MMSE Chip Equalizer-Symbol evel MMSE In an alternative receiver structure, the output of the chip-equalizer is fe into a symbol level spatial MMSE filter after the escrambler/correlator block. This is shown in Fig. 3. As iscusse in III-A, the output of the correlator is givenby4. enotes the [j] [n] z k[n] c H k S H n W H B Fig. 3. Chip MMSE equalizer an correlator followe by symbol-level spatial MMSE. spatial MMSE at the output of which we have a linear estimate of the symbol vector as =a k [n] ã k [n]. 8 The error covariance matri for the MMSE estimate of a k [n] is given by Rãã = R aa R az R z z R z a 9 = σ 2 ai σ 4 aw H σ 2 ai B R z z B H W. Epressing the above relation in terms of the correlator output covariances, BR z z B H an using some algebra leas to the epression Rãã = σ 2 ai σ 4 aw H σ 2 ai R z z W R zz. ike the MMSE chip level equalizer/correlator RX, this translates to a sum-capacity epression similar to the one erive in the previous section. 4 C C 2 =log 2 etiagrãã The throughput maimizing precoing matri can therefore be shown to be the one with element w that maimizes [ R w I 2 R z ] R zz One may remark that spatial MMSE processing after the equalizer/correlator stage shoul lea to further suppression of resiual to its best abilities given the limite resolution of W

3 interference an lens itself to low-compleity per-coe implementation. The spatial channel sees a non-negligible contribution from the kth coe esire coe, as seen in section IV, RX 2 oes mprove on RX but its performance is still limite by the temporal inter-chip interference that is still sufficiently strong at the correlator output. C. Receiver 3: MMSE Chip Equalizer - Preictive DFE A noise-preicive ecision feeback equalizer DFE [5] uses past noise estimates to preict the current noise sample. This is reaily applie to our spatial-multipleing problem where once one stream is etecte, spatial correlation of noise spatial interference can be eploite to improve estimation of the stream etecte last secon in this case. With some abuse of terminology this can be brane Successive Interference Cancellation SIC. The SIC receiver is shown in Fig. 4. Denote the output of the correlator as u k [n], written as u k [n] =W H B z k,n = a k [n] W H B ũ k [n] 3 The covariance matri R ũũ, the iagonal bias matri B an R z z, the covariance matri of z can be relate as R ũũ = W H B R z z B H W F H sp 4 Assume a 2 2 lower triangular filter G sp with unit iagonal an the remaining element g 2 such that r[n] =G sp ũ k [n]. Then the new error covariance matri is given as R r r = GspR ũũ GH sp. 5 which is minimize if R r r = D, i.e., a iagonal matri an the problem boils own to the estimation of the error term in stream 2 from stream. Towars this en, consier DU factorization of R ũũ = DH. Then, G sp = minimizes 5. Denoting elements of R ũũ as r ij as in 25, the elements of D are given as σ 2 r = r an σ 2 r 2 = r 22 r 2r r2 = etr ũũ = etetb R z z B H etf H sp. 6 Thus MMSE for stream is σ 2 r an that of stream 2 is σ 2 r 2.As epicte in fig. 4, this can be interprete as stream achieving the same performance as for the chip-level MMSE/correlator - spatial MMSE RX 2 above, while stream 2 benefits from stripping an thus achieves the spatial MFB. The rates are therefore epresse as [j] â 2,k [n] [n] c H k S H n r[n] z k[n] G sp W H B ec u k [n] â,k [n] Fig. 4. Chip MMSE equalizer/correlator followe by spatial MMSE an symbol-level SIC for stream 2. C i =logsinr i 7 Another interesting observation is that the SINR epression for stream 2 in the symbol-level SIC case is inepenent of the precoing W applie. Discussion: In this receiver, stream shoul ehibit better performance than in the case of RX. An alternative receiver structure propose in [3] is also possible where stream processing is just limite to the chip equalizer-correlator cascae an stream 2 is subjecte to symbol-level SIC as above. However, RX 3 is a better alternative to [3], since in this case, stream shoul get an aitional boost in SINR ue to the spatial MMSE processing. This shoul not only amplify stream rate, but also has the esirable effect of improving stream etection. This improve reliability, although not relevant in this iscussion where we assume ieal suppression of stream is all-important in practical implementations, reucing chances of error-propagation uring the interference cancellation stage an hence irectly impacting etection performance of stream 2. D. Receiver 4: Chip evel SIC Inee a better known SIC receiver etects ata symbols from one stream, say stream an respreas, rescrambles, rechannelizes etecte ata, the contribution of that stream can be subtracte from the receive signal. The secon stream can now be etecte using a new FIR MMSE chip-level receiver obtaine as where, f sic = σ 2 b 2 hh w h H 2 R yy, 8 y[n] =T HS[n]CA 2[n]V [n], 9 an T H = 2 T H wt H 2. This case, assuming perfect cancellation of stream, is analogous to single stream communications an the SINR achieve for stream 2 is much improve. The SINR epressions for this SIC receiver are straightforwar an similar to the ones for the MISO MMSE chip-level equalizer/correlator case see appeni A. It must be note that there is significant structural ifferences between the two SIC receivers that also translate to behavior ifferences - one such consieration is the possibility of chip-level SIC to cancel intercell interference. One further consieration in RX 4 is that if stream [j] f sic z [n] c H k S H n Ĥ z w W H B â 2,k [n] S n C â,k [n] Fig. 5. Chip MMSE equalizer/correlator followe by spatial MMSE an chip-level SIC for stream 2. symbol estimates are obtaine at the output of a spatial MMSE, this woul also imply spatial processing for stream 2 since spatial processing by nature is simultaneous. Such treatment increases compleity but may be well worth the effort in terms of SINR gains an as iscusse for RX 3 above, the quality of the estimates of stream before feeback. Different Types of SIC Receivers: The noise-preictive DFE is harly comparable to chip-level SIC receiver in any other way ecept that symbols on streams are etecte in the orer of ecreasing SINR. While the former eploits noise plus interference correlation between streams to improve SINR of symbol etecte last, the latter benefits from stripping of spatiotemporal interference of the entire etecte stream, where for stream etecte last, all streams can henceforth be consiere non-eistent assuming perfect cancellation. Not only o streams see ifferent levels of interference, a new chip-equalizer can be calculate at each stage that benefits from 895

4 a larger noise-subspace to cancel remaining interference. For SIC, stream etecte last is known to attain the Matche-Filter Boun MFB. A more general feeback has also been propose in [6] where where it was calle chip-level DFE but in fact it is symbol-level DFE the ecisions are on the symbols, not on chips. Even though the feeback interference cancellation is performe at chip level after respreaing, but that is equivalent to canceling at symbol level an the equivalence of that solution with RX 4 is not straightforwar. In general, many DFE/SIC esigns are possible. MMSE CE RX:2 MMSE CE Spatial MMSE SNR=5B E. Receiver 5: Spatial M Receiver Another possible receiver structure is shown in Fig. 6 where the chip-equalizer correlator front en is followe up, as before, by the spatial MMSE stage. The resulting spatial miture u k [n] =z k[n] =a k [n] ũ k [n], 2 is later processe for joint etection coe-wise M etection of the two symbol streams. The M metric is given as follows. D = {u k [n] a k [n]} H R {u k[n] a k [n]}. ũũ This metric can be solve for a k [n]. It was shown in [3] that joint [j] [n] W H B u k [n] Capacity bouns Fig. 7. Upper bouns on the sum-capacity at the output of RX an RX 2. MMSE CE RX:2 Preictive DFE RX:2 M per coe SNR=5B arg min a k,n {D}.3.2 Fig. 6. Chip MMSE equalizer/correlator followe by spatial MMSE an joint etection. etection outperforms SIC. It must be however be note that the SIC structure in [3] aresses a SIC applie irectly at the output of the chip equalizer-correlator output. Thus stream gets the same SINR as the chip-equalizer while in our case, stream woul also reap the benefits of spatial MMSE processing. For joint etection, the SINR for the ith stream correspons to the MFB of spatial channel resulting from the cascae of an B. The MFB can be interprete as the SNR of ith stream when it is etecte assuming that symbols of the other streams are known. R ũũ is the noise variance. IV. SIMUATION RESUTS We present here the simulation results an compare the performance of the ifferent receiver structures base on their sumcapacity. For a fie SNR an over several realizations of a frequency selective 2m 2 MIMO FIR channel Hz, we compute the optimal precoing matrices an use the corresponing SINRs of both streams at the output of the receivers to calculate an upperboun on the sum capacity. The channel coefficients are comple value zero-mean Gaussain of length 2 chips. We assume FIR MIMO equalizers of length comparable to the channel. The sum-capacity CDF is thus use as a performance measure for all receivers. The structure of the precoing matrices use in HSDPA is such that two out of the four possible precoing matrices give the same SINR an thus sum-rate for the MMSE/correlator esign. The ifference between them being that one favors stream by bestowing a higher SINR for stream, an the other matri oes just the reverse. This means that one can not only achieve the same sum-rate by choosing any of the two matrices, but one can also choose which stream among the two, contributes a larger fraction of the sum. Without loss of generality, in all our simulations, we choose the matri that maimizes the SINR of stream. Fig. 7 shows istribution of sum-capacity at the output of the MMSE chip-equalizer correlater receiver an that of the spatial MMSE receiver. With an aitional processing stage of a very small Capacity bouns Fig. 8. Sum-capacity at the output of RX, RX 3, an RX 5. compleity we are able to see some gain in the achievable rates of the receiver. In Fig. 8 we compare the performance of RX with RX 3 an RX 5. As before, optimal precoing matrices are use at the base-station. RX 3 benefits slightly from the aitional spatial processing for both streams an a non-linear equalization stage for stream-2. That the gain is not consierable is ue to the fact that stream- oes not benefit from non-linear equalization. Since the performance measure is the sum-capacity of both streams, the performance of this receiver is limite by the performance of stream-.rx 5 on the otherhan performs better than RX 3 thanks to spatial M etection performe on a per-coe basis. In Fig. we raw attention to the fact that one shoul eercise caution while choosing the metric for M etector in orer to compute the correct MFB. The correct metric takes into account the correlation in noise at input of the etector.the chip-level SIC, in Fig. 9 as can be epecte, outperforms all other receivers at the cost of a significant compleity at the receiver. V. CONCUSIONS In this contribution, we erive analytical epressions for the choice of the precoing matri when the precoing matrices are unitary an the receivers are base on MMSE esigns. We also compare five istinct receiver structures for D-TAA MIMO HSDPA all base on the MMSE chip-level equalizer/correlator as the first processing stage an presente performance comparison of these receivers. The MIMO precoing scheme for HSDPA is such that one can favour any one of the two streams. Two versions of SIC receivers were shown an the funamental ifferences between chip-level ecisionfeeback SIC an symbol-level SIC were pointe out. Chip-level SIC receiver inee performs far better than all per-coe symbol-level receivers while in the class of latter, joint M etection outperforms 896

5 .3.2. MMSE CE Chip evel SIC SNR=5B Capacity bouns Fig. 9. Sum-capacity at the output of RX M metric with colore noise M metric with white noise SNR=5B Capacity bouns Fig.. MFB for RX 5 all others if the metric for M properly takes into account the spatial correlation among the two streams. APPENDIX A. Estimation of Error Covariance R at MMSE Chip- Equalizer Output We first consier linear MMSE FIR estimation of the 2 chip sequence. Referring back to fig., b[j] is the input chip vector efine as b[j] = [b [j] b 2[j]] T, where b i[j] is the jth chip of the ith input stream. Each chip stream is the sum of K sprea an scramble CDMA sub-streams user per CDMA coe. Thus b i[j] = K k= b ik[j].the2 2matri H[j] is the jth MIMO element of the FIR channel an W is the precoing matri. et us assume an arbitrary oversampling factor m. Then, the 2m receive signal at the jth time instant is given as = N l= H[l]Wb[j l]v[j] =HW N b N [j]v[j], 2 where H = [H H 2], with H i being the 2m N is the FIR channel from the ith transmit antenna to the 2 RX antennas. W N = W I N an b N [j] =[b T,N [j] b T 2,N [j]] T where b i,n [j] =[b i[j N ]... b i[j]] T is chip sequence vector of the ith stream. Stacking E successive samples of the receive signal, we can epress the receive signal as Y [j] =T EHW NE b NE [j]v [j], 22 where T EH = [T EH T EH 2] an T EH i is a block Toeplitz matri with [H i 2m E ] as the first block row. et us assume a 2 2mE MMSE equalizer F =[f T f T 2 ] T. The output of the equalizer is a linear estimate of the chip sequence given by [j] =FY[j] =BWb[j] [j] BW NE b NE [j]fv[j]. [j] 23 Defining α ij = f i T EH j, wehave [ α B = α 2 ] [ ] α α α 2 α 22 an B = 2 α 2 α 22, respectively are the 2 2 matri that represents the joint bias in the equalizer output, an the resiual inter-chip interference ICI. The α ii are the same as α ii with the α ii term replace by, an is the equalization elay associate with F. The joint-bias can also be interprete as a spatial miture at the chip-equalizer correlator output facilitating formulation of the spatial signal moel to be treate henceforth. It must be pointe out that the spatial channel B is so efinable assuming the scrambler to be a ranom sequence. The resulting spatial channel is per-coe, while still being the same for all coes. The MMSE of the MMSE chip-equalizer is given by R.We can show that R = R R R R, 24 an the error variance can be epresse as [ ] R = r r 2 r 2 r, from which the MMSE can be obtaine. In the above, r = σb 2 α 2 α 2 2 f Rvvf H r 22 = σb 2 α 2 2 α 22 2 f 2 Rvvf H 2 26 r 2 = r2 = σb 2 α α 2H α 2 α 22H f Rvvf H 2 B. Estimation of Error Covariance at Correlator Output R z z Consiering scrambler as a ranom sequence an taking epectation over the scrambler s[j] as well as input ata symbol sequence, one can show that the covariance matri of the estimation error R z z is similar to the chip-equalizer output error covariance matri R with scaling of the interference quantities by the number of users coes. We can show that r = α 2 K 2 α 2 2 f Rvvf H α 2 2 α 22 2 r 22 = σ 2 a K r 2 = r 2 = σ 2 a K f 2 Rvvf H 2 α α 2H α 2 α 22H f Rvvf H 2 REFERENCES [] 3GPP, TS Physical layer proceures FDD Release 7, May 27, version [2]. Mailaener, inear MIMO equalization for CDMA ownlink signals with coe reuse, IEEE Transactions on Wireless Communications, vol.4, no. 5, pp , September 25. [3] J. C. Zhang, B. Raghothaman, Y. Wang, an G. Manyam, Receivers an CQI measures for MIMO-CDMA systems in frequency-selective channels, EURASIP Journal on Applie Signal Processing, no., pp , November 25. [4] K. Ko, D. ee, M. ee, an H. ee, Novel sir to channel-quality inicator CQI mapping metho for HSDPA system, in Proc. IEEE Vehicular Technology Conference, Montreal, Canaa, September 26. [5] J. M. Cioffi, G. P. Duevoir, M. V. Eyuboglu, an G. D. Forney, MMSE Decision-Feeback Equalizers an Coing. Part : Equalization Results, IEEE Trans. Communications, vol. 43, no., Oct [6] J. Choi, S.-R. Kim, Y. Wang, an C.-C. im, Receivers for chiplevel ecision feeback equalizer for CDMA ownlink channels, IEEE Transactions on Wireless Communications, vol. 3, no., pp. 3 33, January