SSO Simulation with IBIS
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1 SSO Simulation with IBIS Manfred Maurer Industrial Solutions and Services Your Success is Our Goal Manfred Maurer Folie 1
2 Motivation SSN with IBIS in 2000 Simulation setup BEHAVIOR model with Voltage-Controlled Current Sources very good concordance with transistor based models Table driven kssn-multiplier Multiplier extraction Results HSPICE vs. VCCS-BEHAVIOR Lacking concordance VCCS-BEHAVIOR Additional RC Timing coeficient Improved results Manfred Maurer Folie 2
3 Acknowledgements INFINEON TECHNOLOGIES HYB18T512160AF DDR2 - Memory TEXAS INSTRUMENTS CDCE706 PROGRAMMABLE 3-PLL 3 CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER Manfred Maurer Folie 3
4 SSO Simulation Setup ( m+1 switching outputs ) TRANSMITTER RECEIVER H / L T1 Quiet Output tr-line R1 VCC Package RLC Package RLC R VD D C VDD L VD D I F1 =m x I VDD I VDD I GND T2 Switching Output tr-line R2 R GND I F2 =m x I GND L GND C GND GND Manfred Maurer Folie 4
5 VCCS-Model enhancement VDD kssnr(vdd-vss) * kpu(t) *Ipu(Vout) Ipc(Vout) C_comp/2 OUT kssnf(vdd-vss) * kpd(t) *Ipd(Vout) Igc(Vout) C_comp/2 A second multiplier for rising (kssnr) and falling (kssnf) edges Both multipliers are controlled by the (Vdd-Vss) voltage drop Feedback on the gate source voltage of the output transistors Multiplier generation: Pullup/down V/I-tables as a function of Vdd SSO-V/t-table (Golden Waveform) VSS Manfred Maurer Folie 5
6 VCX16244 SSN analysis results (rising edge) two waveform behavioral model Number of SSO = 6 Node NodeOUT: Transistor Transistor based based Behavioral Behavioral Node NodeEND: Transistor Transistor based based Behavioral Behavioral Manfred Maurer Folie 6
7 kssnr/f Multiplier Generation Method CMOS Driver Output High Characteristic I(3.3V) I(3.6V) kssnr(3.6v) = I(3.6V)/I(3.3V) 50 Ohm loading characteristic Manfred Maurer Folie 7
8 kssn rising coefficient extraction HYB18T512160AF (DDR2) INFINEON Manfred Maurer Folie 8
9 kssn falling coefficient extraction HYB18T512160AF (DDR2) INFINEON zoom Manfred Maurer Folie 9
10 kssn falling coefficient extraction (zoom) HYB18T512160AF (DDR2) INFINEON Manfred Maurer Folie 10
11 HYB18T512160AF / INFINEON kssn Vdd = 0.5V to 3.6V (1.8V nom.) 2,0000 1,5000 Vdd_nom kssn 1,0000 kssnr kssnf 0,5000 0,0000 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 2,2 2,4 2,6 2,8 3 3,2 3,4 3,6 Vdd (V) Manfred Maurer Folie 11
12 TI CDCE706 TEXAS INSTRUMENTS kssn Vdd = 0.5V to 5V (3.3V nom.) 1,600 Vdd_nom 1,400 1,200 1,000 kssnf kssn 0,800 0,600 slew rate max kssnr kssnr_00 kssnf_00 0,400 slew rate min 0,200 0,000 0,3 0,6 0,9 1,2 1,5 1,8 2,1 2,4 2,7 3 3,3 3,6 3,9 4,2 4,5 4,8 Vdd(V) Manfred Maurer Folie 12
13 DDR2 buffer Infineon Supply voltage drop ( L=2x1nH) / Load Tline Zo=50 Ohm IBIS VCCS + kssn Transistor based w/ pkg w/o pkg Manfred Maurer Folie 13
14 TI CDCE706 / Voltage drop / Rising edge VCCS-model with kssn table ( L=2x3nH) transistor based model VCCS + kssn IBIS / NO PKG transistor based model VCCS + kssn Manfred Maurer Folie 14
15 TI CDCE706 Rising edge vs. Vdd drop Transistor based model Vdd=3.3V Vdd drop L=1nH 9nH drop Manfred Maurer Folie 15
16 TI CDCE706 Falling edge vs. Vdd drop Transistor based model Vdd drop L=1nH 9nH Vdd=3.3V drop Manfred Maurer Folie 16
17 Differences VCCS 2000 vs Transition Time Operation Point Vdd/GND drop amplitude width Design of the OUTPUT stage Time domains Slew rate control VCCS 2000 VCCS 2006 ca. 5ns saturation region <500ps linear region ca. 15%Vdd ca. 40% Vdd ca. 7ns NO Vdd-drop drop Feed back NO On-die capacitance NO/YES NO/YES NO ca. 1ns YES YES YES YES YES Manfred Maurer Folie 17
18 Vdd drop improvement with Cpre=30pF CDCE706 with PKG L=2x3nH 10 SSO Manfred Maurer Folie 18
19 Vdd drop improvement with Cpre=30pF CDCE706 with PKG L=2x3nH 10 SSO Manfred Maurer Folie 19
20 VCCS-Behavior Model with kssn (static) and td_rc (dynamic) coefficients td_rc td_rcdetermination determination td_rcr(vdd-vss) * kssnr(vdd-vss) * kpu(t) *Ipu(Vout) Ipc(Vout) VDD C_comp/2 -by -byoptimisation optimisationthrough through the known knownl --by byadjustment adjustmentfrom from I=I(t) I=I(t) table L td_rcf(vdd-vss) * kssnf(vdd-vss) * kpd(t) *Ipd(Vout) Igc(Vout) C_comp/2 OUT VSS Manfred Maurer Folie 20
21 Vdd drop improvement DDR2 with PKG L=2x3nH 5 SSO Manfred Maurer Folie 21
22 Vdd drop improvement CDCE706 with PKG L=2x3nH 10 SSO Manfred Maurer Folie 22
23 With improved IBIS models,, SSO can be simulated in a better concordance with transistor based models, IF kssn table information (BIRD 97.x) current vs. time known RLC environment (BIRD 95/98) Advantages Signal integrity analysis PDS Voltage drop Timing simulation More investigations have to be done, to evaluate for different technologies, the validity range and the accuracy of the proposed improvement Manfred Maurer Folie 23
24 SSO Simulation with IBIS Thank you for your attention Manfred Maurer Industrial Solutions and Services Your Success is Our Goal Manfred Maurer Folie 24
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