Unified Padring Design Flow

Transcription

1 2013 First International Conference on Artificial Intelligence, Modelling & Simulation Unified Padring Design Flow Ang Boon Chong, Ho Kah Chun PMC-Sierra, Design Service, Penang,Malaysia Abstract In the early design phase, padring design is one of the critical elements in design planning. The result from padring design not only will impact packaging, board level design, power integrity and signal integrity result, but also the overall product cost.in the past, padring design is often done through separate standalone tool like Orbit IO or internal excel estimation spreadsheet. The intend of this paper is to share the unified padring design methodology where single design database is referenced hence padring design will always be in sync with fullchip backend database. Unified padring flow allows consistent cross functional review reference point as well as better controllability for core and padring design integration. Hopefully the methodology proposed will benefit the padring designers in floorplanning and product cost estimation through unified padring flow. Keywords ASIC Padring Design, Padring I. INTRODUCTION In the early chip design planning phase, padring design is one of the early design critical aspects as it involves continuous iteration of board level design, packaging power integrity and signal integrity team feedback. The different design space consideration for chip design, package design and board design can be summarized as in Table I [1]-[10]. capacitance(decap) deployment on high speed I/O interface voltage domain. The interdependency of multi-disciplinary between IC design, package design and board design, the geographical separation of design teams, shorter design cycle and increase in design complexity such as demand for high speed interfaces and multiple voltage domain, demands for faster iteration of padring floorplanning at early design stage to minimize overdesign and associated cost impact. In the past, padring design is done through the following methods: Excel spreadsheet Proprietary tool ASCII files OrbitIO Padring design through excel spreadsheet is done through visual basic scripting. Example of excel spreadsheet is as shown in Figure 1. TABLE I. CO-DESIGN SPACE CONSIDERATION[1]-[10] IC Design Space Package Design Space Board Design Space I/O padring optimization Package routability Package optimization Signal performance Signal performance PCB symbol creation Timing Optimization Package ball timing delays Inter Package pin timing delays Power delivery network Power Optimization PCB footprint creation optimization Chip Physical Verification LVS across fabrics Board Design LVS From Table I, the I/O padring optimization in chip design will affect the package routability due to the bump to ball optimization is done within the package. I/O padring optimization will also affect the number of package routing layers required due to the power distribution noise (PDN) specification requirement that package design team need to meet as well as possible package decoupling Figure 1. Excel Spreadsheet Padring Design Planner. The disadvantages of Excel spreadsheet solution in padring design are: 1. The technology dependence update is hardcoded within the spreadsheet. There is no clear segregation of technology node update to allow live update from the technology group and feed into the spreadsheet as direct input. 2. The padring floorplan calculation is fixed at specific floorplan aspect ratio without potential area optimization /13 $ IEEE DOI /AIMS

2 3. The text based floorplan generated is lack of coherent with physical design database. The padring design flow with excel spreadsheet is as shown in Figure 2. iteration during design planning phase within single environment. However OrbitIO padring design flow still has the risk of design planning phase being restarted during design implementation due to design validation feedback. Figure 4. OrbitIO Padring Design Flow Figure 2. Traditional Padring Design Flow As shown in Figure 2, the traditional padring design flow involves continuous iterations between 2 design phase where chip design at design implementation may potentially restart the bump and IO placement loopback process due to design validation feedback. For OrbitIO design, it is a java based compiled tool from Sigrity. Example of OrbitIO padring design tool is shown in Figure 3 [11]. The padring design flow interaction with various functional group is shown in Figure 5 Figure 5. Padring Design Interaction Figure 3. OrbitIO Padring Planner[11] The design flow with OrbitIO is shown in Figure 4. By comparing Figure 4 and Figure 2, OrbitIO padring design flow does show improvement compare to traditional padring design flow as OrbitIO consolidates the design From Figure 5, padring design deals with various functional groups. Each functional groups has specific area of interest. For example, marketing group s primary interest will be the cost and customer ball bond out, packaging team s primary interest will be signal integrity, power integrity as well as package routing cost and test group s primary interest will be test plan and test features. The objective of this paper is to share the unified padring design flow. This paper will focus on single die implementation only. For multi-die padring floorplanning, 3D implementation padring planning and package-die codesign aspect will not be covered within this paper. Hopefully the readers can benefit from the sharing

3 II. UNIFIED PADRING DESIGN FLOW The unified padring design flow aims to address the following concerns during padring planning phase: To provide clear standardization on input requirements To provide integrated padring development flow with layout To improve padring development efficiency The overview of unified padring design flow is shown in Figure 6. Figure 7. Ordered Padring Placement Generation Flow Figure 6. Unified Padring Design Flow From Figure 6, inputs to the unified padring flow are divided into device dependent information which is captured within a master spreadsheet and device independent category. The device independent is mainly technology node related specifications as well as some fixed rule for high speed interface signals from packaging as well as mixed signal IP s requirement. Based on the device dependent and device independent inputs, the whole process is automated through scripting to create unified design database where padring floorplanning and ASIC backend floorplanning can be accessed. Since it is an unified database, the possibility of golden database from padring planner off sync with the golden database used by ASIC backend floorplanner is eliminated. The unified padring flow can generate golden die for packaging team, BSDL for tester team, physical database as well as golden spreadsheet to ensure any incremental changes can be reflected within the golden device dependent spreadsheet. For current status of implementation, the BSDL and golden spreadsheet flow is still work in progress. Example of the internal flow within the order spreadsheet placement to create the unified golden database is shown in Figure 7. For the ordered padring placement shown in Figure 7, the DIE rule file contains the device independence rules used by the script while the device dependence information is available within the spreadsheet. The LEF file is the library exchange format defined by Cadence which contains the physical information of the library cells in ASCII format. At the end of the Padring generator, the place and route floorplan script is generated. The package rule requirement is handles within the covercell methodology. The covercell methodology consists of fixed IO signals and power cell bump placement for various IO standards. This methodology can ensure minimum package routing required at the expense of IO area efficiency. The covercell methodology is deployed at the initial state as a proof of concept before future investment on the bump pad placement optimization as well as RDL routing scripting development. The place and route script output format is pending on actual place and route tool used within the company. For this paper, only the floorplan outlook from the padring generation within the ASIC implementation tool will be shared. The DIE file output will not be discussed in this paper.the die file generation flow is as shown in Figure

4 Figure 8. Die File Generation Flow From Figure 8, die file generation flow shares the common inputs used the padring design automation. Hence, during implementation, the die file generation is incorporated as part of the unified padring design flow as shown in Figure 7 instead of standard-alone flow. The advantage of unified padring design flow versus the OrbitIO padring design flow is as shown in Table II below Figure 8. Unified Padring Design Flow Data Extraction The result of first padring floorplan generated within the ASIC implementation tool database is shown Figure 9 TABLE II PADRING FLOW COMPARISON Scenario OrbitIO padring generation Unified Padring Flow planning database off sync with layout database Yes No possibility of full respin due to project dependent source incremental changes Yes Incremental changes possibility of input data off sync with golden source Yes No possibility of full respin due to project independent source incremental change Yes Incremental changes easy prediction of changes impact to overall flow and respective required extremely good experience easier feedback from juniors to counter part resource project lead flow maintainance high low flow portability low high From Table 2, it is observed that heavy investment is required within unified padring flow due to the scripting work required, however it offers portability as well as turn around time improvement on the padring design iterations without the risk of database off sync. III. RESULT For the data extraction in unified padring design flow, the flow overview is as shown in Figure 8. Figure 9. Unified Padring Floorplan Snapshot 1 From Figure 9, this design is based on the IO limited floorplanning and I/Os are pre-assigned to 4 sides of the die. The unified padring generation flow is able to generate the smallest die required. In the 2 nd floorplan spreadsheet given, the generated floorplan snapshot is shown in Figure

5 designer are working on separate database where constant communication are required to ensure the changes is properly propagated up or propagate down during design implementation phase. For the unified flow turn-around-time (TAT), each iterations is within 2 hours as the flow is automated. Further improvement to the turn-around-time of the flow will be carried out once the overall framework is completed. IV. CONCLUSION The overall comparison of spreadsheet chipbuilder flow, OrbitIO padring generation flow and unified padring generation flow can be summarized as in Table III TABLE III. PADRING GENERATION FLOW SUMMARY Figure 10. Unified Padring Floorplan Snapshot 2 From Figure 10, the pad placement style is adjusted automatically to produce the optimum area based on the constrained given. The actual implementation for 2 nd implementation is shown in Figure 11. ACKNOWLEDGEMENTS Thanks to Alan Nakamoto and Chong Thow Pang for the support given. REFERENCES Figure 11. Actual Padring Floorplan For Snapshot 2 From Figure 11, the floorplan based on actual implementation is different from padring placement at the left IO placement and bottom IO placement of the die. The floorplan in Figure 11 is based on manual work through OrbitIO flow by layout engineer continuous feedback to the padring designer. Both fullchip layout engineer and padring [1] Jia-Wei Fang, YW Chang, Area-I/O flip-chip routing for chip package co-design, ACM International Conference on Computer- Aided Design, Nov 2008, California [2] Ming-Fang Lai, Hung-Ming Chen, An Implementation of Performance-Driven Block and I/O placement for chip-package codesign, ISQED, 2008 [3] Ren-Jie Lee, Hung-Ming Chen, Fast flip-chip pin-out designation respin for package-board codesign, IEEE VLSI, August 2009 [4] K.S.Lin, H.W. Hsu, R.J.Lee, H.M.Chen, Area-I/O RDL routing chip-package codesign considering regional assignment, EDAPSS, 2010 [5] J.F.Park, Board driven I/O planning&optimization, International Conference on CAD, Nov 2010, California [6] C.Y.Peng,W.C.Chao,Y.W.Chang,J.H.Wang, Simultaneous block and I/O buffer floorplanning for flip-chip design, Asia and South Pacific Design Automation Conference, 2006 [7] S.Logan,M.R.Guthaus, Package-chip co-design to increase flip-chip C4 reliability,isqed 2011 [8] H.M.Chen,I.M.Liu,M.D.F.Wong, M.Shao, L.D. Huang, I/O Clustering in Design Cost and Performance Optimization for Flip- Chip Design, ICCD 2004 [9] M.F.Yu,W.W.M.Dai, Single-layer fanout routing and routability analysis for Ball Grid Arrays, ICCAD,1995 [10] S.S.Chenl, W.D.Tseng,J.T.Yan,S.J.Chen, Printed circuited board routing and package layout codesign, IEEE Asia Pacific Conference on Circuits and Systems, 2002 [11]