Continuous Time Sigma Delta Modulators and VCO ADCs

Transcription

1 Continuous Time Sigma Delta Modulators and VCO ADCs Pieter Rombouts Electronics and Information Systems Lab., Ghent University, Belgium Pavia, March 2017 P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

2 Outline 1 Sigma Delta Modulation 2 Continuous Time Sigma Delta Modulation 3 FoM Confusion 4 VCO ADC 5 Conclusion P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

3 A/D converter: traditional interpretation I U converts analog value into digital number of bits n quantisation step q: error within ±q/2 staircase I/O static nonlinearity INL or DNL q = V ref /2 n P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

4 A/D converter: other interpretation I converts analog signal into digital signal quantisation eror Q (white) noise signal like other noise contributions number of bits not essential large enough Leave margin for other noise sources effective bits quantisation noise variance U σ 2 Q = q2 12 P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80 I Q U

5 Core concept 1: Oversampling signal spectrum white noise spectrum frequency/f sample frequency/f sample Oversampling ratio: OSR = f S 2f 0 P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

6 Core concept 1: Oversampling signal spectrum white noise spectrum frequency/f sample frequency/f sample ideal digital filter after quantizer averaging mechanism number of bits has increased less noise filters signal as well not Nyquist-rate anymore! P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

7 Core concept 1: Oversampling signal spectrum white noise spectrum frequency/f sample frequency/f sample quantisation noise variance σ 2 Q = 3dB/octave improvement q2 12OSR 1 OSR P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

8 The Σ control loop V in + D V in + + D H quant H - - Q DAC (a) (b) ideal DAC filter discrete time continuous time P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

9 The Σ control loop V in + D V in + + D H quant H - - Q DAC (a) (b) D = H 1 + H V in H Q for low frequencies H D V in nullator P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

10 The Σ control loop D = H 1 + H V in H Q }{{} error input signal is also filtered for low frequencies NTF = 1 1+H 0 for high frequencies NTF = 1 1+H 0 P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

11 Core concept 2: Noise Shaping NTF(z) 1 freq. DC f sample /2 for high frequencies NTF = 1 1+H 0 spectral shaping P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

12 Core concept 2: Noise Shaping signal shaped noise DC f sample /2 freq. DC f sample /2 freq. (a) (b) noise spectrum has the shape of NTF combine with oversampling most noise vanishes P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

13 Σ Modulators V in + D V in + + D H quant H - - Q DAC (a) (b) quantizer very few bits accuracy from oversampling + noise shaping 1 bit P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

14 Σ Modulators V in + D V in + + D H quant H - - Q DAC (a) (b) 1-bit quantizer simple inherent linear noise is not white tones stability P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

15 Σ Modulators V in + D V in + + D H quant H - - Q DAC (a) (b) multi-bit quantizer better performance DAC needs linearization DEM calibration always larger area P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

16 Σ Modulators V in + D V in + + D H quant H - - Q DAC (a) (b) filter cascade of integrators order: design parameter trade-off complexity-performance special design techniques Richard Schreier s toolbox P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

17 1st order, 1bit Σ Modulator Typical circuit C V in C - V ref b i + b - D Q i + clk switched cap devices can be very small also C (thermal) noise due to oversampling P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

18 High Order Σ Modulators Cascade of integrators with feedback u(n) b 1 b 2 b 3 b 4 -g 1 1 z -1 x 1 (n) c 1 1 z -1 x 2 (n c 2 1 z -1 x 3 (n) c 3 y(n) v(n) -a 1 -a 2 -a 3 DAC without extra feed ins high swing on internal nodes poor distortion performance P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

19 High Order Σ Modulators Cascade of integrators with feedforward u(n) b 1 b 2 b 3 b 4 -g 1 1 z -1 x 1 (n) c 2 1 z -1 x 2 (n c 3 1 z -1 x 3 (n) a 3 y(n) v(n) -c 1 a 2 a 1 DAC without extra feed ins negligible swing on internal nodes excellent distortion performance P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

20 Σ ADC analog digital f cutoff < f S f = f cutoff 0 V in anti-aliasing prefilter f S Sigma Delta modulator lowpass filter 2f 0 D out decimation filter several filters in chain simple anti-aliasing filter no sample-to-sample correspondence number of bits in D out high enough P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

21 Σ ADC analog digital f cutoff < f S f = f cutoff 0 V in anti-aliasing prefilter f S Sigma Delta modulator lowpass filter 2f 0 D out decimation filter scientific literature without filters accuracy calculated from ideal filter P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

22 OSR Low OSR? keep f s feasable need many quantizer bits need high order filter minimum 8 High OSR? small devices noise is filtered low filter order 1-bit quantiser P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

23 Outline 1 Sigma Delta Modulation 2 Continuous Time Sigma Delta Modulation 3 FoM Confusion 4 VCO ADC 5 Conclusion P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

24 CTSDM vs DTSDM Σ modulators oversampling and noise shaping high-accuracy P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

25 CTSDM vs DTSDM Discrete-time versatile simple design easy to abuse standard cell IP core Continuous-time potential for higher speed potential for lower power anti-aliasing non-trivial design (needs tuning) performance and stability depend on fclk common myth: sensitive to clock jitter P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

26 Continuous Time Σ modulator V in (s) Σ a 1 st s Σ... Σ a N sts f s quant D out(z)... ZOH(s) closed feedback loop cascade of integrators with feedback cascade of integrators with feedforward... loop filter = continuous time sampler inside loop P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

27 Continuous Time Σ modulator Linearized model Q V in (s) Σ a 1 st s Σ... Σ a N sts f s Σ D out(z)... ZOH(s) output contains two contributions Input signal Quantisation noise superposition P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

28 Quantization noise Q Σ a 1 st s Σ... Σ a N sts f s Σ D out(z)... ZOH (s) Q Σ D out (z) f s H eq (z) H (s) ZOH (s) equivalent discrete time loop filter H eq (z) fully equivalent impulse invariant transform of H(s) CT - DT relationship: z = e st clk P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

29 Quantization noise Q Σ D out (z) f s H eq (z) H (s) ZOH (s) 1 H eq + 1 Q = NTF Q equivalent to DT Σ modulator P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

30 Quantization noise Q Σ D out (z) f s H eq (z) H (s) ZOH (s) remarks theory = mature e.g. c2d function in matlab H eq depends on Dac-pulse H eq depends on f s H eq sensitive to analog imperfections excess loop delay parasitic (opamp) poles P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

31 Continuous Time Σ modulator Linearized model Q V in (s) Σ a 1 st s Σ... Σ a N sts f s Σ D out(z)... ZOH(s) output contains two contributions Input signal Quantisation noise superposition P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

32 Input signal V in (s) Σ a 1 st s Σ... Σ a N sts f s D out(z)... ZOH (s) V in (s) G(s) f s Σ D out (z) f s H eq (z) H (s) ZOH (s) P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

33 Input signal V in (s) G(s) f s Σ D out (z) f s H eq (z) H (s) ZOH (s) V in (s) G(s) f s NTF(z) D out (z) V in (s) G(s) NTF(z) f s D out (z) AAF(s) equivalent to filter AAF (s) = G(s) NTF (z = e st clk ) followed by sampler P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

34 Anti-Aliasing in CTSDM AAF (s) = G(s)NTF (z) Double filter effect in alias bands (around nf clk ) G(S) lowpass filter NTF (z) notches at nf clk P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

35 Anti-Aliasing in CTSDM Amplitude response (db) AAF (s) G(s) NT F eq (e sts ) N = 2 a 1 = a 2 = f/f s P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

36 Feedback vs Feedforward V in (s) Σ a 1 st s Σ... Σ a N sts f s quant D out(z)... ZOH(s) cascade of integrators with feedback double anti-aliasing: G(s) and NTF less stringent prefiltering requirements large internal signal swing more demanding opamps ADC itself = power hungry but system may be more efficient P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

37 Feedback vs Feedforward a 1 a 2 V + in - + st st st + + a n D quant T H DAC (s) cascade of integrators with feedforward single anti-aliasing: NTF but G(s) does not filter stringent pre-filtering requirements small internal signal swing no demanding opamps ADC itself = efficient but system may be power hungry P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

38 Noise and power a 1 a 2 V + in - + st st st + + a n quant T D H DAC (s) First stage noise dominates later stages scaled lower power still negligible noise First stage power dominates as well increasing order moderate impact on power P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

39 Circuit Noise Ev 2 n = 4kTR eff B noise sees anti-aliasing filter only in band noise no kt /C noise in theory much better than SC P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

40 Excess Loop delay CTSDM problems a 1 a 2 V + in - + st st st + + a n T quant D H DAC (s) parasitic loop delay also parasitic poles P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

41 Excess Loop delay CTSDM problems Σ V c1 in (s) sts Σ c2 sts g c3 sts a 3 a 2 a 1 Σ d f s V out (z) H DAC (s) z 1 H DAC (s) e sτ z 1 2 parasitic loop delay make loop delay explicit add compensation path also for parasitic poles P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

42 Process variations CTSDM problems Σ V c1 in (s) sts Σ c2 sts g c3 sts a 3 a 2 a 1 Σ d f s V out (z) H DAC (s) z 1 H DAC (s) e sτ z 1 2 large errors on RC products tune robust design P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

43 Slew rate CTSDM problems opamp not allowed to slew injection of quantisation noise multi-bit some filtering (e.g. FIR) P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

44 Jitter CTSDM problems Σ V c1 in (s) sts Σ c2 sts g c3 sts a 3 a 2 a 1 Σ d f s V out (z) H DAC (s) z 1 H DAC (s) e sτ z 1 2 jitter in outer feedback DAC directly affects performance depends on DAC pulse P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

45 Jitter CTSDM problems clock clock ZOH ZOH ZOH white jitter catastrophical solution: multi-bit, FIR etc. lowpass jitter (= reality) no big deal P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

46 CTSDM vs DTSDM Continuous-time inherent anti-aliasing no noise aliasing cfr kt /C noise in switched cam better power-noise trade off common myth sensitive to clock jitter not as bad as widely assumed facts performance and stability depend on fclk non-trivial design P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

47 Outline 1 Sigma Delta Modulation 2 Continuous Time Sigma Delta Modulation 3 FoM Confusion 4 VCO ADC 5 Conclusion P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

48 Figure of Merit Need for FOM difficult to compare ADC architectures different Peak SNDR, Power, Bandwidth, Technology, area which architecture for new design? P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

49 Figure of Merit Walden s FOM (1999) FOM W = P 2 ENOB 2 BW pj/conversion code (or pj/conversion step) intended to reduce variables no justification used for many years but meaningless... P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

50 Justifying Walden s FOM? FOM W = in good design: P BW OK P 2 N??? P 2 ENOB 2 BW P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

51 Justifying Walden s FOM? P 2 N??? V ref + - D clk Q 0 V in flash 2 N comparators OK if comparator power constant comparator accuracy 2 N oops... comparator power 2 N comparator power 2 2N D Q clk D Q clk D Q clk P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

52 Impedance Scaling laws C R 2C R/2 V V I W L 2I 2W L (a) (b) start from best design possible need 3dB better SNR scale impedances: factor 2 power: factor 4 per bit P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

53 FOM confusion FOM W = P 2 ENOB 2 BW Walden fixed (scaling laws) P FOM W,fixed = 2 2 ENOB 2 BW all high accuracy designs were rated bad... SAR s were overrated... P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

54 FOM confusion FOM W,corrected = Walden fixed (scaling laws) not used P 2 2 ENOB 2 BW correct FOM: Schreier s FOM (2005) ) FOM S = Peak SNDR + 10log 10 ( BW P P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

55 Outline 1 Sigma Delta Modulation 2 Continuous Time Sigma Delta Modulation 3 FoM Confusion 4 VCO ADC 5 Conclusion P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

56 VCO-ADC: drivers N stages v in+ 4x 1x 1x v out- Vdd 2W Ctrl v in- 4x main inverters aux inverters v out+ W Ctrl quest for more digital ADC s ring oscillators digital signals no opamps P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

57 VCO-ADC naive f s f s V in k v f c reset D VCO 1 counter accuracy f VCO f s e.g. 6-bit for f s = 1GHz, f VCO = 64GHz, P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

58 VCO-ADC equivalent f s f s V in k v f c reset D VCO 1 counter V in f s k v f c DI VCO 1 counter 1 - z -1 D P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

59 VCO-ADC in phase domain f s V in k v f c D I VCO 1 counter 1 - z -1 D f f s c f c V D in I k v + 1/s quant D 1 - z -1 phase = integral of frequency edge occurs when phase = n 2π phase information is quantized with step = 2π P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

60 VCO-ADC in phase domain f c Q V D in I k v + 1/s + f s D 1 - z -1 ( ( ) ) Vin 1 z 1 D(z) + ( 1 z 1) Q s }{{} NTF like 1st order CTSDM anti-aliasing noise shaping boost accuracy by oversampling P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

61 multi-phase VCO-ADC N stages v in+ 4x 1x 1x v out- Vdd 2W Ctrl v in- 4x main inverters aux inverters v out+ W Ctrl untill now 1 VCO output ring oscillator has N output phases use all N VCO-phases now phase transition at 2π/N quantization error: N times smaller higher effective number of bits P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

62 multi-phase VCO-ADC use all N VCO-phases counter triggered by N clock inputs? use parallelism P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

63 multi-phase VCO-ADC f s f s reset counter V in VCO adder D f s f s reset counter E.g. N = 64 phases, f s = 1GHz, f VCO = 1GHz, equivalent f s = 1GHz, f VCO = 64GHz, 6-bit P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

64 multi-phase VCO-ADC f s f s reset counter V in VCO adder D f s f s reset counter Reset counter? special case: 1 bit counter possible if fvco f s P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

65 1-bit counter for VCO-ADCs f s VCO [i] ^ clk D Q ^ clk D Q D out DFF (a) +1 VCO CLK D out < > < > < > T S TS TS (b) t t t reacts on both edges effectively fvco,eff = 2f VCO P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

66 multi-phase VCO-ADC w1(t) D Q D Q fs x(t)... w2(t) fs D Q D Q... + y[n] w M(t) D Q D Q fs M-phases ring oscillator Readout circuit (xm) 2 important properties P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

67 multi-phase VCO-ADC w1(t) D Q D Q fs x(t)... w2(t) D Q D Q fs... + y[n] w M(t) D Q D Q fs M-phases ring oscillator Readout circuit (xm) output = barrel shifted thermometer encoded inherent DWA can drive unit element DAC summation = thermometer to binary coder P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

68 multi-phase VCO-ADC w1(t) D Q D Q fs x(t)... w2(t) D Q D Q fs... + y[n] wm(t) D Q D Q fs M-phases ring oscillator Readout circuit (xm) condition on f VCO : 0 < f VCO < f s /2 typical sizing: free running f VCO,0 = f s /4 KV for full scale swing some tuning P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

69 VCO-ADC challenges higher order noise shaping current research VCO non-linearity P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

70 VCO-ADC with high-order noise shaping Current work at UGent digital 3rd order VCO ADC prototype in 65 nm CMOS (with digital calibration) (without digital calibration) 3.5 mw 0.01 mm 2 P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

71 VCO-ADC challenges higher order noise shaping VCO non-linearity best: 11-bit linearity (UGent) other solutions digital (self)-calibration swing reduction embed in Sigma Delta Loop P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

72 Ghent University linear VCO circuit ring oscillator VCO non-linearity N stages V in Vdd Ring-Osc Ctrl R 1 R 2 Ctrl A. Babaie-Fishani and P. Rombouts, Highly linear VCO for use in VCO-ADCs, Electron. Lett P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

73 Ghent University linear VCO circuit VCO Frequency [MHz] ring oscillator VCO non-linearity VCO Frequency error [MHz] (a) Input voltage [volt] Input voltage [volt] (b) almost 12 bit linearity in pseudo differential configuration some noise penalty P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

74 digital (self)-calibration ring oscillator VCO non-linearity V in non-linearity f( ) oversampling noise-shaping modulator D out digital non-linearity correction f -1 ( ) decimation D dec look-up table nonlinearity is smooth can be very small (11 points excellent results) some calibration mechanism P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

75 Input swing reduction ring oscillator VCO non-linearity V in + k v, f c VCO f s reset counter ADC f DAC f + D out(z) 0-1 mash structure aux ADC and DAC uncritical sensitive to mismatch P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

76 VCO-ADC in sigma delta loop ring oscillator VCO non-linearity f s V in + - loop filter k v, f c VCO reset counter D out (z) DAC embed in Sigma Delta Loop Original work by Perrott s group input signal of VCO still large for e.g. 2nd order loop filter 3rd order noise shaping 2nd order suppression of VCO nonlinearity P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

77 Phase domain VCO-ADC VCO in feedback loop k v, f c k v, f c + VCO 1 V in k v, f c - VCO 2 V in + VCO out k v, f c PD - - VCO PD DAC f s register sampler D out(z) VCO performs integration pseudo differential Phase detector can be largely digital P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

78 Phase domain VCO-ADC VCO in feedback loop k v, f c V in + + VCO 1 k v, f c - VCO PD f s register sampler D out(z) DAC VCO performs integration pseudo differential Phase detector can be largely digital can be multi-phase P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

79 VCO-ADC in sigma delta loop ring oscillator VCO non-linearity k v, f c Vin + - loop filter + VCO 1 k v, f c - VCO 2 + PD - f s register sampler Dout(z) DAC for e.g. 2nd order loop filter 3rd order noise shaping input signal of VCO small 3rd order suppression of VCO nonlinearity P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80

80 Conclusion Review of 1 Sigma Delta Modulation 2 Continuous Time Sigma Delta Modulation 3 FoM Confusion 4 VCO ADC 5 Conclusion P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia / 80