y Reduction of Lekge Power Jun Cheol Prk, Vincent J. Mooney III, nd Philipp Pfeiffenerger Center for Reserch on Emedded Systems nd Technology School of Electricl nd Computer Engineering, Georgi Institute of Technology tlnt, G 30332-0250 US {jcprk,mooney}@ece.gtech.edu, gte125y@mil.gtech.edu strct. Lekge power consumption of current CMOS technology is lredy gret chllenge. ITRS projects tht lekge power consumption my come to dominte totl chip power consumption s the technology feture size shrinks. We propose novel lekge reduction technique, nmed sleepy stck, which cn e pplied to generl logic design. Our sleepy stck pproch retins exct logic stte mking it etter thn trditionl sleep nd zigzg techniques while sving lekge power consumption. Unlike the stck pproch (which sves stte), the sleepy stck pproch cn work well with dul-v th technologies, reducing lekge y severl orders of mgnitude over the stck pproch in single-v th technology. Unfortuntely, the sleepy stck pproch does hve re penlty (roughly 50 120%) s compred to stck technology; nonetheless, the sleepy stck pproch occupies niche where stte-sving nd extr low lekge is desired t (potentilly smll) cost in terms of incresed dely nd re. 1 Introduction The dvent of moile computing er hs ecome mjor motivtion for low power design ecuse the opertion time of moile device is hevily restricted y its ttery life. The growing complexity of moile devices, such s cell phone with digitl cmer or personl digitl ssistnt (PD) with glol positioning system (GPS), mkes the power prolem more chllenging. Dynmic power consumption ws previously mjor concern for chip designers since dynmic power ccounted for 99% or more of the totl chip power. However, s the feture size shrinks, sttic power, which consists minly of suthreshold nd gte-oxide lekge power, hs ecome gret chllenge for current nd future technologies. The min reson is tht lekge current increses exponentilly s the feture size shrinks. sed on the Interntionl Technology Rodmp for Semiconductors (ITRS), Kim et l. report tht suthreshold lekge power dissiption of chip will exceed dynmic power dissiption t the 65nm feture size [1][2]. Techniques for lekge power reduction cn e grouped in two ctegories: stte-preserving techniques where circuit stte (present vlue) is retined nd stte-destructive techniques where the current oolen output vlue of the circuit E. Mcii et l. (Eds.): PTMOS 2004, LNCS 3254, pp. 148 158, 2004. c Springer-Verlg erlin Heidelerg 2004
y Reduction of Lekge Power 149 might e lost [1]. stte-preserving technique hs n dvntge over sttedestructive technique in tht with stte-preserving technique the circuitry cn resume opertion t point much lter in time without hving to somehow regenerte stte. Our new design technique, which we cll the sleepy stck technique, retins dt during sleep mode while providing reduced lekge power consumption t cost of slightly incresed dely. Furthermore, the sleepy stck pproch cn e pplicle to single- nd dul-threshold voltge technologies. The sleepy stck pproch delivers new choice to designers to implement lowlekge-power circuits tht retins stte. The rest of the pper is orgnized s follows: Section 2 discusses sources of lekge power nd previous low-lekge pproches. Section 3 descries the proposed sleepy stck pproch with comprisons to previous pproches. Section 4 presents the simultion methodology, nd Section 5 explins the results. Section 6 concludes the pper. 2 Previous Work In tody s technology, the min contriuter to sttic power consumption of CMOS circuit is suthreshold lekge, i.e., source to drin current when gte voltge is smller thn the trnsistor threshold voltge. The suthreshold lekge current cn e expressed s follows: I su = K 1 We V th/nv θ (1 e V/N θ ) (1) where K 1 nd n re experimentl vlues, W is the width of the trnsistor, V th is the threshold voltge nd V θ is the therml voltge [1]. Since suthreshold current increses exponentilly s the threshold voltge decreses, deep sumicron technologies with scled down threshold voltges will severely suffer from suthreshold lekge power consumption. In ddition to suthreshold lekge, nother contriuter to lekge power is gte-oxide lekge power due to the tunneling current through the gte-oxide insultor. Since gte-oxide thickness will e reduced s the technology decreses, deep su-micron technology will lso suffer from gte-oxide lekge power. However, previously proposed work for lekge power reduction t the circuit level hs focused on suthreshold lekge power ecuse gte-oxide lekge is reltively smll compred to suthreshold lekge [1]. lthough gte-oxide lekge will lso increse exponentilly s technology feture size decreses, solution for gte-oxide lekge my lie in the development of high dielectric constnt (high-k) gte insultors. In this pper, we focus exclusively on reducing suthreshold lekge power. s introduced in Section 1, previously proposed work cn e divided into techniques tht either (i) preserve stte or (ii) destroy stte. Stte-destructive techniques (ii) cut off trnsistor (pull-up or pull-down or oth) networks from supply voltge or ground using sleep trnsistors [5]. These types of techniques re lso clled gted-v DD (note tht gted clock is generlly used for dynmic power reduction). Motoh et l. propose technique clled multi-thresholdvoltge CMOS (MTCMOS), which dds high V th sleep trnsistors etween pullup networks nd V DD nd etween pull-down networks nd ground while logic
150 J.C. Prk, V.J. Mooney, nd P. Pfeiffenerger circuits use low V th to mintin logic performnce [5]. The sleep trnsistor is turned off when the logic circuits re not in use. Powell et l. propose gted- V DD cche technique clled DRI cche, which dynmiclly chnges cche size with gted-v DD trnsistors of dul or single V th [4]. Since the gted-v DD technique cuts off logic locks from V DD nd Gnd, time nd energy for wking up re significnt. The zigzg technique proposes the reduction of wke-up overhed y choosing prticulr circuit stte (e.g., corresponding to reset ) nd then, for the exct circuit stte chosen, cutting off the pull-down network for ech gte whose output is high while conversely cutting off the pull-up network for ech gte whose output is low [9]. lthough the zigzg technique cn retin prticulr stte chosen prior to chip friction, ny other ritrry stte during regulr opertion is lost in power-down mode. nother technique to reduce lekge power is trnsistor stcking tht exploits the stck effect, i.e., it turns out tht two stcked nd turned off trnsistors reduce suthreshold lekge current sustntilly due minly to reverse is etween the gte nd source [6]. Nrendr et l. study the effectiveness of the stck effect including effects from incresing the chnnel length [7]. Since forced stcking of wht previously ws single trnsistor increses dely, Johnson et l. propose n lgorithm tht finds circuit input vectors tht mximize stcked trnsistors of existing complex logic [8]. Flutner et l. propose the drowsy cche technique tht switches supply voltge insted of gting V DD [10]. The effect of drowsy cches in terms of lekge power reduction is smller thn gted-v DD techniques, ut the drowsy cche technique cn retin the originl stte thus cn e used for designing memories. 3 y In this section, our new low-lekge-power design, nmed sleepy stck, is descried nd compred with well-known previous pproches, i.e., the sleep, zigzg nd stck techniques explined in Section 2. The se cse, shown in Fig. 1, consists of three stges ech with pull-up network nd pull-down network nd with the finl stge connected to lod cpcitnce. Fig. 2, 3 nd 4 show previous low-lekge pproches pplied to the se cse. The sleep pproch in Fig. 2 S S S S S S Fig. 1. se cse Fig. 2.
y Reduction of Lekge Power 151 S S S network Fig. 3. Zigzg Fig. 4. uses sleep trnsistors etween oth V DD nd the pull-up network s well s etween Gnd nd the pull-down network. Generlly, the width/length (W/L) rtio is sized sed on trde-off etween re, lekge reduction nd dely. During sleep mode, sleep trnsistors re turned off nd lekge current is suppressed. However, the dditionl sleep trnsistors increse re nd dely. Furthermore, the pull-up nd pull-down network will hve floting vlues nd lose stte during sleep mode. The zigzg pproch in Fig. 3 first nlyzes ech gte for prticulr input ssumed during sleep mode nd either ssigns sleep trnsistor to the pull-down network if the output is 1 or else ssigns sleep trnsistor to the pull-up network if the output is 0. In Fig. 3, we ssume tht, in the sleep mode, the input of the logic is 0 nd ech logic stge reverses its input signl, i.e., the output is 1 if the input is 0, nd the output is 0 is the input is 1. ccordingly, the pull-down network of the first stge is off, nd so sleep trnsistor is dded. Thus, the zigzg pproch uses fewer sleep trnsistors thn the originl sleep pproch. However, nlyzing logicl stte nd finding input vectors of complex logic locks re NP-hrd prolems which need to e solved in order to pply the zigzg pproch [8]. Fig. 4 shows the stck pproch, which forces stck effect y reking down n existing trnsistor into two hlf size trnsistors. The forced stck pproch cn chieve huge lekge power sving while retining the logic stte. However, the divided trnsistors increse dely significntly nd my restrict the usefulness of the forced stck pproch. The key ide of the sleepy stck technique is to comine the sleep trnsistor pproch during ctive mode with the stck pproch during sleep mode. The structure of the sleepy stck pproch is shown in Fig. 5. The sleepy stck technique divides existing trnsistors into two trnsistors ech typiclly with the sme width W 1 hlf the size of the originl single trnsistor s width W 2 (i.e., W 1 = W 2 /2). Then sleep trnsistors re dded in prllel to one of the trnsistors in ech set of two stcked trnsistors; see Fig. 6 for n exmple. The divided trnsistors reduce lekge power using the stck effect while retining stte. The dded sleep trnsistors operte similr to the sleep trnsistors used in the sleep technique in which sleep trnsistors re turned on during ctive mode nd turned off during sleep mode. Fig. 6 depicts the sleepy stck opertion
152 J.C. Prk, V.J. Mooney, nd P. Pfeiffenerger S network On S=0 Off S=1 S On S=1 Off S=0 Fig. 5. y stck Fig. 6. y stck ctive mode (left) nd sleep mode (right) using n inverter. During ctive mode, S=0 nd S =1 re sserted, nd thus ll sleep trnsistors re turned on. Due to the dded sleep trnsistor, the resistnce through the ctivted (i.e., on ) pth decreses, nd the propgtion dely decreses (compred to not dding sleep trnsistors while leving the rest of the circuitry the sme, i.e., with stcked trnsistors). During the sleep mode, S=1 nd S =0 re sserted, nd so oth of the sleep trnsistors re turned off. The stcked trnsistors in the sleepy stck pproch suppress lekge current. 4 Experimentl Methodology We compre the proposed sleepy stck pproch to se cse (sed on Fig. 1) nd three of the previous pproches explined erlier, nmely zigzg, sleep nd stck. Thus, we compre five design pproches in terms of power consumption (dynmic nd sttic), dely nd re. To show tht the sleepy stck pproch is pplicle to generl logic design, we choose three generic circuits: (i) chin of 3 inverters, (ii) 4-input multiplexer nd (iii) 4-it dder. The logic digrm of the 4-input multiplexer used for (ii) is shown in Fig. 7. One it of the 4-it dder used for (iii) is shown in Fig. 8 of which is sized s noted in the sme figure. The inverter chin uses three inverters ech with for PMOS nd for NMOS for the se cse. trnsistors in the sleep pproch (Fig. 2) nd the zigzg pproch (Fig. 3) re sized such tht ny sleep trnsistor etween V DD nd pull-up network tkes the size of the lrgest trnsistor in the pull-up network, nd ny sleep trnsistor etween Gnd nd pull-down network tkes the size of the lrgest trnsistor in the pull-down network. For exmple, sleep trnsistors used in the pull-up nd pull-down networks of the se cse inverter chin hve nd, respectively s shown in Fig. 2. Trnsistors in the stck pproch re sized to hlf of the size of the se cse trnsistors, e.g., trnsistors used in pull-up nd pull-down of the se cse inverter chin hve nd, respectively, s shown in Fig 4. Similrly, trnsistors, including sleep trnsistors, in the sleepy stck pproch re sized to hlf of the size of the se cse trnsistors s shown in Fig. 5. The
y Reduction of Lekge Power 153 I0 W/L=12 W/L=12 c W/L=12 W/L=9 W/L=9 W/L=12 I1 I2 c W/L=4.5 W/L=9 W/L=9 Crry W/L=4 W/L=12 W/L=12 c Sum c W/L=4.5 I3 c W/L=4.5 W/L=4.5 S1 S0 E Fig. 7. 4-input multiplexer Fig. 8. 1-it full dder lod cpcitnce is set to 3C inv (where C inv is the cpcitnce of n inverter with pull-up, pull-down ). To estimte re, dely nd power, we first design trget enchmrk circuits using Cdence Virtuoso, custom lyout tool [12], nd North Crolin Stte University Cdence design kit trgeting TSMC 0.18µ technology [13]. Then we extrct schemtics from lyout to otin trnsistor circuit netlists. we use HSPICE simultion to estimte dely nd power of the enchmrks, for which we use vnt! Stt-HSPICE [11]. Since we don t hve ccess to the lyout design proprietry elow 0.18µ technology, we use the erkeley Predictive Technology Model (PTM) prmeters to estimte dely nd power for technologies elow 0.18µ [14,15]. We choose four different technologies from PTM to oserve chnges of power nd dely s technology shrinks. The chosen technologies, i.e., 0.07µ, 0.10µ, 0.13µ nd 0.18µ, use supply voltges of 1.0V, 1.3V, 1.6V nd 1.8V, respectively. We ssume tht only single supply voltge is ville in ech technology. We do consider oth single- nd dul-v th technology for the zigzg, sleep nd sleepy stck pproches (note tht for the strightforwrd stck pproch, no trnsistors exist which could e mde high-v th without drmtic increse in dely). With dul-v th technology, the zigzg nd sleep pproches use high-v th sleep trnsistors. Similrly, in the sleepy stck pproch with dul-v th technology, high-v th trnsistors re used for sleep trnsistors nd trnsistors tht re prllel to the sleep trnsistors. We set ll high-v th trnsistors to hve 2.5 times higher V th thn the V th of norml trnsistor just like [5]. More detils out the experimentl methodology cn e found in technicl report [16]. 5 Experimentl Results We mesure worst cse propgtion dely nd power for the five design pproches, which re the se cse, zigzg, sleep, stck nd sleepy stck p-
154 J.C. Prk, V.J. Mooney, nd P. Pfeiffenerger 1.E-07 1.E-08 1.E-11 1.E-12 1.E-13 1.E-14 1.E-15 1.E-16 1.E-17 se cse 1.E-06 TSMC 0.18u erkeley 0.18u erkeley 0.13u erkeley 0.10u erkeley 0.07u 1.E-07 () Sttic power (W) () Dynmic power (W) 1.E-05 y * * y * se cse y (c) Propgtion dely (s) (d) re (µ 2 ) 100 * * y * 10 1.E-11 se cse y * * y * 1 se cse y * * y * Fig. 9. Results of chin of 3 inverters (*dul V th ) proches. Dynmic power is mesured with rndom input vector chnging every clock cycle, i.e., 4ns; sttic power is mesured using smpling of input vectors nd verged. The re of the enchmrks elow 0.18µ technology is estimted y scling re of enchmrk lyout using TSMC 0.18µ technology. We dd 10% of re overhed considering non-liner scling lyers, e.g., metl lyer. Fig. 9, 10 nd 11 show the experimentl results. Focusing on the single V th 0.07µ technology implementtion of ech enchmrk shown in Tle 1, we see tht our sleepy stck pproch results in lekge power roughly equivlent to the other three lekge-reduction pproches in the sme technology. Compred to the sleep nd zigzg pproches, which do not sve stte, the sleepy stck pproch results in up to 67% dely increse nd up to 69% re increse. Thus, we do not recommend the sleepy stck pproch with single-v th when sttepreservtion is not needed. Compred to the stck pproch, which sves stte, the sleepy stck pproch results in up to 120% re increse, ut the sleepy stck is up to 32% fster. Note tht if we increse stck widths (thus decresing trnsistor resistnces), we otin the results shown in Tle 2. In this cse, rther thn improve, the stck pproch shows incresed lekge with slight improvement in dely! s explined in Section 4, the zigzg, sleep nd sleepy stck pproches re lso implemented using dul-v th technology. The min dvntge of the sleepy stck pproch over the stck pproch is tht dul-v th technology cn e effec-
y Reduction of Lekge Power 155 1.E-06 1.E-07 1.E-08 () Sttic power (W) TSMC 0.18u erkeley 0.18u erkeley 0.13u 1.E-04 () Dynmic power (W) erkeley 0.10u erkeley 0.07u 1.E-05 1.E-11 1.E-12 1.E-13 1.E-14 1.E-06 se cse y * * y * se cse y (c) Propgtion dely (s) (d) re (µ 2 ) 1000 * * y * 100 1.E-11 10 se cse y * * y * se cse y * * y * Fig. 10. Results of chin of 4-input multiplexers (*dul V th ) 1.E-06 () Sttic power (W) TSMC 0.18u 1.E-03 () Dynmic power (W) 1.E-07 erkeley 0.18u 1.E-08 erkeley 0.13u erkeley 0.10u erkeley 0.07u 1.E-04 1.E-11 1.E-12 1.E-05 1.E-08 se cse y * * y * se cse y (c) Propgtion dely (s) (d) re (µ 2 ) 1000 * * y * 100 se cse y * * y * 10 se cse y * * y * Fig. 11. Results of chin of 4-it dders (*dul V th )
156 J.C. Prk, V.J. Mooney, nd P. Pfeiffenerger Tle 1. re, dely nd power estimtion (0.07µ) chin of 3 inverters Propgtion dely (s) Sttic Power (W) Dynmic Power (W) re (µ2) se cse 4.61E-11 1.24E-08 6.56E-07 3.92 1.28E-10 9.89E-10 4.08E-07 4.48 6.98E-11 2.40E-09 9.49E-07 8.00 5.99E-11 2.27E-09 1.05E-06 5.54 y 8.75E-11 1.77E-09 6.35E-07 6.78 (dul Vth) 1.14E-10 4.32E-13 8.58E-07 8.00 (dul Vth) 9.03E-11 3.84E-13 9.87E-07 5.54 y (dul Vth) 1.38E-10 9.88E-13 4.88E-07 6.78 4-input multiplexer Propgtion dely (s) Sttic Power (W) Dynmic Power (W) re (µ2) se cse 1.05E-10 1.72E-07 4.35E-06 50.17 3.39E-10 8.63E-09 3.43E-06 57.40 1.56E-10 2.24E-08 3.66E-06 74.11 2.58E-10 1.41E-08 3.64E-06 74.36 y 2.58E-10 1.51E-08 3.64E-06 125.33 (dul Vth) 2.35E-10 5.03E-12 3.73E-06 74.11 (dul Vth) 3.97E-10 7.54E-12 3.43E-06 74.36 y (dul Vth) 3.97E-10 8.19E-12 3.43E-06 125.33 4-it dder Propgtion dely (s) Sttic Power (W) Dynmic Power (W) re (µ2) se cse 2.91E-10 1.81E-07 1.52E-05 22.96 8.89E-10 9.25E-09 1.24E-05 30.94 4.11E-10 1.69E-08 1.54E-05 30.94 4.06E-10 1.20E-08 1.47E-05 27.62 y 6.79E-10 1.50E-08 1.31E-05 65.88 (dul Vth) 6.20E-10 3.31E-12 1.61E-05 30.94 (dul Vth) 6.15E-10 4.92E-12 1.47E-05 27.62 y (dul Vth) 1.03E-09 1.88E-11 1.22E-05 65.88 Tle 2. re, dely nd lekge power with vrious stck width ( chin of 3 inverters, 0.07µ) se cse (1X) (2X) (3X) (4X) y stck (single Vth) y stck (dul Vth) re (µ 2 ) 3.92 4.48 5.37 6.27 7.17 6.78 6.78 Dely (S) 4.61E-11 1.28E-10 1.14E-10 1.10E-10 1.07E-10 8.75E-11 1.38E-10 Lekge (W) 1.24E-08 9.89E-10 1.98E-09 2.97E-09 3.96E-09 1.77E-09 9.88E-13 tively pplied to the sleepy stck, resulting in three orders of mgnitude reduction in lekge when compred to the stck pproch s seen in Figs. 9(), 10() nd 11() with smll (7 17%) ssocited increses in dely. Not surprisingly, the sleepy stck pproch hs 50 120% lrger re s compred to the stck pproch. Therefore, our sleepy stck pproch with dul-v th cn e used where stte-preservtion nd ultr-low lekge power consumption re needed nd re judged to e worth the re overhed. One oservtion we notice from the results is tht none of the pproches shows the est result in ll criteri. Designers need to choose n pproprite technique for given technology nd prticulr chip. Our sleepy stck pproch provides new low-power VLSI design technique to chieve significnt lekge power reduction in deep su-micron while chieving either (i) sving of stte (unlike sleep nd zigzg) or (ii) lower dely thn strightforwrd stck pproch.
y Reduction of Lekge Power 157 6 Conclusions In nnometer scle CMOS technology, suthreshold lekge power consumption is gret chllenge. lthough previous pproches re effective in some wys, no perfect solution for reducing lekge power consumption is yet known. Therefore, designers choose techniques se upon technology nd design criteri. Our novel sleepy stck, which comines the sleep nd the stck pproches, is proposed s new choice for logic designers. Furthermore, the sleepy stck is pplicle to single nd multiple threshold voltges. In conclusion, the sleepy stck comine some of the dvntges of sleep trnsistors most notly the effective use of dul-v th technology with some of the dvntges of the stck pproch most notly the ility to sve stte. s such, the sleepy stck pproch represents new wepon in the VLSI designer s repertoire. References 1. N. S. Kim et l., Lekge Current: Moore s Lw Meets Sttic Power, IEEE Computer, Vol. 36, Issue 12, pp. 68-75, Decemer 2003. 2. Interntionl Technology Rodmp for Semiconductors y Semiconductor Industry ssocition, http://pulic.itrs.net, 2002. 3. L. T. Clrk et l., n Emedded 32- Microprocessor Core for Low-Power nd High-Performnce pplictions, IEEE Journl of Solid-Stte Circuits, Vol. 36, No. 11, pp. 1599-1608, Novemer 2001. 4. M. Powell, S.-H. Yng,. Flsfi, K. Roy nd T. N. Vijykumr, Gted-Vdd: Circuit Technique to Reduce Lekge in Deep-sumicron Cche Memories, Interntionl Symposium on Low Power Electronics nd Design, pp. 90-95, July 2000. 5. S. Mutoh et l., 1-V Power Supply High-speed Digitl Circuit Technology with Multithreshold-Voltge CMOS, IEEE Journl of Solis-Stte Circuits, Vol. 30, No. 8, pp. 847-854, ugust 1995. 6. Z. Chen, M, Johnson, L. Wei nd K. Roy, Estimtion of Stndy Lekge Power in CMOS Circuits Considering ccurte Modeling of Trnsistor s, Interntionl Symposium on Low Power Electronics nd Design, pp. 239-244, 1998. 7. S. Nrendr, S. orkr, V. De, D. ntonidis nd. Chndrksn, Scling of Effect nd its ppliction for Lekge Reduction, Interntionl Symposium on Low Power Electronics nd Design, pp. 195-200, ugust 2001. 8. M. Johnson, D. Somsekhr, L-Y. Chiou nd K. Roy, Lekge Control with Efficient Use of Trnsistor s in Single Threshold CMOS, IEEE Trnsctions on VLSI Systems, Vol. 10, No. 1, pp. 1-5, Ferury 2002. 9. K.-S. Min, H. Kwguchi nd T. Skuri, Zigzg Super Cut-off CMOS (ZSC- CMOS) lock ctivtion with Self-dptive Voltge Level Controller: n lterntive to Clock-gting Scheme in Lekge Dominnt Er, IEEE Interntionl Solid-Stte Circuits Conference, Vol. 1, pp. 400-401, Ferury 2003. 10. K. Flutner, N. S. Kim, S. Mrtin, D. luw nd T. Mudge, Drowsy Cches: Simple Techniques for Reducing Lekge Power, Interntionl Symposium on Computer rchitecture, pp. 148-157, My 2002. 11. vnt! Corportion, http://www.vnticorp.com. 12. Cdence Design Systems, http://www.cdence.com.
158 J.C. Prk, V.J. Mooney, nd P. Pfeiffenerger 13. NC Stte University Cdence Tool Informtion, http://www.cdence.ncsu.edu. 14. erkeley Predictive Technology Model (PTM), http://www-device.eecs.erkeley.edu/ ptm/. 15. Y. Co, T. Sto, D. Sylvester, M. Orshnsky, nd C. Hu, New prdigm of predictive MOSFET nd interconnect modeling for erly circuit design, Proc. of IEEE CICC, pp. 201-204, June 2000. 16. P. Pfeiffenerger, J. Prk nd V. Mooney, Some Lyouts Using the y pproch, Technicl Report GIT-CC-04-05, Georgi Institute of Technology, June 2004. http://www.cc.gtech.edu/tech reports/index.04.html