EUV. Scanner Optimization for DPT. Bob Socha. Immersion ASML. MC Escher. Slide 1

Transcription

1 Scanner Optimization for DPT Bob Socha ASML Double Patterning EUV Immersion MC Escher Slide 1

2 Outline SRAM gate DPT example Overlay, CDU, Resolution (Design) trade-off Spacer Challenges Conclusion / Slide 2

3 Enabling DPT DPT for the 22nm node (logic) and 32nm node (memory) is a necessary reality Overlay is critical DPT Vertical scaling (3D layout) Most cost effective DPT implementations will involve scanner optimization and design optimization Implementation of DPT for one layer (such as spacer at logic gate for CDU) has design effects of other layers (increased M1 2-D complexity) The customer that most effectively optimizes the design and scanner together will produce the most cost effective product Strong need developing for closer interaction between designers, fab, and scanner vendor. How much of this interaction knowledge can be done in the design library and in the place and route CAD tools. / Slide 3

4 Low k 1 : High Design to Wafer Integration Low k1 (<0.4) : Integration of design, mask and Lithography processes Design for Manufacturing DFM OPC & RET s: PSM, Scatterbars, CPL, DDL Verification Source- Mask optimization Application Specific tuning Application Specific Manufacturing Litho aware design constraints Design space Manufacturing space / Slide 4

5 Outline SRAM gate DPT example Overlay, CDU, Resolution (Design) trade-off Spacer Challenges Conclusion / Slide 5

6 Typical SRAM Gate Layer L+CDU SE w+cdu SE s+ov SE B+OV SE Pitch < 0.5λ/NA Unit Cell needed for Area Calculation A SE is a function of 3 variables The Area of the SRAM cell is the most widely used Metric to determine the shrink of the node As a result, the area must also be used to compare Litho-DPT to Spacer-DPT shrink capabilities. Comparison between Litho-DPT to Spacer- DPT based on 1-D geometries (1Dmetric) is not relevant R SE, OV SE and CD SE / Slide 6

7 Process Steps Required LELE Spacer / Slide 7

8 Double patterning require better and more lithography Litho exposure equipment parameter as percentage of CD Single exposure Litho double patterning Spacer double patterning CD 7% 3.5% 3% Overlay (depending on DFM) 20% 7% 7-20%* #mask steps # process steps relative to single exposure Application 2D, All 2D, All 1D, Mainly Memory * Depending on the amount of Design For Manufacturing effort / Slide 8

9 OVSE and CDUSE requirements for 35nm HP SRAM (shrink of the 50nm HP SE SRAM area by 50%) Litho-DPT Spacer-DPT Below 50% line is the area of interest OV SE must be less than 2.5nm for 50% shrink with Litho- DPT at CDU SE =3nm If current CDU SE =3nm and OV SE =5nm, a 56.2% shrink can be done with Litho-DPT If current CDU SE =3nm and OV SE =5nm, a 49.5% shrink can be done with Spacer-DPT / Slide 9

10 Outline SRAM gate DPT example Overlay, CDU, Resolution (Design) trade-off Spacer Challenges Conclusion / Slide 10

11 100 Cost of Ownership estimates for 32nm Challenges Litho Cost per Layer [$] Pattern split Process complexity CDU control Pattern split Process complexity Overlay & CDU Defect free mask / no pellicle Source power / resist sensitivity Further cost reduction opportunity? 0 193nm Spacer DPT 193nm Litho DPT EUV Fixed Operating Source Chemical CVD Etch Metrology Other Strip Reticle * Mask cost based on 5000 wafers / mask usage / Slide 11

12 Spacer process can be used for random structures Desired layout After spacer process applied / Slide 12

13 Spacer needs overlay friendly layout to enjoy overlay advantage from the self aligned process Areas surrounded by geometry formed by spacer are less sensitive to overlay errors. Areas not surrounded by geometry formed by spacer are more sensitive to overlay errors. Possible CD error or bridging can occur. Without design change, overlay is still critical for spacer when exposing a clear field mask! / Slide 13

14 Spacer with overlay friendly layout to enjoy overlay advantage from the self aligned process In areas not surrounded by geometry formed by spacer, the space width between patterns must increase. Design change to increase the space width between patterns may need tighter overlay for next layer. Design change to shift a pattern to increase space width may require verification of the electrical performance. With these design changes, the cell size may increase. / Slide 14

15 Spacer Challenges CoO is higher with Spacer DPT compared to LELE/LFLE DPT Spacer process integration/complexity increases cycle time Not all designs can benefit from Spacer DPT self-alignment Burdens the designer or makes design rules overly restrictive Industry not yet ready for Spacer friendly designs / Slide 15