Design and Implementation of Fine-grained Power Gating Control for Real Time OS

Transcription

1 OS (PG) OS PG PG OS PG PG PG OS 23% Design and Implementation of Fine-grained Power Gating Control for Real Time OS Shimada Yumi 1 Kobayashi Hiroaki 1 Takahashi Akihiro 1 Sakamoto Ryuiti 1 Sato Mikiko 1 Kondo Masaaki 2 Amano Hideharu 3 Nakamura Hiroshi 4 Namiki Mitaro 1 Abstract: This paper describes a PG(power gating) control mechanism for the processor equipped with a fine-grained PG technology for RTOS. An RTOS equipped with a PG control mechanism aims to reduce the power consumption while guaranteeing real-time performance. A PG control mechanism switches the operating mode by predicting the slack time that occurs when running periodic tasks. The real-time OS running on the PG processor has been implemented to perform the detailed design of the proposed control mechanism PG. In the evaluation, the average leakage power consumption was measured when operating a periodic task. As results of the evaluation, a reduction of up to 23% in average leakage power compared with dynamic PG were achieved 1. LSI LSI 1 Tokyo University of Agriculture and Technology 2 The University of Electro-Communication 3 Keio University 4 The University of Tokyo DVFS LSI Dual-Vth ( PG:Power Gating)[1] PG c 2012 Information Processing Society of Japan 1

2 PG PG Geyser [2] 5 Geyser MIPS R3000 PG Geyser 4 (Alu, Shift, Mult, Div) PG Geyser PG BEP(Break Even Point: )[3] BEP BEP DVFS [4][5] DVFS [6] 2 3 Geyser PG 4 Geyser RTOS 5 PG PG 8 2. BEP PG OS OS PG Geyser OS PG PG PG Geyser OS 4 3. Geyser Geyser PG Geyser PG 4 PG PG Geyser PG PG PGStatus PGStatus OS PG PG 1 PG Geyser BEP BEP. BEP PG 1 BEP Geyser RTOS PG Geyser OS Geyser RTOS Geyser OS OS Geyser c 2012 Information Processing Society of Japan 2

3 1 Fig. 1 Transition of power 1 BEP Table 1 BEP Alu Shift Mult Div Geyser RTOS PG Fig. 3 Geyser RTOS and PG control 3 Geyser RTOS PG OS PG 2 Geyser RTOS Fig. 2 Geyser RTOS configuration OS [7] Geyser RTOS Geyser OS MIPS R4000 [8] Geyser RTOS 2 Geyser RTOS Geyser OS 5. PG 5.1 Geyser PG 4 BEP PG PG OS 5.2 PG Geyser RTOS PG PG() BEP PG() BEP PG PG PGBEP PG PG 4 PG BEP 5 BEP PG PG PG PG c 2012 Information Processing Society of Japan 3

4 6 Fig. 6 Extend cyclen 4 PG Fig. 4 Overview of the control mechanism PG 5 Fig. 5 Relationship between slack time and extend time 1 PG BEP BEP BEP PG BEP PG BEP 6 BEP BEP BEP Ti Ri = {R i (BEP T i )} (1) BEP i=1 BEP PG, BEP PG 5.4 PG Geyser PG BEP PG BEP PG c 2012 Information Processing Society of Japan 4

5 Fig. 7 7 Algorithm to change the operating mode 8 Fig. 8 Processing during the deadline miss BEP PG PG BEP PG PG BEP PG BEP PG BEP 5.5 BEP BEP PG BEP PG PG 8 6. Geyser OS PG BEP PG 9 Geyser 2 Table 2 The number of code changes / 540 PG 115 OS Geyser OS PG Geyser OS PG PG BEP PG BEP PG PG BEP PG BEP 8 Geyser OS 2 PG 115 Geyser OS 655 c 2012 Information Processing Society of Japan 5

6 4 Table 4 Periodic task Fig. 9 Table 3 9 Implementation Overview 3 Development environment Geyser on FPGA(Xilinx ML501) DELL Optiplex 980 Windows 7 OS Professional(Cygwin-1.7.9) 7. gcc4.3.4 Tera Term4.69 Xilinx ISE Design Suite 4 PG FPGA Geyser Geyser on FPGA Geyser on FPGA Geyser on FPGA [9] P sleep T i P i R i T total P sleep = (ms) matrix 2717 dijkstra 1845 dhrystone 2752 whetstone 2658 i=1 (P i T i R i ) T total (2) P active [3] BEP P active = P i=bep (3) P P sleep P active / T sleep T active / T total P = P sleep T sleep + P active T active T total (4) ms 30s 4 4 Geyser BEP PG BEP PG BEP PG 48 2 BEP PG BEP PG BEP PG Div Mult Shift Alu BEP PG PG 25 matrix Alu 25 whetstone Alu BEP c 2012 Information Processing Society of Japan 6

7 5 Table 5 BEP PG Unit to apply the BEP-preserving PG whetstone dhryston matrixe dijkstra Div,Mult,Alu Div,Mult,Alu Div,Mult,Shift Div,Mult,Shift 10 Fig. 10 Average leakage power PG PG 25 matrix Shift 25 whetstone Mult Shift BEP PG BEP PG PG 30ms whetstone Alu 23.14% 65 whetstone Div Mult Shift BEP PG BEP PG BEP PG BEP PG Div Mult Alu Shift 3 BEP PG 5 Alu Shift BEP PG Alu Shift BEP PG Fig. 11 Average leakage power PG 4.01% BEP PG BEP PG BEP PG whetstone BEP PG shift shift Alu (0) (1) BEP PG shift PG Shift Alu 12 Alu 4 Alu PG BEP c 2012 Information Processing Society of Japan 7

8 12 Fig. 12 Active/sleep state in each operating mode PG Alu BEP PG PG Alu BEP PG OS Geyser Geyser RTOS Geyser on FPGA 4 BEP PG 23.14% BEP PG PG 8.2 PG BEP BEP JST CREST LSI [1] N. Seki, L. Zhao, J. Kei, D. Ikebuchi, Y. Kojima, Y. Hasegawa, H. Amano, T. Kashima, S. Takeda, T. Shirai, M. Nakata, K. Usami, T. Sunata, J. Kanai, M. Namiki, M. Kondo, and H. Nakamura, A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000, Proceeding of the 26th IEEE International Conference on Computer Design, pp , [2],,,,, LSI ARC-173, pp.79-84, Jun [3] MIPS R3000 ( ), vol.107, no.414, VLD , pp.43-48, Jan [4] Pillai, P. and Shin, K. G., Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems, 18th ACM Symposium on Operating Systems Principles, pp , [5] Kim, W., Kim, J. and Min, S. L. A Dynamic Voltage Scaling Algorithm for Dynamicb Priority Hard RealTime Systems Using Slack Time Analysis, in Proc. Design Automation and Test in Europe, pp , [6],,,,, (ETNET2006), Vol. 105, No. 670, pp.7-12, [7],,,,,,, OS, 2010-ARC-189 pp.1-8, Apr [8], pp.91-98, Feb [9], vol.107, no.414, VLD , pp.37-42, Jan [10] David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, and Mary Jane Irwin, Evaluation Run-Time Techniques for Leakage Power Reduction, ASPDAC 2002, pp , Aug (2002). [11] James T. Kao and Anantha P. Chandrakasan Dual- Threshold Voltage Techniques for Low-Power Digital Circuits, IEEE Journal of Solid-State Circuits, vol. 35, pp , Jul (2000). c 2012 Information Processing Society of Japan 8