Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations

Transcription

1 Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations Brent Bero and Jabulani Nyathi School of EECS Washington State University Pullman, WA (USA) Abstract- Interest in subthreshold design has increased due to the emergence of systems that require ultra-low power and the ever increasing leakage currents (now used to drive logic). Subthreshold sacrifices speed for power creating a clear divide between designing for high speed and ultra-low power. It might be beneficial to allow subthreshold circuits to operate in super-threshold, depending on processing needs. In this paper, the feasibility of optimizing device sizes for both subthreshold and above threshold operations is considered. In addition body biasing techniques that could facilitate bridging the speed gap are presented. Device sizing for circuits of the subthreshold region is examined with the view that these circuits could be optimized for subthreshold but also operate effectively in super-threshold. In an effort to attain optimal performance (speed-power), an operating region is identified in terms of the energy-delay product. To enhance the operating speed of both subthreshold and super-threshold circuits, a novel body biasing technique termed tunable body biasing (TBB), is introduced. This approach leads to increased operating frequencies particularly in subthreshold operation and shows no performance degradation at voltages above threshold, hence bridging of the speed gap. Post layout simulations of circuits ranging from simple to more complex ones enable for effective evaluation of optimal device sizing and identifying the optimal power-speed operational region. Simulations have been performed at a modest 180 nm technology node and circuits show optimal operating regions ranging from 0.5 to 1.1 V. Further more results indicate that the TBB approach for an inverter triples speed and has a 60 percent lower EDP while dissipating just 28 percent more energy than a traditionally biased approach (pmos bulk at and nmos bulk at Vss). I. INTRODUCTION Interest in subthreshold design has increased because of the emergence of systems that require ultra-low power. This approach sacrifices speed for power, utilizing leakage currents to drive logic gates [1]. Considerable work on limiting leakage currents has been done for super-threshold (above threshold) circuits [2], [3], [4] and there is a distinct separation between designing for ultra-low power and high speed. It is noted that embedded systems are the prime candidates for ultra-low power methods since they do not necessarily require fast operation. Examples include circuits for wearable devices, implantable medical technology, and sensor nodes. A majority of the work on subthreshold has focused only on the ultra-low power aspect of this region treating speed as a secondary metric. A number of body biasing techniques have been proposed for both the subthreshold and the superthreshold regions. The body biasing schemes include Dynamic Threshold Voltage MOSFET (DTMOS) [5], multithreshold CMOS (MTCMOS) [6], and swapped body biasing (SBB) [7] just to name a few. In the case of SBB technique the bulk of the nmos devices are tied to the power supply rail while those of the pmos devices are tied to ground, hence swapped biasing compared to the conventional configuration. Swapping the bulk terminals provides increased drive currents in the subthreshold operation, but degrades output node voltages when is greater than the threshold voltage. The DTMOS configuration on the other hand has the bulk terminals connected to the gate terminals of each device in a circuit. This approach is not scalable to the super-threshold region however and requires partitioned wells or specialized processes to realize. The MTCMOS technique is intended for super-threshold operation, mainly to limit leakage current. MTCMOS couples high and low threshold-voltage transistors to limit leakage current while the circuit is idle. Given the fact that most the configurations offer limited operation i.e. provide improved performance for a prescribed region, a body biasing technique that could offer improved performance in both subthreshold and above threshold regions is sought. The application space for systems using circuits that could offer ultra-low power, high-speed or an optimal speed-power trade-off is yet to be explored. Microprocessors, microcontrollers and a host of system on chip designs would benefit from such tunable digital design. Controlling the bulk terminals of CMOS devices offers improved performance and such circuits are explored in this paper with performance gains achieved under such configurations being reported. Controlling the devices' bulk terminals is done primarily to increase speed at subthreshold, but also to provide the capability to operate at full using the same circuits and maintaining the performance gains. To /06/$ IEEE. 221

2 span the subthreshold and super-threshold regions of operation a tunable body biasing (TBB) approach is proposed. The pmos bulks are driven by either Vss in subthreshold or - Vth,O in super-threshold, while nmos bulks are driven by in subthreshold or Vthno in superthreshold. Vth11o denotes the n-type device threshold voltage when the device's bulk and source are at ground. The TBB bulk control voltages are summarized in Table 1 and they allow for fluent operation at both subthreshold and superthreshold voltages. Fig. 1 depicts the different configurations described and also features the proposed tunable body biasing scheme. In this study the focus is on device sizing for the tunable body biased circuits that would enable for optimal operation in both subthreshold and super-threshold. TABLE I. VSS< <VthnO > Vtl.O TUNABLE BODY BIASING SCHEME'S BULK CONTROL VOLTAGES TBB MOS Bulk Control Signal (Vcontroi) pmos Device nmos Device Vss -Vth0 uut XL n oi-1 --ovpcontrol Vncontrol Vth.O (a) Traditional (b) SBB (c) TBB (d) DTMOS Figure 1. Body Biasing Techniques a) Traditional Body Biasing b) Swapped Body Biasing, c) Tunable Body Biasing and d) Dynamic Threshold CMOS Ideally the design is expected to offer ultra-low power when operating in subthreshold, high-speed when the power supply is higher than twice the threshold voltage as well as an optimal range with a good speed-power trade-off. All these operating regions are considered based on devices optimized for either subthreshold or super-threshold operation. Simulation results obtained from the inverter circuit are considered to be representative for many other logic circuits. Inverter simulations are relied upon to evaluate the tunable body biasing scheme under various input conditions. To analyze the behavior of a more complex system, an eight-bit linear feedback shift register (LFSR) is studied. Operating frequencies and energy dissipation in the various regions of operation using the different body biasing techniques are compared. In Section 2 a discussion of device sizing and operation in the subthreshold and super-threshold regions at discrete supply voltage levels is presented. Section 3 presents tunable bulk control circuits while Section 4 has plots that depict the optimal regions of operation for an inverter and the LFSR based on delay-energy trade-off and energy-delay product (EDP). Section 5 discusses the dynamic to static power ratio and some concluding remarks appear in Section 6. II. DEVICE SIZING FOR TUNABLE OPERATION A challenge in designing circuits to operate in both the super-threshold and subthreshold regions is determining optimal device sizing. The devices optimally sized to provide symmetric switching in subthreshold must operate in superthreshold with minimal deviation in providing the rise time that is equal to the fall time for a given load. There have been two major contributors towards the study of optimal device sizing for subthreshold designs. In [8] it is suggested that when sizing devices for minimum energy in the subthreshold region, minimum device sizes are best. The analysis of [8] focuses on a reduction of switched capacitance, leakage current, and minimum operating voltage. Using minimum device sizes reduces all of the above parameters and provides an ultra-low energy optimization for subthreshold. There are penalties in terms of decreased switching speed and increased energy-delay product. Few, if any, minimum-sized gates exhibit symmetric switching in the subthreshold region because of the differences in mobility of the pmos and nmos devices. Results reported in [8] show 50 percent energy savings. A process level approach presented in [9] recommends eliminating halo and retrograde doping while designing the device with high-to-low doping profiles to improve subthreshold operation. In doing so, the devices are no longer optimized for super-threshold operation because of increased drain-induced barrier lowering and body punchthrough. Neither [8] nor [9] consider operating logic gates optimized for subthreshold in the super-threshold region. This would be ideal as it would allow for the same integrated circuit to be used as a high-speed device or low power device when necessary. This study attempts to bridge the ultra-low power-speed gap, enabling designs intended for subthreshold operations to be usable at power supply voltages above threshold and at high speed. It is therefore of great interest to optimize devices such that they can operate in both regions. At the very least, it is prudent to be aware of the trade-offs made when sizing logic circuits in the subthreshold region then operating with the same circuits in the super-threshold region or vice versa. Inverters are used to examine optimal device sizing at either region of operation. The conventional (traditional) inverter whose devices are configured such that the pmos' bulk terminal is at while that of the nmos is at ground is used as reference. The inverter is designed for symmetric switching at 1.8 V, resulting in a Wp to W11 ratio of 1100 nm to 300 nm. The second inverter has the bulk terminals controlled to be at certain voltage levels depending on the desired region of operation (ultra-low power, optimal power-speed trade-off or high speed). This is considered to be a tunable approach since it offers such flexibility based on the power supply voltage and the bulk terminal control 222

3 voltage. Symmetric switching for the TBB design at a power supply voltage of mv is achieved with devices sized to give a Wp to W11 ratio of 1000 nm to 300 nm with a fan-outof four (FO4) load. Ideally this inverter's power supply voltage when changed to 1.8 V, and with appropriate bulk terminal voltages, should allow symmetric switching to be achieved. Any deviations from the expected values should be negligibly small. The optimized traditional inverter's average propagation delay (Tpavg) is 128 ps at 1.8 V. If the traditional inverter has a power supply voltage of mv, Tpavg is three orders of magnitude slower (123.7 ns) and shows very little deviation in terms of symmetric switching. The tunable inverter switches an order of magnitude faster than the traditional inverter in subthreshold and 20 percent faster in super-threshold. Tpavg for the tunable inverter is ps at super-threshold and 11.6 ns at subthreshold. Thus, the same device gives switching speed gains at both subthreshold and super-threshold. The voltage transfer characteristic (VTC) curves of the traditional inverter are presented to provide a sense of the deviation under different power supply voltages. From Fig. 2 the inverter threshold (Vthi,V) at each power supply voltage (1.8 V, 1.0 V, mv and mv) as well as the deviation from the expected value of /2 can be determined. Results in Table II indicate a 5.6 percent variation at subthreshold. Thus, operating at either region has minimal effect on the 50 percent switching point. Operating further into the subthreshold region shows a 13.4 percent variation at Vth,o/2. These results show promise in that the inverter can be sized approximately the same in both regions for symmetric switching and maintain an acceptable variation at the 50 percent switching point. Devices optimally sized for symmetric switching in the subthreshold region show similar deviations in super-threshold leading to a conclusion that circuits optimized for ultra-low power can be used to design for high-speed. Also circuits designed for high-speed can be used to design for ultra-low power. This substantiates the approach taken in [10] where standard cell libraries are used to design circuits for subthreshold operations with minimal modification. TABLE II. 1.8 V 1.0 V mv mv RECORD OF INVERTER THRESHOLD VOLTAGES AT DIFFERENT POWER SUPPLY VOLTAGES Ideal Inverter Threshold Simulated Threshold Inverter ~Threshold 900 mv 500 mv mv mv 900 mv 498 mv mv mv Percent Variation 0.O% 0.4% 5.6% 13.4% BULK TERMINAL CONTROL CIRCUITS The capability to control the nmos and pmos device bulk terminals offers some increase in drive current and simple circuits to enable controlling the bulk CMOS wells are presented. The bulk terminals must be controlled appropriately depending on whether the circuit is intended to operate in ultra-low power, high-speed or at an optimal point where the power-speed trade-off is achieved. Bulk control circuits are designed using pass transistor logic and relying on the properties of this logic style i.e. capability to pass "good/poor" Is and Os. To select the appropriate voltage, multiplexers are used and a select signal is introduced enabling a user to select the desired region of operation. Circuit schematics and simulation waveforms are presented in Fig. 3 and 4. This approach uses two transistors per MOS bulk control circuit. Note that bulk control circuits are biased using the traditional approach. The bulk control circuits are scalable from one technology node to another. The bulk voltage level required will be determined primarily by the power supply voltage level and the designated threshold voltage of the technology node. In both Fig. 3 and 4 the signals labeled SubVt and SubVt b are the control signals that enable for selection of the bulk voltage connection. III. Vdd Vdd SubVt b pmos Bulk - ~1r Subvt nmos Bulk u T SubVt Figure 3. MOS Bulk Control Circuit Diagrams Figure 2. Voltage Transfer Characteristics of an Inverter sized for symmetric switching at above threshold and showing capability to switch optimally at subthreshold. Figure 4. Bulk Control Waveform with varying for a pmos Device 223

4 Fig. 4 shows traces for a power supply voltage that is initially set to mv then changed to mv. Since these are subthreshold values the bulks of the pmos devices are shown to remain at 0 V. When the power supply voltage is changed to 1 V and then to 1.8 V the bulk control voltage changes from 0 V to a voltage level that will always be -V,h,O. The nmos devices' bulks are driven to in subthreshold and Vthno when operating in super-threshold. IV. OPTIMAL REGIONS OF OPERATION Section II presented optimal device sizing to enable circuits to operate at different power supply voltages. As a result propagation delay and inverter threshold voltages were the metrics to pursue. The TBB approach forward biases the bulk terminals of the devices thereby increasing leakage currents. This is the desired effect particularly when the circuit is performing useful computations. The increased switching speed gained might affect energy dissipation adversely especially when the devices are expected to be OFF. There is a significant static current component under these conditions. It becomes important to determine how much additional power and energy is dissipated to achieve these speed gains. Authors of [11] question the validity of energy as a quality metric because it can be made arbitrarily low by reducing the supply voltage. Thus, subthreshold operation appears very attractive in terms of energy. It is argued that EDP is a more relevant metric because it combines a measure of speed and energy. Energy as a metric is not discarded in this study and analysis of the optimal region is based on the energy-delay tradeoff as well as the overall EDP. Through a series of experiments, an optimal supply voltage region is determined. This provides the ability to identify an optimal region of operation which saves considerable power while allowing medium speed. To provide a meaningful basis for comparison, delay versus energy, and EDP are computed for both traditionally biased and TBB inverters as well as an eight-bit linear feedback shift register (LFSR). TBB circuits favor highly active circuits like clock networks and data path circuits where idle periods are minimal, thus maximizing the ratio of utilized leakage current to wasted leakage current. Fig. 5 and 6 plot the delay versus energy trade-off and EDP. Delay versus energy trade-off of the TBB inverter follows the trend of the traditional inverter and is thus omitted. The results indicate that an optimal region exists between 500 and 700 mv for both approaches. In this region, a tunable inverter can operate over three times faster than the traditional inverter with a 60 percent smaller EDP at the cost of 28 percent more energy. By examining delay, energy, and EDP metrics across the range of possible supply voltages as shown in Fig. 5 and 6, a designer can choose how much speed they are willing to sacrifice in order to save energy. Surprisingly, the body bias scheme has a negligible effect on the optimal region of operation. Thus, for brevity, charts of the delay versus energy trade-off and EDP of the traditionally biased LFSR are omitted T Figure Supply VoHa.ge V Figure 6. Energ,v versus Delay Trade-off for a Traditional Inverter Supply Voftage (V EDP for a Traditional and Tunable Inverter Having established appropriate device sizing for optimal operation in both subthreshold and super-threshold it is instructive that simulations of a more complex circuit; the linear feedback shift register be performed. The LFSR studied in this paper is an 8-bit Fibonacci implementation with four taps. Fig. 7 shows a general Fibonacci LFSR block diagram with feedback in parallel. The interested reader is referred to [12] for details on LFSR design. Fig. 8 shows the delay versus energy trade-off of a TBB LFSR. The results indicate an optimal region exists between 0.5 and 1.1 V. In this region (at 550 mv), a TBB LFSR can operate over 3.8 times faster than the traditional LFSR with a 33 percent smaller EDP at the cost of 2.5 times more energy. Figure TBB Energy-Delay Product Fibonacci LFSR Block Diagram 224

5 Figure Supply Voltage(V ) Energy versus Delay Trade-off for a TBB 8-bit LFSR approach gives comparable results to sizing at subthreshold with TBB. An optimal region of operation, as determined by the energy-delay product, for an inverter was determined to be between 500 and 700 mv while the optimal region for an eight-bit LFSR was determined to be between 0.5 and 1. 1 V. A significant drawback of the TBB approach is the increase in static power. Circuit diagrams and waveforms showing the feasibility of the proposed tunable circuits were presented. The bulk terminals of the MOS devices were driven to the desired voltage levels using these simple control circuits. Future work will involve determining the substrate size that a control circuit can effectively drive. An in-depth study of the static power dissipation at more current technology nodes is underway. V. DYNAMIC TO STATIC CURRENT/POWER RATIO The proposition of a tunable body biasing approach has its drawbacks, for an example the increased leakage currents. It might be acceptable to have increased leakages if the speed of circuits is increased dramatically to offset the energy dissipation in the OFF state. Emphasis has been placed on the overall energy dissipation of devices and the energydelay product. These metrics have shown that TBB can provide a low-energy approach. In spite of this, it is important to know what impact idle circuits have on static current and power dissipation. With idle circuits, the activity factor is low, presumably zero. To limit static power, most designers put devices into "sleep" mode during extended periods of inactivity. In order to determine how badly leakage currents are increased with the TBB approach an inverter at the subthreshold and super-threshold regions is examined and results compared to those of a traditionally biased inverter. Total current for both approaches (traditionally biased and tunable circuits) at super-threshold and subthreshold regions of operation have been calculated in order to assess the impact of the static current. The traditionally biased circuit at peak performance in subthreshold dissipates an average of 193 pw per cycle. The static power constitutes 0.l1% of the total power under these conditions. When operating at 1.8 V the total power is 39.6 piw per cycle and the static power is negligible. The TBB circuit at peak performance in subthreshold dissipates an average of 1.43 nw per cycle and the static power contributes 25.2 percent towards this value. When operating at 1.8 V the peak power per cycle for the TBB is 34.9 piw and percent of this is the static dissipation. From these values, it can be determined that static current contributes significantly in the TBB approach at subthreshold operation. VI. CONCLUSION This paper presents work on device optimization for operation in the subthreshold and super-threshold regions. Results show that sizing devices for symmetric switching at super-threshold operation with a traditional body biasing REFERENCES [1] Soeleman, H., Roy, K. and Paul, B. C. "Robust Subthreshold Logic for Ultra-Low Power Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No 1, February 2001, pp [2] J. Kao, S. Narenda, and A. Chandrakasan, "Subthreshold Leakage Modeling and Reduction Techniques," IEEEIACM International Conference on Computer Aided Design (ICCAD), November 10-14, 2002, pp [3] S. Yang, W. Wolf, N. Vijaykrishnan, T. Xie and W. Wang, "Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100 nm Circuits," 18th International Conference on VLSI Design, 2005, pp [4] C. Neau and K. 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