Adiabatic CMOS Circuit Design: Principles and Examples

Transcription

1 Aditi CMOS Ciruit Design: Priniples nd Exmples X.Wu,G.Hng,ndM.Pedrm Astrt: In view of hnging the type of energy onversion in CMOS iruits nd therey hieving ultr-low-power design, this pper investigtes diti CMOS iruits, whih use slow-rmping power lok. First, lgeri expressions for nd properties of power-loked signls re disussed. Then the design of diti gtes sed on AC power supply nd CMOS trnsmission gtes is nlyzed. On this sis, si rules for the design of diti iruits re proposed, nd design exmple of n diti full dder is demonstrted. PSPICE simultions using trpezoidl power-lok demonstrte tht the designed diti omintionl iruits hve orret logi funtion nd low-power hrteristis. I. Introdution Power dissiption in CMOS iruits is relted to the type of energy onversion tht they employ. In stti CMOS iruits, DC power supply is used, nd the signl vlue is relized y hrging (or dishrging) the node pitne. During this proess, the hrge is drwn from the power supply V dd, then trnsported to node pitne nd returned to the ground terminl, resulting in n irreversile energy onversion from eletri energy to het. As result, when node pitne is hrged (or dishrged), it leds to n energy dissiption of /2(CV dd 2 ), where C is the node pitne. Thus, reduing the energy dissiption hs een equted with reduing the swithed-pitne. Low power design tht trgets minimum swithed-pitne hs mde signifint progress in reent yers []. It hs een shown to e espeilly suitle to the design of low power sequentil iruits where signifint energy svings hve een oserved [2-4]. However, the energy svings otined re still limited. Reserhers nd designers, however, remin interested in developing logi elements tht operte sed on different X. Wu is with the Institute of Ciruits nd Systems, Ningo University, Ningo 352, People s Repuli of Chin. Hng is with the Deprtment of Informtion nd Eletroni Engineering, Zhejing University, Hngzhou 327, People s Repuli of Chin. M Pedrm is with the Deprtment of Eletril Engineering-Systems, University of Southern Cliforni, Los Angeles CA 989, USA.

2 type of energy onversion, i.e., one tht minimizes the onversion of eletri energy to het. An energy onversion is needed to represent hnge in signl vlue. If energy exists only in one form, i.e., eletri energy, then there is only one irreversile energy onversion from eletri energy to het. To rek this one-wy onversion, reserhers hve introdued nother energy form, i.e., mgneti field energy, into the digitl iruit. If the signl hnge is relted to the onversion of eletri energy to mgneti energy, the irreversile onversion from eletri energy to het used y dissiptive elements, i.e., resistors, is lrgely voided. For this reson, reserhers hve ttempted to mke rekthrough in low-power CMOS iruit design, from si iruit unit to miroproessor, y hnging the mode of energy onversion. Energy onversion from eletri field to mgneti field nd vie vers implies tht iruits should e supplied with AC power. In this se, signls in the iruits should lso e lternting quntities. The ltter hs een extensively used in dynmi CMOS logi, suh s loked CMOS logi, nd domino logi. However, those iruits still rely on DC power, nd the energy onversion remins onversion from eletri energy to het. Therefore, iruits supplied with AC power should e studied further [5]. Sine the AC power supply ontrols the working rhythm of the iruit nd ts s the lok, it hs een lled the power-lok [6]. Previous reserh shows tht if the dopted power lok is grdully hnging (rising or flling), less energy is dissipted when hrging nd dishrging the node pitne through the onduting MOS trnsistor. Therefore, the so-lled diti swithing opertion is relized, y whih new pproh to designing ultr-low-power CMOS iruits is proposed. Aditi omputtion hs een widely studied s low-power design tehnique. In the reent yers, severl diti or energy reovery logi rhitetures hve een proposed [6-8]. They hve hieved signifint power svings ompred to onventionl CMOS iruits. The outputs of these iruits re only vlid during prtiulr phse of the power lok yle. Hene, multiple-phse loking is required to drive hin of sded diti logi iruits. The need for multiple-phse power lok not only inreses the power dissiption of the loking network, ut it lso results in extr omplexity of oth the logi nd the required power 2

3 lok genertor. An diti logi iruit sed on trnsmission gtes ws proposed in Ref.[7] nd hieves fully diti omputing t the ost of dditionl omplexity in the lok wveforms for proper interfing etween stges nd dditionl omplexity in iruit struture when implementing omplex logi funtion. The proposed diti iruits in Refs.[8,9] use diodes or diode-like devies for pre-hrging (or pre-dishrging) tht uses unvoidle energy loss due to the voltge drop ross the diodes. Other designs proposed in Ref.[,] eliminte these pre-hrge diodes; however, they require four-phse loking. The numer of lok phses is redued in the designs proposed in Refs.[2-4]. They require only two-phse loking, ut extr uxiliry timing ontrol lok signls re needed [3] nd lok-powered lthes re inserted etween the logi gtes [4]. Although single-phse loking sheme is used in the designs proposed in Refs.[5,6], the extr demnds of two DC referene voltges nd omplementry ontrol lok signls need to e met. Finlly, it n e seen tht the ommon feture of the previously proposed iruits is tht the input signls nd the output signls in iruit re not in the sme lok-phse [7], whih results in the omintionl iruits hving the hrteristis of the sequentil iruit. Furthermore, the non-diti energy dissiption resulting from the loss of the threshold voltge of the MOS trnsistor in the iruits proposed in Refs.[8-,3-6] still exists. Referene [8] proposes tht the loss of threshold voltge n e voided y using ootstrpped MOS swith. The methodology for designing diti iruits in this pper hs elements tht re different from the previous studies. First, the lgeri expressions nd the orresponding properties of power-loked signls in diti iruits re studies tht serve s the mthemtil sis for designing diti iruits. Then some diti gtes with physil restortion funtion re designed y onverting the demnd of level-restortion in onventionl CMOS gtes into the demnd of pulse-restortion in diti CMOS gtes. All of the diti gtes proposed in this pper do not hve ross-oupled struture nd the sequentil hrteristi, tht is, the output nd the input signls will pper in the sme lok phse. Finlly, the design rules of diti omintionl iruits re summed up, nd the design proedures re demonstrted y tking the diti full dder s n exmple. PSPICE 3

4 simultions dopting trpezoidl power-lok prove tht ll the diti iruits proposed in this pper hve orret logi funtion nd low-power hrteristis. II. Algeri expressions for loked signls For the ske of simpliity, it is ssumed tht the lok of the CMOS iruit is symmetri squre-wve. When =, the loked signl displys its true logi vlue; when =, the loked signl is fored to its se vlue, or. For the pre-hrge iruits, the se vlue is, wheres for the pre-dishrge iruits, the se vlue is. Therefore, in every lok yle, the loked signl is divided into two stges: set se (B) when =ndevlute (E) when =. Figure shows pir of omplementry signls x / x nd the orresponding loked signls. The vlues of x / x in Fig. re ()/(); they ould e regrded s the synhronous outputs of flling-edge triggered-flip-flop. x / x re, however, not loked signls. In Fig.,,, x +,nd x + re the four loked signls derived from x / x. Notie tht the supersript i in the expression of i x, i {, + }, represents the logi reltion etween the originl signls x / x nd the loks /.Thtis, is, x + is x +, nd so on. Oviously, the funtion of ( )or( + ) is to set the loked signl during the B stge to se or se, respetively. x BE BE BE B E B E B E x x + x + Fig. Four loked signls derived from signl x The following inverting reltionships etween these loked signls n e oserved (f. Fig.): 4

5 (i) Logil inverse (with the sme se), suh s nd ; x + nd x +. (ii) Bse inverse (with the sme logi vlue), suh s nd x + ; nd x +. (iii) Complete inverse, suh s nd x + ; nd x +. Figure lso shows tht: x x + =,nd x x + =. () In line with the ove-mentioned exponentil expressions, the power supply V dd (), the ground (), nd the lok ( / ) stisfy the following loked expressions: + =, =. (2) =, + =. (3) If the exponentil opertion is regrded s Boolen opertion, then Eq.(2) nd Eq.(3) n e esily proved. Furthermore, the following expressions n lso e proven: ( y) ( y) ( x + y) ( x + y) + + = x = x = x = x + y + y + y, + + y., +. (4) (5) The physil mening of the ove Eq.() - Eq.(5) n e explined s follows: (i) Eq.() represents De Morgn s Lw. It shows tht the inverter funtion pplied to loked signls produes the omplete inverse of the originl loked signls (i.e., oth the logi vlue nd the se re inverted). (ii) Eq.(2) shows tht V dd () nd ground () n ontinully work in the loked iruits of se nd se, respetively. (iii) Eq.(3) indites tht n ssume the role of the power supply in the loked iruit of se, wheres n ssume the role of the ground in the loked iruit of se. (iv) Eq.(4) nd Eq.(5) suggest tht the loked signls tht prtiipte in the AND/OR opertions should hve the sme se. The result is equl to the AND/OR opertion of the originl signls nd is loked y the sme se. It 5

6 should e pointed out tht result of the NAND nd NOR opertions inverts the se due to Eq.(). III. Aditi CMOS gtes Considering tht the si iruits in diti CMOS iruits re the gtes, the struture of the diti gtes nd their working priniples re investigted first [9]. Similr to the trditionl CMOS gtes, the power-loked CMOS gtes should lso e of physil-restortion. In trditionl CMOS gtes, the outputs re lwys lmped to either the power supply y ondutive pmos trnsistor for the high-level output or the ground y ondutive nmos trnsistor for the low-level output, wherey the level-restortion is relized. Similrly, the outputs of the diti CMOS gtes should lso e lmped to the power lok y ondutive MOS swith to otin pulse-restored outputs. Beuse of the lternting feture of the power lok, the MOS swith used should e omplementry CMOS trnsmission gte. From the reltionships mong the loked signls s shown in Fig., it is seen tht pir of omplete inverse loked signls, nd x +, n e used to ontrol the pmos nd nmos trnsistors of the trnsmission gte, respetively, nd then the other pir of omplete inverse loked signls, nd x +, will e generted when nd re trnsmitted. Similrly, the ltter pir of loked signls n e used to ontrol the trnsmission of nd to reprodue the originl pir of loked signls. Bsed on this nlysis, the iruit shown in Fig. 2() is derived. The reltionships etween the input nd output in the iruit n e summed up s follows: (i) The pir of loked signls tht re used to ontrol ny trnsmission gte should e the omplete inverse of one nother. Furthermore, the se- nd the se- signls ontrol the pmos nd the nmos trnsistors, respetively. (ii) The output generted from is se- signl nd the logi inverse of the se- input signl ting on the pmos trnsistor. On the other hnd, the output otined from is se- signl nd the logi inverse of the se- input signl ting on the nmos trnsistor. (iii) Given ny four unrestored loked signls, their four restored loked signls n e otined y using two trnsmission gtes to trnsmit the power loks nd. 6

7 x + x + x + 6 Energy dissiption pj stti CMOS iruit diti CMOS iruit Time ns Fig. 2 Aditi CMOS inverter Aditi CMOS inverters PSPICE simultion result using trpezoidl power-lok Energydissiption urve By using trpezoidl power-lok nd the PSPICE progrm, the iruit shown in Fig. 2() is simulted with 2µ CMOS tehnology. The result is given in Fig. 2(), where it is found tht the output signls do not mintin flt-high top or flt-low ottom when the trnsmission gte shuts down. Tking x + s n exmple for explining, 7

8 does not immeditely jump to the high-level when x + is dropping. The nmos trnsistor in the trnsmission gte is still turned on t tht moment, so the output trks nd rises until the nmos trnsistor shuts down ompletely. However, the simultion hs verified tht these un-flt outputs do not ffet the next stge. Figure 2() shows the energy dissiption urve of one-stge iruit with the use of the trpezoidl power-lok with loked input sequene pir () nd (). The delining prt of this urve shows the effet of energy reovery. For ontrst, the energy dissiption urve of the ommon two-stge inverter using DC power supply with the sme onditions is lso drwn. It is shown tht the former iruit hs out n 86% energy svings in omprison with the ltter. The power sving is remrkle. Bsed on the diti CMOS inverter shown in Fig.2(), the diti NOR gte nd NAND gte n e designed further y onneting CMOS trnsmission gtes in series nd prllel s ws done for the onventionl CMOS NOR gte nd NAND gte. Tke the diti NOR gte shown in Fig.3() nd () s n exmple. Their logi funtions n e explined s follows. In the se-setting period, =, ll pths in Fig.3() nd () re ondutive, nd two outputs re set to nd y trnsmitting =nd =, respetively. Now we think out the evlution period: when =nd =. In Fig.3() sine soure (= ) is trnsmitted through pmos trnsistors in series, whih is like the pmos prt in onventionl CMOS NOR gte, the output will e x + y.if we onsider tht the output is se- loked signl, the output should e rewritten s x + y. On the other hnd, in Fig.3() the soure (= ) is trnsmitted through nmos trnsistors in series, whih is like the nmos prt in onventionl CMOS NAND gte. Thus the output will e y = x + y. Considering tht the output is se- loked signl the output should e rewritten s + ( x + y). Aording to De Morgn s Lw the signl n lso e expressed s x + y, whih is the omplement of the output in Fig.3(). Similrly, disussion n e rried out with the diti NAND gte shown in Fig.3() nd (d). 8

9 y x + y y y y + y y y y d y x + y + y Fig. 3 Aditi CMOS gtes d Aditi CMOS NOR gte with se- output Aditi CMOS OR gte with se- output Aditi CMOS NAND gte with se- output Aditi CMOS AND gte with se- output IV. Aditi CMOS Comintionl Ciruits The ove disussion my e expnded to ny diti CMOS trnsistor network for relizing more omplited logi funtion. As n exmple, n diti CMOS trnsistor network used to relize f = ( y + z) is given in Fig.4(). Its output n lso e expressed s x y z +. Its omplementry iruit n e esily derived y simply repling soure with soure. We hve verified the diti CMOS iruits y using trpezoidl power-lok. The PSPICE simultion results for inputs x (), y (), nd z ()re shown in Fig.4(). The output f hs the orret response: (). Bsed on the ove disussions of the si diti gtes in Fig.3 nd the diti omintionl iruit in Fig.4, the rules for designing generl diti CMOS omintionl iruit omposed of CMOS trnsmission 9

10 gte n e summrized s follows: (i) First, re-express logi funtion to e relized in its omplementry form y using De Morgn s Lw. (ii) Gte terminls of the pmos trnsistor nd nmos trnsistors re onneted to two omplete-inverse loked input signls ( se- signl is onneted to the pmos trnsistor wheres se- signl is onneted to the nmos trnsistor). y z ( y + z) y z Fig. 4 Aditi CMOS network Aditi CMOS iruit for relizing f = ( y + z) PSPICE simultion result using trpezoidl power-lok (iii) For the iruits with se- output signls (i.e., trnsmitting power lok ), the OR-opertion is relized y onneting pmos trnsistors in series, nd the AND-opertion is relized y onneting pmos trnsistors in prllel. The output signl is the omplement of the logi opertion of ll se- input signls tht t on the pmos trnsistors. (iv) For the iruits with se-output signls (i.e., trnsmitting power lok ), the AND-opertion is relized

11 y onneting nmos trnsistors in series, nd the OR-opertion is relized y onneting nmos trnsistors in prllel. The output signl is the omplement of the logi opertion of ll se- input signls t on the nmos trnsistors. (v) Finlly, find the trnsmission swithes tht n e shred, in order to simplify the iruit struture. As n exmple, we will design n diti full dder y using the ove design rules s follows. Aording to the truth tle of full dder, the expressions of S nd C + n e derived: S = ABC + ABC + ABC + ABC = A( BC + BC ) + A( BC + BC) = [ A + ( B + C ) ( B + C)] [ A + ( B + C) ( B + C )] 6 C = AB + AC + BC = A( B + C) + BC = ( A + B C ) ( B + C ) + 7 Bsed on the ove two equtions nd design rules, we n design omplete diti full dder ssemled y CMOS trnsmission gtes. However, we only disuss the prt design for giving se- output signls s n exmple. The iruit is shown in Fig.5(), where A, B, C nd A +, B +, C + represent se- nd se- input signls, respetively, S is the se- sum output signl (notie tht the orresponding trnsmission gtes ontrolled y signls A nd B re shred), nd C + is the se- rry-out signl (the orresponding trnsmission gte ontrolled y signl A is lso shred). By using trpezoidl power lok (frequeny is 25MHz, pek-to-pek supply is 3V) nd with Gry-oded input strem, we hve simulted the iruit shown in Fig. 5() with the PSPICE progrm. The simultion result given in Fig.5() proves tht the designed iruit hs the orret logi funtion. The energy dissiption urve is given in Fig.5(). For ontrst, the energy dissiption urve of the stti CMOS full dder [2] relized with trnsmission gtes is lso given in Fig. 5() under the sme simultion onditions. The urve shows tht the energy dissiption of the diti full dder is less thn pj within 7ns, wheres the energy dissiption of stti full dder exeeds pj within 7ns. Oviously, the power sving of the diti full dder is onsiderle. Similrly, the prt design for giving se- output signls n lso e derived.

12 A + B + C + A + B + A A + B B + B B + C C + S A B + B C + C C + C + A B B + C B C B A + B + C + A B C S C Time / ns 2 Energy Dissiption / pj 8 4 Stti full dder Aditi full dder Time / ns Fig. 5 Aditi CMOS full dder Aditi CMOS full dder with se- output signl PSPICE simultion result using trpezoidl power lok Energy onsumption urve V. Conlusions Aditi CMOS iruits, whih dopt grdully rising nd flling power-lok, n result in onsiderle energy sving. However, the opertionl onstrint tht the output signl should trk the power-lok s 2

13 slow-rmping ehvior to omplish the diti hrging nd dishrging proesses retes mjor diffiulty in the iruit design. In the previous studies of diti iruits, reserhers either dopt retrtile sde power loks or use multiple phse power loks with memory shemes in the design [2,22]. Oviously, their ppliility will e limited. The reserh eing performed on the lgeri expression of loked signls nd the design of si diti gtes with pulse restortion funtion re two key reserhes. Therefore, this pper first presents systemti study of loked signls y using pproprite lgeri expressions nd fully exploits the four types of loked signl. Furthermore, the design of n diti CMOS gte sed on AC power supply nd CMOS trnsmission gtes is nlyzed. On the ove sis, the generl rules for designing diti CMOS omintionl iruits re further summrized. Aording to the proposed design rules, the design of n diti CMOS full dder omposed of CMOS trnsmission gtes is demonstrted. The PSPICE simultions using trpezoidl power lok prove tht the designed iruits hve the orret logi funtion nd onsiderle energy sving. The design priniple n lso e used for designing more omplited diti CMOS iruits. To design n diti digitl system, merely reserhing on diti gtes nd diti omintionl iruits is insuffiient. Following the reserh in this pper, the design of diti flip-flop nd the diti sequentil iruits hs een investigted. Corresponding reserh results will e reported in nother pper. VI. Aknowledgments This work is supported in prt y the NNSF of Chin (Grnt No ) nd the NSF of USA (Grnt No ). VII. Referenes PEDRAM, M.: Power minimiztion in IC design: Priniples nd pplitions, ACM Trnstions on Design Automtion, 996,, (), pp WU, Q., PEDRAM, M., nd WU, X.: Clok-gting nd its pplition to low power design of sequentil iruits, IEEE Trns. on Ciruits nd Systems I: Fundmentl Theory nd Applitions, 2, 47, (3),pp WU, X., nd PEDRAM, M.: Low-power design on sequentil iruits using T flip-flops, Int. J. Eletronis, 2, 88, (6), 3

14 pp WU, X., PEDRAM, M., nd WANG, L.: Multi-ode stte ssignment for low power iruit design, IEE Pro.- Ciruits Devies Syst., 2, 47, (5), pp LAU, K., T., nd LIU, F.: Four-phse improved diti pseudo-domino logi, Eletronis Letters 998, 34, (4), pp DENKER, J., S.: A review of diti omputing. Proeedings of the Symposium on Low Power Eletronis, Sn Diego, Ot. 994, pp ATHAS, W., C., SVENSSON, L., J., KOLLER, J., G., TZARTZANIS, N., nd CHOU, E.: Low-power digitl systems sed on diti-swithing priniples, IEEE Trns. on VLSI Systems, 994, 2, (4), pp DENKER, J., S., AVERY, S., C., DICKINSON, A., G., KRAMER, A., nd WIK, T., R.: Aditi omputing with the 2N-2N2D Logi fmily. Proeedings of the Workshop on Low Power Design, Np Vlley, Apr. 994, pp DICKINSON, A., G., nd DENKER, J., S.: Aditi dynmi logi, IEEE Journl of Solid-Stte Ciruits, 995, 3, (3), pp KAMER, A., DENKER, J., S., FLOWER, B., nd MORONEY, J.: 2ND order diti omputtion with 2N-2P nd 2N-2N2P logi iruits. Proeedings of the Interntionl Symposium on Low Power design, Dn Point, Apr. 995, pp MOON, Y., nd JEONG, D., K.: An effiient hrge reovery logi iruit, IEEE Journl of Solid-Stte Ciruits, 996, SC-3, (4), pp OKLOBDZIJA, V., C., MAKSIMOVIC, D., nd LIN, F.: Pss-trnsistor diti logi using single-lok supply, IEEE Trnstions on Ciruits nd Systems-II: Anlog nd Digitl Signl Proessing, 997, 44, (), pp LIU, F., LAU, K., T., SIEK, L., nd CHAN, P., K.: A low-power ompt swithed output diti logi (CSOAL) fmily, Int. J. Eletronis, 999, 86, (3), pp LO, C., -K., nd CHAN, P., C., H.: An diti differentil logi for low-power digitl systems, IEEE Trnstions on Ciruits nd Systems-II: Anlog nd Digitl Signl Proessing, 999, 46, (9), pp KIM, S., nd PAPAEFTHYMIOU, M., C.: True single-phse-reovering logi for low-power, high-speed VLSI. Proeedings of the Interntionl Symposium on Low-Power Eletronis nd Design, Monterey, Aug. 998, pp MAKSIMOVIC, D., OKLOBDZIJA, V., G., NIKOLIC, B., nd CURRENT, K., W.: Cloked CMOS diti logi with integrted single-phse power-lok supply, IEEE Trnstions on VLSI Systems, 2, 8, (4), pp PEDRAM, M., nd WU, X.: Anlysis of loked power CMOS gtes with pplition to the design of energy-reovery 4

15 iruits. Proeedings of ASP-DAC, Pifio Yokohm, Jn. 2, pp LIM, J., KIM, D., -G., nd CHAE, S., -I.: Redution in energy onsumption y ootstrpped nmos swithes in reversile diti CMOS iruits, IEE Proeeding-Ciruits, Devies nd Systems, 999, 46, (6), pp WU, X., nd PEDRAM, M.: Low power CMOS iruits with loked power. Proeedings of IEEE Asi Pifi Conferene on Ciruits nd Systems, Tinjin, De. 2, pp ZHANG, N., nd WU, H.: A new design of the CMOS full dder, IEEE J. of Solid-Stte Ciruits, 992, 27, (5), pp WU, X., nd HANG, G.: Priniple of diti omputing nd CMOS iruits with energy reovery, Chinese J. of Computers, 2, 23, (7), pp WU, X., nd HANG, G.: Energy reovery iruits with ross-oupled struture, Journl of Ciruits nd Systems, 2, 5, (2), pp.-8. 5

16 Figures x BE BE BE B E B E B E x x + x + Fig. Four loked signls derived from signl x 6

17 x + x + x + 6 Energy dissiption pj stti CMOS iruit diti CMOS iruit Time ns Fig. 2 Aditi CMOS inverter Aditi CMOS inverters PSPICE simultion result using trpezoidl power-lok Energydissiption urve 7

18 y x + y y y y + y y y y d y x + y + y Fig. 3 Aditi CMOS gtes d Aditi CMOS NOR gte with se- output Aditi CMOS OR gte with se- output Aditi CMOS NAND gte with se- output Aditi CMOS AND gte with se- output 8

19 y z ( y + z) y z Fig. 4 Aditi CMOS network Aditi CMOS iruit for relizing f = ( y + z) PSPICE simultion result using trpezoidl power-lok 9

20 A + B + C + A + B + A A + B B + B B + C C + S A B + B C + C C + C + A B B + C B C B A + B + C + A B C S C Time / ns 2 Energy Dissiption / pj 8 4 Stti full dder Aditi full dder Time / ns Fig. 5 Aditi CMOS full dder Aditi CMOS full dder with se- output signl, PSPICE simultion result using trpezoidl power lok, Energy onsumption urve 2