Interconnect Manufacturing Challenges for the Most Advanced Technology Nodes

Transcription

1 Interconnect Manufacturing Challenges for the Most Advanced Technology Nodes Andrzej J. Strojwas Chief Technologist, PDF Solutions, Inc., San Jose, CA Keithley Professor of ECE, Carnegie Mellon University, Pittsburgh, PA, USA First IEEE International High Speed Interconnects Symposium Dallas, TX, April 30 th 2013

2 Agenda BEOL Evolution for Advanced Nodes BEOL Manufacturing Challenges BEOL Failure Modes and Characterization Needs BEOL Reliability Characterization 3D Integration Challenges and Roadmap Page 2

3 20/14nm Node: Increased Complexity of Design Rules Increased number of masks and patterning steps Complex integration requiring more masks Dual patterning steps with cut-masks (gate, AA, Fins) Dual coloring decomposition of patterns (Contacts, Vias, Metal lines) New integration requires validation of Process Assumptions 3D effects due to RMG and R-S/D Narrow process window due to multi-patterning scheme Complex OPC, RET, Dummy Fill and Mask Data Prep Special constructs, especially in MOL to enable efficient Std Cell design and expected area scaling Page 3

4 New Integration elements Migration from 32/28 to 20nm process 32/28nm Bulk 20nm Bulk M1 M1 M1 M1 M1 V0 V0 V0 CA CA CB TS TS TS esige esi Feature 32/28nm 20nm Isolation STI STI Gate Gate First, Poly-Si, with HK, Dual MG (or with Poly/SiON in 28 LP) Gate Last, HK last with Dual MG + Al Fill Dummy Poly with Replacement Metal Gate (+2 CMP) S/D Planar junctions, esige for Strain Raised S/D for both N (esi) and P (esige) Silicide Planar salicide - NiSi Salicide only inside the LI Trench - NiSi Page 4 Contacts BEOL Single Patterned CA for AA and Gate connecting to M1 Single patterning Vias and M1/Mx with Metal HM Complex Contact stack Trench Silicide (2mask W TS) + Contacts (2mask W CA+CB) + V0 (2mask Cu) Dual patterning SAV Vias and Dual Patterning LELE Metal lines

5 BEOL Evolution Feature 45/40 32/28 20/14 Metal Patterning Single patterning Single Patterning (28 - Metal HM) Dual Patterning LELE with Metal HM Via0 No No SAV - Merged Via, or Dual Patterning V1/Vx Single patterning Single Patterning Single/Dual Patterning Dielectric Low-k Ultra Low-k Ultra Low-k Barrier metal PVD Ta/TaN PVD Ta/TaN CVD Ta/TaN Cu Fill ECD Cu ECD doped Cu ECD doped Cu Dual patterning of Metal lines requires dual coloring and decomposition - Coloring conflicts - Stitching Self-Aligned Via requires very good selectivity to Metal HM - Via sizing (retargeting) - Enhanced Via chamfering Metal LELE Merged Via Page 5

6 Dual Patterning Dual patterning is used for multiple reasons, either to enhance Line-End Patterning, Contact/Via hole process Window, or to decrease pitch below resolution limits Page 6

7 Dual Patterning Dual patterning is used for multiple reasons, either to enhance Line-End Patterning, Contact/Via hole process Window, or to decrease pitch below resolution limits Page 7

8 Summary - Increasing Process Integration and Material Complexity Feature 28 nm 20 nm 14 nm New Challenges MOL stack CA/CB-M1 TS-CA/CB-V0- M1 Double TS patterning Double CA/CB V0 No V0 Single/Dual patterning Merged Self- Aligned-Via M1, Mx Single patterning DDL, 80nm LELE, 64nm TS-CA/CB-V0- M1 Double TS patterning Double CA/CB with SAC Dual patterning Self-Aligned Via LELE 64nm Very Complex MOL Misalignment process window Via Patterning and Etch Patterning and defectivity Page 8

9 Agenda BEOL Evolution for Advanced Nodes BEOL Manufacturing Challenges BEOL Failure Modes and Characterization Needs BEOL Reliability Characterization 3D Integration Challenges and Roadmap Page 9

10 20nm Fail Modes Test Structure Coverage Requirements Page 10 Module 20 nm Fail Mode Test structures for 20 nm MOL PC-TS and TS/CA-PC shorts Passive Combs and Dual Chains TS-Rx, CA-TS open TS/CA induced Junct. Leakage Open CB-PC Shorts TS-CA-CB Keyhole W tunnels TS-CA-CB W under/over CMP Contact Chains Leakage Arrays Contact Chains Passive Combs and Dual Chains CCKH Combs Passive Combs and Dual Chains BEOL Self Aligned Via (SAV) Opens Via Chains SRAM Self Aligned Via (SAV) Shorts Metal Shorts/Opens (Dual Color, or SameColor) Shorts and Opens in SRAM cell environment Via Combs, Diual Via Chains Snake Combs Combs, snakes, and chains implemented in SRAM "fabric"

11 Agenda BEOL Evolution for Advanced Nodes BEOL Manufacturing Challenges BEOL Failure Modes and Characterization Needs BEOL Reliability Characterization 3D Integration Challenges and Roadmap Page 11

12 New Wafer Quality Monitoring Needs John Chen Nvidia; SPIE August 2012 With 100 million worst-case vias on a 20nm chip, if 10nm is the minimum spacing required to guarantee product lifetime reliability, chip failure would be about 240 DPPM if the standard deviations (σ's) of nth via (VIAn) and nth metal (Mn) layer critical dimensions (CDs) are controlled at 2.0nm and 1.4nm, respectively, and the VIAn-to-Mn alignment σ is as tight as 2.3nm. At 20 and 14nm, if misalignment operates at equipment/foundry provided specs, field reliability failure rate will be >0.1% from misalignment alone PDF is providing full wafer (every reticle shot) electrical misalignment CV coverage to enable fabless to avoid shipping high misalignment die to customers Page 12

13 Concept of ema (Electrical Misalignment) MA = designed-in MA + process MA Process misalignment On purpose mis-alignment in DOE ema uses a set of DUT structures to extract process mis-alignment. Additional DOE factors, e.g., horizontal vs. vertical, can be designed per client request. ema is insensitive to Via size : due to same via size change on all structures in the DOE set (assume uniform local variation) Upper and lower layer CD : for the same reason above Upper and lower border pull back : for the same reason above Thickness between layers : for the same reason above Defectivity : redundancy and safeguard DUT included Wafer tile & rotation on metrology equipment, wafer warpage impact on metrology error (aberrations etc) : no impact Page 13

14 Parametric Issue Capture Large test structures do not capture small parametric changes Need smaller (less contacts/vias per chain) test structures for sensitivity Contact chain Large Small Links 10, Ohm/link Total ohms/chain 600,000 3,000 % change 10% 10% Ohm change 60, and need multiple structures for observability, need to check multiple layout shapes for modern nodes more pads, taking up valuable realestate, and increases test time and need Kelvin measurements for accuracy, which is normally a longer test for typical parametric testers Page 14 Combination of requirements forces need for new layout/test paradigm sensitive parametric measurement multiple unique structures reasonable area & test time

15 Kelvin Array Soft Failure Detection Single die All die on wafer Ability to detect soft failures Soft failures are determined at local level, to isolate from across-wafer trends Parametric structures implemented in a Kelvin Array are very small (5um x 5um), to allow for soft failure detection 40~50 contacts per chain Lengths limited to ~3-4um Small DUT size along with multiplexing allows for thousands of DUTs in a small scribeline area 1-POR - N8A524KAFULLV2-DEFSUMPLI-Gas - N8A524KAFULLV2-DEFSU-PLI-II - N8A524KAFULLV2-DEFSUM Multiple replicates are placed in order to detect soft open fails at die or even sub-die level removing away the within wafer spatial pattern Typical Rs Soft Opens (Global Spec) SiCoNi - N8A524KAFULLV2-DEFSUiSi-Dep1 - N8A524KAFULLV2-DEFSiSi-Dep2 - N8A524KAFULLV2-DEFS Soft Opens (Local Spec) -RTA2 - N8A524KAFULLV2-DEFSUM-BOX - N8A524KAFULLV2-DEFSUMC-CESL - N8A524KAFULLV2-DEFSU Page 15

16 Agenda BEOL Evolution for Advanced Nodes BEOL Manufacturing Challenges BEOL Failure Modes and Characterization Needs BEOL Reliability Characterization 3D Integration Challenges and Roadmap Page 16

17 3D Integration History and Roadmap Source: J. Lau, ITRI Page 17

18 3-D Roadmap Page 18

19 3D Roadmap Page 19

20 3D Roadmap Page 20

21 3-D Technical Challenges Source: V. Tong, Xilinx Page 21

22 2.5D Interposer Solution: Xilinx FPGA Source: V. Tong, Xilinx Page 22

23 Xilinx: 2.5D Passive Interposer Solution Page 23

24 Current Supply Value Chain Page 24

25 Xilinx Supply Value Chain Source: V. Tong, Xilinx Page 25

26 Wide I/O Memory Via-Middle TSV Supply Chain Source: J. Lau, ITRI Page 26

27 3D Integration Roadmap Source: J. Lau, ITRI Page 27

28 3D Integration Roadmap Source: J. Lau, ITRI Page 28

29 3D Development Needs Page 29

30 3D Integration History and Roadmap Source: J. Lau, ITRI Page 30