Stacked Die Advanced Interconnect Technologies

Transcription

1 Orient Semiconductor Electronics, Inc. OSE-USA Stacked Die Advanced Interconnect Technologies Dave Tovar VP of Technology Development OSE-USA Page: 1 Overview Summary Stacked Die Trends Challenges Wafer and Die Thinning Stacked Die Programs - 3 Die Stack, 4 Die Stack, Same Size Die Stack - Equipment - Test Die - Design Rules - Mechanical Simulation - Process Optimization by Design of Experimentation - Environmental Test Results - Future Projects Conclusions Page: 2

2 Summary Due to market demands in the wireless telecommunication industry, OSE has been involved with multiple die stack programs since By year 2000 OSE was thinning wafers via backgrinding to 150 microns thick. Qualification of a 2-die with overhang stack program failed due to approximately 2% of the product dying during thermal gradient environmental tests. The failure mechanism was discovered to be microcracks on the bottom of the top die at the overhang junction. OSE researched and evaluated three different methods of thinning wafers: (a) by backgrinding, (b) by chemical etching, and (c) by atmospheric downstream plasma. Through an alliance with Tru-Si, an ADP wafer thinning organization, both organizations are working together in thinning wafers to 100 microns for a three die stack program and 75 microns for a four die stack program. Tonight we will present design, manufacturing, quality, and environmental test results on these programs. Page: 3 Stacked Die Trends (Why Stacked Die?) Miniaturize: Leaded to Laminate 28x28 QFP x17 Wire Bonded Wire Bonded With Leads: 30.6x30.6mm LFBGA 256 Balls, 1.0mm Pitch sq mm 289 sq mm 69% Space Reduction! MultiChip Modules 4 Pkgs: 37% Space Reduction Stacked Die Wire Bonded Single Die 17x17mm LFBGA 256 Balls 1.0mm Pitch, 289 sq mm Wire Bonded, MultiChip Modules 27x27mm PBGA 400 Balls 1.27mm Pitch, 729 sq mm 4 Die: 60% Space Reduction Wire Bonded, MultiChip Modules 27x27mm PBGA 400 Balls 1.27mm Pitch, 729 sq mm Wire Bonded, Stacked Die 17x17mm LFBGA 256 Balls 1.0mm Pitch, 289 sq mm Page: 4

3 Challenges Establishment of wafer thinning method w/o microcracks Design of Experimentation (DOE) to assure no microcracking Handling of 100 & 75µ thick 200mm diameter wafers Saw, water clean, and removal from attached films Development of reverse wirebond (stitch on ball) Manufacturable process flow and equipment Qualification Cost competitive Stacked die program co-development alliance between two companies to increase R&D headcount and reduce cost + Page: 5 Wafer Thinning Methods Why Thin Wafers? - More die into thinner CSP packages - More electrical function per given area - Operation at higher power levels - Wafer thinning improves ability to dissipate heat Challenges - Resistance to die stress generated by backgrinding - Pkg CTE s (ppm/ C): Si - 3, Substrate - 18, Underfill Thin die stress and damage on backside more prominent - Surface roughness ( peaks and valleys ) - Must increase chip strength Wafer Thinning Methods - Backgrinding and Polish o Rough wheel #100 - #700 o Fine wheel # #4000 o Polish #6000 (grain sizes less 1µ) - Backgrind plus Wet Chemical Etching - Backgrinding plus Dry Chemical Etch (Atmospheric Downstream Plasma, OSE-USA choice) Page: 6

4 Wafer and Die Thinning, ADP Atmospheric Downstream Plasma (ADP) Si Wafer Frontside SiF4 CO2 CO Normal Atmosphere C + 4F Argon CF4 No induced electrical damage No vacuum pumps excellent process control No Etch induced rate electrical for mass production damage No vacuum pumps excellent process control Etch rate for mass production Data Source: Tru Si Page: 7 Atmospheric Downstream Plasma vs. Mech Polish Tru-Si Si s s ADP Etch System Damage Removal after removing 2 to 3 microns of backside silicon Yes, With edge chip and scratch removal Backside Silicon Removal of > 5 Yes microns Low Cost per wafer Mechanical Polishing Yes, but marginal die strength benefits and with minimal edge chip and scratch removal Unacceptable High cost per wafer, low throughput Backside Silicon Removal of > 50 microns Thinning of bumped flip chip wafers Creating rough wafer backside surface to improve metal and film frame adhesion Silicon removal without disturbing thru the silicon structures, such as Thru-Silicon Vias or MEMs structures Wet Chemistry Disposal Yes Yes Improves flip chip assembly reliability Yes Yes Minimal Prohibitive Very high cost per wafer Impractical Impractical Impossible Minimal Data Source: Tru Si Comparison of ADP Dry Chemical Etch Vs. Mechanical Polish for Silicon Wafer Thinning, Grinder Damage Removal, and Backside Roughening Page: 8

5 Fine Grid Grinding Vs ADP Etch 1.0 Cumulative Fraction Understrength Wafers 2,8, & 9 were backgrind, no ADP Wafers 1,3,5,7 were backgrind and ADP ADP treated wafers have stronger die strength Die Strength, Psi. Data Source: Tru Si Page: 9 Wafer and Die Thinning, Benefits of ADP Backside of Wafer After 2000 Grid Backgrind Backside of Wafer After Backgrind Plus 3µ ADP SEM picture after grinding Data Source: Tru Si Page: 10

6 Current CSP Stacked Die Programs Two Die Stacked (Qualified) `` Die Stacked in QFN Three Die Stacked Two Die Stacked Cross-Section (Same Die Size) Page: 11 Equipment OSE-USA Stacked Die Equipment Process Equipment Front End of Line Class 5,000, Area 600 Sq M Wafer Handling TruSi No Touch Wands Wafer Mount Semi-Corp Mounting Wafer Saw & Clean K&S 918 Die Attach Alphasem SL9002 Epoxy Cure Despatch LND Series Plasma Clean March Wire Bond K&S 8028 Pre-Mold Bake Despatch ovens Back End of Line Class 100K; Area 500 Sq M Mold Tsukuba SB-100L Post Mold Cure Despatch Ovens Laser Mark MMS Promark V Ball Attach / Reflow Vitronics Singulation K&S 984 Page: 12

7 Stacked Test Die Wafer Diameter: 200mm Die Configuration: Daisy Chain Die Sizes: 400x340 mils, 400x308 mils, 400x277 mils Bond Pad Pitches: - Outer Row, Staggered, 130µ, 65µ effective - Middle Row, Staggered, 100µ, 50µ effective - Inner Row, Staggered, 90µ, 45µ effective Page: 13 Summary of Stacked Die Design Rules A A Bond Pads to Die Edge, Minimum: 0.381mm Larger Die Edge to Sub Bond Fingers, Minimum: 0.508mm Finger Length, Minimum: Single Bond is 0.254mm; Double Bond is 0.305mm Distance from Finger to Package Edge, Minimum: 0.254mm Two Die Stack B E Two Die Stack Overhang Bond Pads to Die Edge, Minimum: 0.381mm Die Overhang, Maximum: 1.27 Distance from 1 st Die to Substrate Fingers, Minimum: 0.508mm Distance from Overhanging Die to Substrate Fingers, Minimum: 0.381mm Finger Length, Minimum: Single Bond is 0.254mm; Double Bond is 0.305mm Distance from Finger to Package Edge, Minimum: 0.254mm 1 st Die Bond Pads to Top Die Edge, Minimum: 0.381mm Distance from 1 st Die to Substrate Fingers, Minimum: 0.508mm Finger Length, Minimum: Single Bond is 0.254mm Finger Length, Minimum: Double Bond is 0.305mm Finger Length, Minimum: Triple Bond is is Distance from Finger to Package Edge, Minimum: 0.254mm Three Die Stack Overhang Page: 14

8 Wafer Thinning Mechanical Simulation Thick chip: u = 700 µm, b = 1000 µm Thin chip: u = 50 µm, b = 200 µm Software: ANSYS 6.0 Simulated Von Mises stress (fracture criteria for ductile material) of the substrate occurs in the die corners. Package is stress free at 175 C 1/4 Simulation Model Page: 15 Process Optimization Through D.O.E.s Design of Experimentation is an integral part of OSE-USA Technology Development To compare normal forward bonding to reverse bonding and effects on die cracking in terms of process parameters, wire and loop control and process performance in low profile (1.4mm) BGA stacked die packages DOE set-up relative to equipment, die, wire, capillary, wirebonding, die overhang, and optimization of equipment process parameters including bond force, power, temperature, and time. Attributes include visual inspections, loop height measurements, wirebond pulls, die shear tests, Ppk computation, and analysis of results Normal Bonding Reverse Bonding Page: 16

9 Process Optimization Through D.O.E.s Ball Shear By Bond Condition Wire Pull Position 2 By Bond Condition Normal Bonding Reverse Bond Bond Condition All Pairs Tukey-Kramer 0.05 Normal Bond Reverse Bond 1 Bond Condition Reverse Boà All Pairs Tukey-Kramer 0.05 Ball Shear by Bond Condition Wire Pull on Position 2 by Bond Condition Wire pull By Bond Condition 6.0 Wire pull position 3 By Bond condition Reverse Bond 2 Reverse bond 1 Bond Condition normal bond All Pairs Tukey-Kramer Normal Bond Reverse Bond 1 Reverse Boà Bond condition All Pairs Tukey-Kramer 0.05 Wire Pull on Position 1 by Bond Condition Wire Pull on Position 3 by Bond Condition Software: SAS-Jmp Variance Analysis Conclusions (both forward and reverse bonding are acceptable) Page: 17 Stacked Die Process Flow Key Process Key Process Wafer Grinding Wafer Saw Stack Die Attach (Paste & Film) Plasma Clean Key Process Wire Bonding Plasma Clean Molding Post Mold Curing Laser Mark Ball Placement Singulation (Package Saw) Electrical Test Dry Packing Ship Out Page: 18

10 Qualification Problems Silicon die thicknesses were 150 microns on this evaluation Approximately 2% of the assembled and molded units were failing on temperature gradient tests Failure mechanism was cracked die at overhang junction Failures attributed to microcracks caused by backgrinding Page: 19 Yr 2002 Environmental Test Results Environmental Test Results with ADP Thinning Package Size 15 x 15mm, 176 Balls 15 x 15mm, 176 Balls Number of Die Three Three OSE-USA Stacked Die Environmental Test Data Die Dimensions 100µ Thick 6.4x4.4mm 8.4x4.4mm 9.4x4.5mm 100m Thick 6.4x4.4mm 8.4x4.4mm 9.4x4.5mm Stacked Die Pyramid Pyramid Environmental Test Conditions Results Pre-Condition, Level 3 Reflow 260 C, 30 C/60% RH, 192 Hrs 0/25 CSAM Through Scan 0/25 High Temperature Storage 150 C, 1000 Hrs, No Bias 0/25 Temperature Cycle -55 C to 125 C, 500 Cycles 0/25 Temperature Cycle -65 C to 150 C, 500 Cycles 0/25 Autoclave 121 C, 2 atm, 168 Hrs 0/25 Pre-Condition, Level 3 Reflow 260 C, 30 C/60% RH, 168 Hrs 0/77 High Temperature Storage 150 C, 168 Hrs, No Bias 0/77 Temperature Cycle -55 C to 125 C, 250 Cycles 0/77 Autoclave 121 C, 2 atm, 96 Hrs 0/77 Package Size 10x10mm 109 Balls 14x22mm 209 Balls Number of Die Two Die, One Spacer Two Die, One Spacer OSE-Taiwan Stacked Die Environmental Test Data Die Dimensions 150µ Thick 6.3x6.7mm 150µ Thick 9.9x12.2mm Stacked Die Same Size Die Same Size Die Environmental Test Conditions Results Pre-Condition, Level 3 Reflow 260 C, 30 C/60% RH, 192 Hrs 0/180 Temperature Cycle -65 C to 150 C, 1000 Cycles 0/45 Thermal Shock -65 C to 150 C, 500 Cycles 0/45 Hight Temp Storage 150 C, No Bias, 1000 Hrs 0/45 Autoclave 121 C, 2 atm, 168 Hrs 0/45 Temperature and Humidity 85 C/85% RH, No Bias, 1000 Hrs 0/45 Pre-Condition, Level 3 Reflow 260 C, 30 C/60% RH, 192 Hrs 0/62 CSAM Through Scan 0/62 Temperature Cycle -65 C to 150 C, 500 Cycles 0/62 CSAM Through Scan 0/62 Page: 20

11 Future CSP Stacked Die Programs Flip Chip on Top of Flip Chip Flip Chip on Bottom of Flip Chip Flip Chip on Top Flip Chip on Bottom Chip 2 Chip 1 Flip Chip on Bottom Wire Bond Die on Top MultiChip Modules 3 Die Stack with Interposer 2 Die Wirebonded 1 Die Flip Chip Page: 21 Conclusions Selection of backgrinding and ADP is the right choice 100µ for 3 die stack and 75µ for 4-die stack is manufacturable No die cracking after saw, pick and place, wire bonding of pyramid, same size, and overhang die Current initial environmental test results are positive I would like to give recognition to the following folks which provided technical information for this article: OSE-USA Gerry Balanon Mitch Duh Rainbow Hjing W.L. Shieh Mitzie Tecson Tru Si Pat Halahan Lorie Cantillep Dr. Andy Feng Ernie Opiniano Paul Sun Tony Wang Phil Marcoux Page: 22