DESIGN AND RELIABILITY ANALYSIS OF A 4:1 MUX USING SINGLE ELECTRON TUNNELING TECHNOLOGY BASED THRESHOLD LOGIC GATE

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1 Journal of Eltron Dvis, Vol. 15, 2012, pp JED [ISSN: ] DESIGN AND RELIABILITY ANALYSIS OF A 4:1 MUX USING SINGLE ELECTRON TUNNELING TECHNOLOGY BASED THRESHOLD LOGIC GATE Rivd , onlin Amit Jain, Subir Kumar Sarkar Dpartmnt of Eltronis and Tlommuniation Enginring Jadavpur Univrsity, Kolkata , India amit2_8@yahoo.o.in ABSTRACT As singl ltron tunnling thnology basd thrshold logi gat uss lss no of tunnl juntions so it rdus th siz of Boolan logi gat ompar to singl ltron tunnling basd logi gat and singl ltron transistor basd logi gat. Th dsign and simulation of a 4:1 multiplxr basd on buffrd thrshold logi gat is prsntd in this papr. Th logi opration is vrifid using Mont Carlo basd simulation tool SIMON. Th rliability of th dsignd iruit is analyzd using MATLAB and SIMON. A omparison of th rliability for normal and uniform distribution of bakground hargs has bn shown in th prsnt work. Th stability of th iruit is analyzd using fr nrgy history diagram and stability plot. Also th stability analysis for diffrnt oprating tmpratur has bn shown in this papr. Kywords: Singl ltron tunnling (SET), Thrshold logi gat (TLG), Rliability Analysis, 4:1 Mux, Fr Enrgy History Diagram, Stability Plot. I. INTRODUCTION Du to siz limitations vn with saling down MOSFET thnology annot ontinu forvr. It an hardly go byond a fw nanomtrs vn if adquat lithographial thnology is availabl. Thr hav bn rports, that th CMOS thnology will prsumably b ontinud up to th yar 2014 by th wll known saling of strutur gomtry[1]. As a onsqun th sarh for nw prinipls of opration of th small siz dvis is boming mor and mor important. Givn th antiipatd nd of th CMOS ra, svral altrnativ thnologis hav bn undr invstigation for th last two dads. Ths andidat thnologis inlud, amongst othrs, Singl Eltron Dvi (SED), Carbon Nanotubs, Rapid Singl Flux Quantum (RSFQ), Rsonant Tunnling Diods (RTD), and Magnti Spin dvis. Th singl ltron tunnling (SET) thnology is on of th most promising andidats to mt th rquird inras in dnsity, prforman and dras in powr dissipation [2-5]. Th ky proprty of singl ltron tunnling thnology is th ability to ontrol th transport of individual ltrons. This proprty an b usd to nod Boolan valus dirtly as singl ltron hargs. On approah for that as first suggstd in [2] is basd on th transport of singl ltron harg from on island to anothr through tunnl juntions, suh that Boolan input signals onsist of th prsn or absn of th arriving harg. So, Thrshold logi gat(tlg) an b an altrnativ to Boolan logi gats in trms of logi funtions. C. Lagwg t al implmntd thrshold logi gat for th first tim mploying SET thnology. A numbr of invstigations hav bn rportd rgarding th thrshold logi basd dsigns and implmntation of usful Boolan logi funtions [7-9].Evn though th dsign and simulation of singl ltron 4:1 multiplxr hav bn rportd in litratur [13],thr is no rport of thrshold logi basd dsign of 4:1 multiplxr. Hn w hav rportd hr th dsign and rliability analysis of a 4:1 multiplxr using singl ltron tunnling thnology basd TLG as Singl ltron tunnling basd thrshold logi gat uss lss numbr of tunnl juntions ompars to SET basd systm, whih rdus th siz of th logi gats. Low dimnsional smionduting dvi (lik SET basd thrshold logi) basd iruits ar statistially lss rliabl du to its snsitivnss towards a varity of random noiss [10]. So, an important issu with th thrshold logi basd gat is th rliability whih dpnds on iruit strutur, paramtr valus, tmpratur and random bakground hargs. From 1241

2 dsignr point of viw th most important on is th random bakground hargs as it an not b ontrolld by th dsignr and ompltly dpnds on th fabriation pross. Thr hav bn rports [10-11] rgarding th rliability analysis of thrshold logi gat but thr is no rport on rliability analysis of thrshold logi gat basd logi iruits. In this papr w hav fousd on th rliability analysis of a 4:1 multiplxr. W hav furthr analyzd th stability of th dsignd iruit. Th main ontribution of this papr an b summarizd as follows: Th dsign and simulation of a 4:1 multiplxr using singl ltron tunnling thnology basd thrshold logi gats. Rliability analysis of th proposd iruit with diffrnt bakground harg distribution. Stability analysis of th dsignd iruit with diffrnt oprating tmpratur. II. BACKGROUND Th basi lmnt of singl ltron tunnling thnology is th tunnl juntion. A tunnl juntion an b onsidrd as two ondutors sparatd by a thin layr of insulating matrial as shown in Fig.1. Th tunnl juntion is haratrizd by a apaitan C j and a rsistan R j ah of whih dpnds on th physial siz of th tunnl juntion and th thiknss of th insulator. As th thiknss of th diltri is vry thin th tunnl juntion an b onsidrd as a laky apaitor [12]. Th transport of hargs through a tunnl juntion is rfrrd to as tunnling [2]. Th harg transport mhanism is disrt in natur[2]. Th voltag that is ndd aross th tunnl juntion for a tunnl vnt to our is known as ritial voltag. Th valu of th ritial voltag is givn by [2]: V (1) 2( C C ) j th iruit thn th iruit is in a stabl stat. As th harg transport mhanism is stohasti in natur [2] so a limitd numbr of tunnl vnts an b onsidrd to our during a stabl stat of th iruit. Th swithing dlay of a singl ltron transport an b alulatd as [2] t d ln( P ) q R ror t V V j (3) Whr R t is th tunnl rsistan and it is assumd to b 10 5 Ω. P rror is th probability that th tunnl vn has not ourrd aftr t d sonds. Th nrgy onsumd by a singl tunnl vnt an b alulatd by dtrmining th diffrn in th total amount of nrgy prsnt in th iruit bfor and aftr th tunnl vnt whih an b alulatd by [2] E E E q ( V V ) (4) initial final j III. THRESHOLD LOGIC GATE Thrshold logi gat oprats on a prinipl of omparison btwn th wightd sum of inputs and a thrshold valu. If th wightd sum of inputs is gratr than or qual to th thrshold, th output is logi 1.othrwis th output is a logi 0. Th funtion whih satisfis th abov onditions is givn by [12] if F(X) 0 F(X) sgny(x) (5) if F(X) 0 n i i (6) i1 F X w x T whr x i ar th n boolan inputs and w i ar th orrsponding n intgr wights. Th thrshold gat implmntd in [4] allows only for positiv wights. Howvr th thrshold logi gat proposd in [6] Whr =1.602*10-19 C, Cj is th tunnl juntion apaitan and C is th quivalnt apaitan for rmaindr of th iruit as sn from th tunnl juntion prsptiv. A tunnl vnt will our aross th tunnl juntion if and only if th voltag aross th juntion V j is gratr than or qual to V i. V j V (2) Othrwis th tunnl vnt will not our and this phnomnon is known as oulomb blokad. If no tunnl vnt ours in any of th tunnl juntion in Fig.1: Thrshold logi gat strutur 1242

3 Fig. 2: Th proposd iruit allows for both positiv and ngativ wights as shown in figur 1. Th input voltags V p (wightd by thir input apaitors C p ) ar addd to th nod x and inputs V n (wightd by thir input apaitors C n ) ar subtratd from voltag aross th juntion. Th bias voltag V b is usd to adjust th ritial voltag V. th funtion F(X) for th iruit shown in Fig.1 is givn by[6] r S n P P P n n K K l l k1 l1 (7) F X C C V C C V T whr 1 ( P n ) n T C C C CbV 2 r p P C Cb Ck k1 b (8) (9) 1243 S n n C C0 C l l1 (10) In this brif w will assum th Boolan input/output signals orrspond to th following voltags: logi 0= 0 V. and logi1=0.1*q /CV, whr C=1aF whih rsults in logi1=16 mv. IV. THE PROPOSED CIRCUIT In th proposd dsign of th multiplxr w hav not usd th onvntional arhittur of a multiplxr whr two NOR gats, four thr inputs AND gats and a four inputs OR gat ar rquird. Th proposd iruit is shown in Fig. 2, whih onsists of 101 nods, 59 tunnl juntions and 104 apaitors. It has bn rportd that strong fdbak ffts our in iruits onsists of ths gats so adding an ativ buffr at th output of th gat rdus th fdbak fft onsidrably. Though th swithing spd of th TLG is of th sam ordr as ltron tunnling

4 spd through a tunnl barrir, as output is takn from th island th pratial implmntation nds CMOS lik SET invrtrs. That s why w hav usd buffrd logi gats for th dsign. But to gt th rsult orrtly w nd to pla two asadd buffr at th output of ah gat, whih maks th iruit biggr in siz and taks lots of ara. To solv this problm th iruit has bn dsignd in a top-down mannr and finally only on buffr has bn addd to ah gat, so pratially th iruit will not follow th onvntional dsign flow, but it will oprat lik a multiplxr funtionally. it is obsrvd that th siz of th dsignd iruit inrass du to us of buffrd logi gats but on th othr hand it inrass stability of th iruit W invstigatd that a thr input or four input thrshold logi gat dos not work vry wll whn inorporatd in th iruit so w hav usd two input thrshold logi gats in all ass. Only two diffrnt voltag sours hav bn usd in th iruit whras six diffrnt voltag sours hav Voltag sours Proposd Ciruit Tabl 1 Diffrnt voltag sours V1(V) V2(V) V3(V) V4(V) V5(V) [13] bn usd in [13] as givn in Tabl 1. S0 and S1 ar two ontrol signals and th four inputs ar namd as I0, I1, I2, and I3 as shown in Fig 2. For th buffr/invrtr th paramtrs ar takn from [2]. Th proposd iruit has similar input and output digital lvls i.. high=16 mv and low=0 mv. Th input voltags ar applid to nods N1, N2, N3, and N4 through th apaitors C1, C2, C3 and C4 rsptivly, whih ar idntial, and thir apaitan is 0.5 C. Th output is takn from nod N6. An ltron tunnling from nod N6 to Vdd1 orrsponds to logi 1 as it lavs a positiv harg in th output nod. Th absn of th positiv harg in th island orrsponds to logi 0. V. SIMULATION RESULTS AND DISCUSSION Th dsignd iruit has bn tstd using SIMON [12], a nanoltronis strutur simulation softwar. Th ontrol signals ar pi wis linar and provids all four ombinations of input. Th input signals ar ithr a logi 0 or a logi 1. So dpnding upon th ontrol signal s ombination w will gt th rsptiv output. All th possibl four outputs namd as O1, O2, O3 and O4 hav bn shown in Fig. 3.Th final output, MUX_O has bn shown in Fig. 4 All th inputs orrsponding to th ontrol signal ombination ar givn in Tabl 2. Th ontrol Fig. 3: Two ontrol signals (S0 and S1) and four possibl outputs (O1, O2, O3 and O4 orrsponding to [S0, S1]=[0, 0], [0, 1], [1, 0] and [1, 1] rsptivly).

5 Tabl 2 Input s Valus S0 S1 INPUT(V) Logi Valu Dsignation I I I I3 signals S0 and S1 hav bn shown in Fig. 3. It an b obsrvd from Fig. 3 that th valu for both th signals O1 and O4 is 0.001V, whih is bing onsidrd as logi 0. A point to b notd hr is w hav usd puls wav form for ontrol signals instad of using a DC signal of valu 0.0V or 0.016V. If w would hav usd a DC signal as a ontrol signal ah tim to hk for all th possibl ombinations output nod. So it is onludd that only on ltron is allowd to lav th output nod for gtting a logi 1 valu. VI. RELIABILITY ANALYSIS At th tim of fabriation random hargs ar produd as bakground hargs on nods of singl ltron dvis. Ths bakground hargs rat xtra voltag whih vntually hangs th total voltag aross th juntion [11], du to whih th iruit may not work proprly and th iruit boms unrliabl. As th hargs produd ar random in natur so pratially it an tak any kind of distribution. Hr w hav usd th mostly usd distributions namly uniform distribution and normal distribution to haratriz th random hargs. i) Assuming all th nods in th dsignd iruit hav bakground hargs with uniform probability distribution givn by 1 z z, p 2 q (11) q 0, othrwis Fig. 4: Final Output of th Multiplxr thn w would hav ndd ight diffrnt signals with four for ah of th ontrol signal. But with th approah w hav usd w nd only on varity for ah of th ontrol signal whih obviously inrass th radability of th iruit. Fig.5: Tim variation of th harg at th output nod N5 of th dsignd iruit Th tim variation of th harg at th output nod N5 is shown in Fig. 5. It an b obsrvd omparing Fig. 4 and Fig. 5 that th output is a logi 1 whn thr is a positiv harg (1.6*10-19 ) at th output nod N5 and th output is a logi 0 if thr is no harg at th whr z is th random variabl and q is th harg of an ltron. So th rang of th variabl z is q. Hr rprsnts th xtnt of th variation so it is alld variation fator. Th random data with uniform distribution has bn gnratd using MATLAB s random numbr gnration toolbox. Th distribution of random data orrsponding to =0.04 has bn shown in Fig. 6. ii) It is assumd that th random bakground hargs an tak normal distribution with standard dviation : 2 Z1 2 2 p( z1) 1/ ( 2 ) ) (12) Whr z1=z/q, and z is th random variabl whih rprsnts th random bakground harg valu. In as of normal distribution 98% of th ara is within two standard dviation and 99.7% of th ara is within thr standard dviation [21] so th valu of th standard dviation is takn as ( / q ), whr th rang of th variabl is q. Th normally distributd data orrsponding to = 0.03 has bn shown in Fig. 7. Th rliability tst for th dsignd iruit has bn don as follows.

6 th valu of =0.01 both distribution givs almost sam rsult. In as of uniform distribution a larg fall is notid aftr =0.02 whih drass th iruit rliability from 76% to 25%, and aftr =0.035 th iruit boms almost unrliabl. But in as of normal distribution as it an b obsrvd th iruit rmains rliabl for all th valus of with th lowst valu of 40 %. Th dtails data rgarding iruit rliability with variation fator for both typ of distribution ar givn in Tabl 3. Fig. 6: Uniform distribution of random data Fig. 8: Rliability of th iruit with normal and uniform distribution of bakground hargs Fig. 7: Normal distribution of random data 1) Following uniform distribution random data ar gnratd using MATLAB with ) Th random data ar distributd among all th 104 nods and thn th iruit is simulatd with SIMON to hk th opration. 3) Stp 1-2 is rpatd T=100 tims with nw random data. 4) If th no of orrt outputs is S thn th rliability r of th dsignd iruit is alulatd as r = S/T (13) 5) Stp 1-4 is rpatd with =0.02, 0.03 and ) Stp 1-5 is rpatd for normal distribution. Th plot orrsponding to uniform and normal distribution of random bakground hargs with diffrnt valu has bn shown in Fig. 8. It an b analyzd omparing two plots that random bakground hargs with normal distribution givs bttr rliability ompar to uniform distribution. For Tabl 3 Dtails of iruit rliability with variation fator Ciruit rliability (%) Variation Fator( ) Normal Distribution VII. STABILITY ANALYSIS Uniform Distribution Th fr nrgy history diagram of th iruit for th transition of th output from 0 to 1 is shown in Fig. 9(a). Transportation of ltron in th output buffr from nod N6 to Vdd1 for this transition is shown in Fig. 9(b). In th first tim stp no harg is prsnt in th nod. In sond tim stp ltron tunnls from nod N6 to nod N7 via J3. Finally th ltron is transportd from nod N7 to Vdd1 through J4 ausing th systm to rah a loal minimum as shown in Fig. 9(a). So absn of ltron in th nod orrsponds to a logi 1 valu. Th tim stps in th Fig 9(a) dfin th tim rquird for an ltron to travl from on nod to anothr. Th fr nrgy of th systm is alulatd as [2].

7 E f Whr 3 E (14) i1 t 1 is th fr nrgy for ah tim stp. Th fr nrgy orrsponding to ths is alulatd as 0.044V. (a) (b) Fig. 9: (a) Fr nrgy history diagram, (b) Eltron tunnling phnomna in th output buffr Th stabl opration of th iruit is tstd using SIMON. Th stability plot of th dsignd iruit is shown in Fig. 10. Eah point in th stability plot orrsponds to a ombination of two ontrol signals. SIMON works on th prinipl of alulating fr nrgy for ah point on th stability plot. Th loal minima of th iruit fr nrgy orrsponds to a stabl ondition and ths points ar olord in whit whih also provs that ths ombinations of ontrol signal vtor prohibits ltron tunnling, kping th ltrons in th islands. Th points orrspond to loal maxima of th iruit fr nrgy ar olord blak and onsidrd as unstabl points. Th rst of th points ar olord gry whih stands for th justifiation of th small urrnt that runs through th juntions. Th points orrspond to th input ontrol signal vtors [0, 0], [0, 1], [1, 0], [1, 1] ar prsntd as A, B, C and D rsptivly as shown in Fig. 10. It an b obsrvd from th figur that all th four points ar in stabl rgions. On of th major onrns rgarding th stability of th dsignd iruit is tmpratur. Th harging nrgy that is th nrgy rquird for an ltron to tunnl is givn as [17] E 2 /2C (15) Now if th availabl voltag sours ouldn t provid this muh nrgy thn no ltron tunnling taks Fig. 10: Stability plot of th iruit with: A= [0, 0], B= [0, 1], C= [1, 0], D= [1,1] and T= 0 K. pla and th situation is known as oulomb blokad. If th availabl thrmal nrgy is gratr than th harging nrgy thn ltron tunnling ours whih rsults in instability of th iruit. So taking th thrmal nrgy into onsidration th ondition for th stability is [17] E 2 /2C k T (16) B To obsrv th stability dpndn on th tmpratur, th stability of th iruit is again plottd with a inras in tmpratur as shown in Fig. 11. It an b obsrvd that in Fig. 10 all th four points ar olord whit, whih provs th dsignd iruit is stabl for all th ombinations of ontrol input for th usd rang. But if w inras th tmpratur iruit boms unstabl. It is obsrvd in Fig. 11 that loal maxima of th iruit fr nrgy orrsponding to A, B, C, and D ar inrasing with inras in tmpratur whih implis that with inras in tmpratur tunnling vnt inrass whih in turn inrass th fr nrgy of th systm. Th fr nrgy orrsponding to th most blak olord points of Fig. 10 (T=0K) is whih for Fig. 11(T=2K) is Fig. 11: Stability plot of th iruit with: A= [0, 0], B= [0, 1], C= [1, 0], D= [1, 1] and T=2 K

8 So it an b onludd that th fr nrgy of th ovrall iruit is inrasing with inras in tmpratur whih implis that th no of tunnling vnt is inrasing with inras in tmpratur ausing th iruit to bom unstabl. VIII. CONCLUSION In this brif th dsign and simulation of a singl ltron 4:1 multiplxr is prsntd. A top down or bhavioral approah has bn usd for dsigning th iruit. Buffrd thrshold logi gats hav bn usd in th iruit as a dfns for th fdbak fft and to inras th stability. For th variation fator of 0.02 th iruit is highly rliabl for both uniform and normal distribution of bakground hargs. For valus gratr than 0.02 th iruit boms lss rliabl for uniform distribution, but for normal distribution th iruit rmains almost rliabl. Ciruit s stability is vrifid through stability plot and fr nrgy history diagram using SIMON. It has bn shown that th iruit s stability also dpnds on tmpratur and th stability plots rlatd to this issu hav bn shown in this papr. Rfrns [1] N. Basanta Singh, Sanjoy Db, Asish Kumar D and Subir Kumar Sarkar, "Dsign and Simulation of 2 to-4 Dodr Using Singl Eltron Tunnling Thnology basd Thrshold Logi Gat" Journal of Eltron Dvis 9, (2011). [2] C. Lagwg, S. Cotofana, and S. Vassilidis, "Singl Eltron Enodd Laths and Flip-Flops", IEEE Trans. On Nanothnology 3, (2004). [3] Chaohong Hu, Sorin Dan Cotofana, and Jianfi Jiang, "Singl-Eltron Tunnling Transistor Implmntation of Priodi Symmtri Funtions", IEEE Trans. Ciruits & Systms-II: Exprss Brifs, 51, (2004). [4] R.H Chn, A. N. Korotkov, and K. K.Likharv, "Singlltron transistor logi", Appl. Phys.Ltt. 68, (1999). [5] K. Likharv, "Singl-Eltron Dvis and Thir Appliation", Pro. IEEE 87, (1999). [6] C. Lagwg, S. Cotofana, and S. Vassilladis, "A Linar Thrshold Gat Implmntation in Singl Eltron Thnology," IEEE Computr Soity Workshop on VLSI, pp , April [7] M. Avdillo, J. M. Quintana, A. Ruda, and E. Jimnz, "Low-powr CMOS thrshold-logi gat", Eltri Lttrs, 31, (1995). [8] J. Frnandz Ramos, J. A. Hidalgo Lopz, M. J. Martin, J. C. Tjro and A. Gago, "A thrshold logi gat basd on lokd oupld invrtr, Intrnational Journal of Eltronis 84, (1998). [9] S. Muroga, Thrshold Logi and its Appliations, Wily and Sons In. (1971). [10] C. Chn, A Statistial Rliability Modl for Singl Eltron Thrshold Logi IEEE Trans. On Eltron Dvis 55, (2008). [11] C. Chn and J. Mi, paramtr sltion for singl ltron thrshold logi with rliability analysis Pro. IEEE Int. Conf. Nanothnol., Cininnati, OH, Jul. 2006, 1, pp [12] Santanu Mahapatra. Hybrid CMOS "Singl-Eltron- Transistor Dvi and Ciruit Dsign" Arth Hous Publiation (2006). [13] T. Tsiolakis, N.Konofaos, G.Ph.Alxiou A omplmntary singl ltron 4 bit multiplxr Quality Eltroni Dsign, 2 nd Asia Symp. Patras, Gr, Aug. 2010, pp [14] S. E. Rhan "Th implmntation of 2-bit dodr using singl ltron linar thrshold gats" Int. Conf. On Miroltronis (ICN), Mansoura, Egypt, D. 2010, pp [15] G. Zardalidis, I. Karafyllidis: Dsign and simulation of a nanoltroni singl-ltron ontrol not gat, Miroltron. J., 37, (2006). [16] Chirstoph Wasshubr, "SIMON-A simulator for singlltron tunnl dvis and iruits", IEEE Trans. On Computr Aidd Dsign of Intgratd Ciruits and Systms, 16, (1997). [17] C. Wasshubr: Computational Singl-Eltronis (Computational Miroltronis), Springr, Nw York, (2001). [18] G. Zardalidis, I. Karafyllidis: A singl-ltron full addr, IEE Pro. Ciruits, Dv. Syst., 150, (2003). [19] I. Karafyllidis, Singl-ltron OR gat, Eltron. Ltt., 36, (2000). [20] T. Tsiolakis, N. Konofaos, G. Ph. Alxiou: Dsign, simulation and prforman valuation of a singl-ltron 2-4 dodr, Miroltronis Journal 39, (2008). [21] Jagdish K. Patl, Campbll B. Rad "Handbook of th normal distribution"taylor and Franis (1996).