Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

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1 Downloadd from orbitdtudk on: Jan 06, 2019 Schduling of onditional Procss Graphs for th Synthsis of Embddd Systms Els, Ptru; Kuchcinski, Krzysztof; Png, Zbo; Pop, Paul; Doboli, Alx Publishd in: Procdings of th confrnc on Dsign, automation and tst in Europ Link to articl, DOI: /DATE Publication dat: 1998 Documnt Vrsion Publishr's PDF, also known as Vrsion of rcord Link back to DTU Orbit itation (APA): Els, P, Kuchcinski, K, Png, Z, Pop, P, & Doboli, A (1998) Schduling of onditional Procss Graphs for th Synthsis of Embddd Systms In Procdings of th confrnc on Dsign, automation and tst in Europ: Th Most Influntial Paprs of 10 Yars DATE (pp ) Springr DOI: /DATE Gnral rights opyright and moral rights for th publications mad accssibl in th public portal ar rtaind by th authors and/or othr copyright ownrs and it is a condition of accssing publications that usrs rcognis and abid by th lgal rquirmnts associatd with ths rights Usrs may download and print on copy of any publication from th public portal for th purpos of privat study or rsarch You may not furthr distribut th matrial or us it for any profit-making activity or commrcial gain You may frly distribut th URL idntifying th publication in th public portal If you bliv that this documnt brachs copyright plas contact us providing dtails, and w will rmov accss to th work immdiatly and invstigat your claim

2 Schduling of onditional Procss Graphs for th Synthsis of Embddd Systms Ptru Els 1,2, Krzysztof Kuchcinski 1, Zbo Png 1, Alxa Doboli 2, and Paul Pop 2 1 Dpt of omputr and Information Scinc Linköping Univrsity Swdn 2 omputr Scinc and Enginring Dpartmnt Tchnical Univrsity of Timisoara Romania Abstract W prsnt an approach to procss schduling basd on an abstract graph rprsntation which capturs both dataflow and th flow of control Targt architcturs consist of svral procssors, ASIs and shard busss W hav dvlopd a huristic which gnrats a schdul tabl so that th worst cas dlay is minimizd Svral xprimnts dmonstrat th fficincy of th approach 1 Introduction In this papr w concntrat on procss schduling for systms consisting of communicating procsss implmntd on multipl procssors and ddicatd hardwar componnts In such a systm in which svral procsss communicat with ach othr and shar rsourcs, schduling is a factor with a dcisiv influnc on th prformanc of th systm and on th way it mts its timing constraints Thus, procss schduling has not only to b prformd for th synthsis of th final systm, but also as part of th prformanc stimation task Optimal schduling, in vn simplr contxts than that prsntd abov, has bn provn to b an NP complt problm [13] In our approach, w assum that som procsss can b activatd if crtain conditions, computd by prviously xcutd procsss, ar fulfilld Thus, procss schduling is furthr complicatd sinc at a givn activation of th systm, only a crtain subst of th total amount of procsss is xcutd and this subst diffrs from on activation to th othr This is an important contribution of our approach bcaus w captur both th flow of data and that of control at th procss lvl, which allows an accurat and dirct modling of a wid rang of applications Prformanc stimation at th procss lvl has bn wll studid in th last yars [10, 12] Starting from stimatd xcution tims of singl procsss, prformanc stimation and schduling of a systm containing svral procsss can b prformd In [14] prformanc stimation is basd on a prmptiv schduling stratgy with static prioritis using rat-monotonic-analysis In [11] schduling and partitioning of procsss, and allocation of systm componnts ar formulatd as a mixd intgr linar programming problm whil th solution proposd in [8] is basd on constraint logic programming Svral rsarch groups considr hardwar/ softwar architcturs consisting of a singl programmabl procssor and an ASI Undr ths circumstancs driving a static schdul for th softwar componnt practically mans th linarization of a dataflow graph [2, 6] Static schduling of a st of data-dpndnt softwar procsss on a multiprocssor architctur has bn intnsivly rsarchd [3, 7, 9] An ssntial assumption in ths approachs is that a (fixd or unlimitd) numbr of idntical procssors ar availabl to which procsss ar progrssivly assignd as th static schdul is laboratd Such an assumption is not accptabl for distributd mbddd systms which ar typically htrognous In our approach w considr mbddd systms spcifid as intracting procsss which hav bn mappd on an architctur consisting of svral procssors and ddicatd hardwar componnts connctd by shard busss Procss intraction in our modl is not only in trms of dataflow but also capturs th flow of control undr th form of conditional slction onsidring a non-prmptiv xcution nvironmnt w statically gnrat a schdul tabl for procsss and driv a worst cas dlay which is guarantd undr any conditions Th papr is dividd into 7 sctions In sction 2 w formulat our basic assumptions and introduc th graph-basd modl which is usd for systm rprsntation Th schdul tabl and th gnral schduling stratgy ar prsntd in sctions 3 and 4 Th algorithm for gnration of th schdul tabl is prsntd in sction 5 Sction 6 dscribs th xprimntal valuation and sction 7 prsnts our conclusions 2 Problm Formulation and th onditional Procss Graph W considr a gnric architctur consisting of programmabl procssors and application spcific hardwar procssors (ASIs) connctd through svral busss Ths busss can b shard by svral communication channls conncting procsss assignd to diffrnt procssors Only on procss can b xcutd at a tim by a programmabl procssor whil a hardwar procssor can xcut procsss in paralll Procsss on diffrnt procssors can b xcutd in paralll Only on data transfr can b prformd by a bus at a givn momnt omputation and

3 P 4 P 2 P 5 P 6 P 1 P 8 P 9 P 7 P 10 P 17 data transfr on svral busss can ovrlap In [4] w prsntd algorithms for automatic hardwar/ softwar partitioning basd on itrativ improvmnt huristics Th problm w ar discussing in this papr concrns prformanc stimation of a givn dsign altrnativ and schduling of procsss and communications Thus, w assum that ach procss is assignd to a (programmabl or hardwar) procssor and ach communication channl which conncts procsss assignd to diffrnt procssors is assignd to a bus Our goal is to driv a worst cas dlay by which th systm complts xcution, so that this dlay is as small as possibl, and to gnrat th schdul which guarants this dlay As an abstract modl for systm rprsntation w us a dirctd, acyclic, polar graph Γ(V, E S, E ) Each nod P i V rprsnts on procss E S and E ar th sts of simpl and conditional dgs rspctivly E S E = and E S E = E, whr E is th st of all dgs An dg ij E from P i to P j indicats that th output of P i is th input of P j Th graph is polar, which mans that thr ar two nods, calld sourc and sink, that convntionally rprsnt th first and last procss Ths nods ar introducd as dummy procsss so that all othr nods in th graph ar succssors of th sourc and prdcssors of th sink rspctivly Th mapping of procsss to procssors and busss is givn by a function M: V PE, whrpe={p 1, p 2,,p Np }is th st of procssing lmnts For any procss P i, M(P i )isth procssing lmnt to which P i is assignd for xcution Each procss P i, assignd to procssor or bus M(P i ), is charactrizd by an xcution tim t Pi In th procss graph dpictd in Fig 1, P 0 and P 32 ar th sourc and sink nods rspctivly Nods dnotd P 1, P 2,,P 17, ar "ordinary" procsss spcifid by th dsignr Thy ar assignd to on of th two programmabl procssors p 1 and p 2 or to th hardwar componnt p 3 Th rst ar so calld communication procsss (P 18, P 19,, P 31 ) Thy ar rprsntd in Fig 1 as black dots and ar introducd for ach connction which links procsss mappd to diffrnt procssors Ths procsss modl intr-procssor communication and thir xcution tim is qual to th corrsponding communication tim An dg ij E is a conditional dg (thick lins in Fig 1) and it has an associatd condition Transmission on such an P 3 P 0 P 14 P 32 P 12 K K P 15 Fig 1 onditional Procss Graph with xcution tims and mapping D P 16 P 11 Excution tim t Pi for procsss P i t P1 : 3 t P6 : 5 t P11 :6 t P16 :4 D P2 t P3 : 12 P7 t P8 : 4 t : 4 t : 3 t P12 :6 t P13 :8 t P17 :2 P 13 t P4 : 5 t P9 : 5 t P5 : 3 t P10 :5 t P14 :2 t P15 :6 Excution tim t i,j for communication btwn P i and P j t 1,3 : 1 t 4,7 : 3 t 11,12 :1 t 13,17 :2 t 2,5 : 3 t 6,8 : 3 t 11,13 :2 t 16,17 :2 t 3,6 : 2 t 7,10 : 2 t 12,14 :1 Procss mapping t 3,10 :2 t 8,10 : 2 t 12,15 :3 Procssor p 1 :P 1,P 2,P 4,P 6,P 9,P 10,P 13 Procssor p 2 :P 3,P 5,P 7,P 11,P 14,P 15,P 17 Procssor p 3 :P 8,P 12,P 16 ommunications ar mappd to a uniqu bus dg taks plac only if th associatd condition is satisfid W call a nod with conditional dgs at its output a disjunction nod (and th corrsponding procss a disjunction procss) Altrnativ paths starting from a disjunction nod, which corrspond to a crtain condition, ar disjoint and thy mt in a so calld conjunction nod (with th corrsponding procss calld conjunction procss) In Fig 1 circls rprsnting conjunction and disjunction nods ar dpictd with thick bordrs W assum that conditions ar indpndnt A boolan xprssion X Pi, calld guard, can b associatd to ach nod P i in th graph It rprsnts th ncssary condition for th rspctiv procss to b activatd In Fig 1, for xampl, X P3 =tru, X P14 =D K, X P17 =tru, X P5 = Two nods P i and P j,whrp j is not a conjunction nod, can b connctd by an dg ij only if X Pj X Pi (which mans that X Pi is tru whnvr X Pj is tru) This rstriction avoids spcifications in which a procss is blockd bcaus it waits for a mssag from a procss which will not b activatd If P j is a conjunction nod, prdcssor nods P i can b situatd on altrnativ input paths According to our modl, w assum that a procss, which is not a conjunction procss, can b activatd only aftr all its inputs hav arrivd A conjunction procss can b activatd aftr mssags coming on on of th altrnativ paths hav arrivd All procsss issu thir outputs whn thy trminat If w considr th activation tim of th sourc procss as a rfrnc, th activation tim of th sink procss is th dlay of th systm at a crtain xcution 3 Th Schdul Tabl For a givn xcution of th systm, a subst of th procsss is activatd which corrsponds to th actual path through th procss graph This path dpnds on crtain conditions For ach individual path thr is an optimal schdul of th procsss which producs a minimal dlay Lt us considr th procss graph in Fig1 If all thr conditions,, D, andkar tru, th optimal schdul rquirs P 1 to b activatd at tim t=0 on procssor p 1, and procssor p 2 to b kpt idl until t=4, in ordr to activat P 3 as soon as possibl (s Fig 4a) Howvr, if and D ar tru but K is fals, th optimal schdul rquirs to start both P 1

4 on p 1 and P 11 on p 2 at t=0; P 3 will b activatd in this cas at t=6, aftr P 11 has trminatd and, thus, p 2 bcoms fr (s Fig 4b) This xampl rvals on of th difficultis whn gnrating a schdul for a systm lik that in Fig 1 As th valus of th conditions ar unprdictabl, th dcision on which procss to activat on p 2 and at which tim, has to b takn without knowing which valus th conditions will latr gt On th othr sid, at a crtain momnt during xcution, whn th valus of som conditions ar alrady known, thy hav to b usd in ordr to tak th bst possibl dcisions on whn and which procss to activat An algorithm has to b dvlopd which producs a schdul of th procsss so that th worst cas dlay is as small as possibl Th output of this algorithm is a so calld schdul tabl In this tabl thr is on row for ach "ordinary" or communication procss, which contains activation tims for that procss corrsponding to diffrnt valus of th conditions Each column in th tabl is hadd by a logical xprssion constructd as a conjunction of condition valus Activation tims in a givn column rprsnt starting tims of th procsss whn th rspctiv xprssion is tru Tabl 1 shows part of th schdul tabl corrsponding to th systm dpictd in Fig 1 According to this schdul procsss P 1, P 2, P 11 as wll as th communication procss P 18 ar activatd unconditionally at th tims givn in th first column of th tabl No condition has yt bn dtrmind to slct btwn altrnativ schduls Procss P 14,onth othr hand, has to b activatd at t=24 if D K=tru and t=35 if D K=tru To dtrmin th worst cas dlay, δ max, w hav to obsrv th rows corrsponding to procsss P 10 and P 17 : δ max = max{34 + t 10,37+t 17 }=39 Th schdul tabl contains all information ndd by a distributd run tim schdulr to tak dcisions on activation of procsss W considr that during xcution a vry simpl non-prmptiv schdulr locatd on ach programmabl/ communication procssor dcids on procss and communication activation dpnding on actual valus of conditions Onc activatd, a procss xcuts until it complts To produc a dtrministic bhavior which is corrct for any combination of conditions, th tabl has to fulfill svral rquirmnts: 1 If for a crtain procss P i, with guard X Pi, thr xists an activation tim in th column hadd by xprssion E k,thn E k X Pi ; this mans that no procss will b activatd if th conditions rquird for its xcution ar not fulfilld 2 Activation tims hav to b uniquly dtrmind by th conditions Thus, if for a crtain procss P i thr ar svral altrnativ activation tims thn, for ach pair of such tims (τ Ej Pi, τ Ek Pi ) placd in columns hadd by xprssions E j and E k, E j E k =fals 3 If for a crtain xcution of th systm th guard X Pi bcoms tru thn P i has to b activatd during that xcution Thus, considring all xprssions E j corrsponding to columns which contain an activation tim for P i, E j =X Pi 4 Activation of a procss P i at a crtain tim t has to dpnd only on condition valus which ar dtrmind at th rspctiv momnt t and ar known to th procssing Tabl 1: Part of schdul tabl for th graph in Fig 1 tru D D D KD KD D KD KDD D P 1 0 P 2 3 P P 11 0 P P P P P lmnt M(P i ) which xcuts P i Th valu of a condition is dtrmind at th momnt τ at which th corrsponding disjunction procss trminats Thus, at any momnt t, t τ, th condition is availabl for schduling dcisions on th procssor which has xcutd th disjunction procss Howvr, in ordr to b availabl on any othr procssor, th valu has to arriv at that procssor Th schduling algorithm has to considr both th tim and th rsourc ndd for this communication Th following stratgy has bn adoptd for schduling th communication of conditions: aftr trmination of a disjunction procss th valu of th condition is broadcastd from th corrsponding procssor to all othr procssors; this broadcast is schduld as soon as possibl on th first bus which bcoms availabl aftr trmination of th disjunction procss For this task only busss ar considrd to which all procssors ar connctd and w assum that at last on such bus xists 1 Thtimτ 0 ndd for this communication is th sam for all conditions and dpnds on th faturs of th mployd buss Givn th minimal amount of transfrrd information, th tim τ 0 is smallr than (at most qual to) any othr communication tim Th transmittd condition is availabl for schduling dcisions on all othr procssors τ 0 tim units aftr initiation of th broadcast For th xampl givn in Tabl 1 communication tim for conditions has bn considrd τ 0 =1 Th last thr rows in Tabl 1 indicat th schdul for communication of conditions, D, andk 4 Th Schduling Stratgy D K Our goal is to driv a minimal worst cas dlay and to gnrat th corrsponding schdul tabl for a procss graph Γ(V, E S, E ), a mapping function M: V PE,andxcution tims t Pi for ach procss P i V At a crtain 1 This assumption is mad for simplification of th furthr discussion If no bus is connctd to all procssors, communication tasks hav to b schduld on svral busss according to th actual intrconnction topology

5 xcution of th systm, on of th N alt altrnativ paths through th procss graph will b xcutd Each altrnativ path corrsponds to on subgraph G k Γ, k=1, 2,, N alt For ach subgraph thr is an associatd logical xprssion L k (th labl of th path) which rprsnts th ncssary conditions for that subgraph to b xcutd If at activation of th systm all th conditions would b known, th procsss could b xcutd according to th (nar)optimal schdul of th corrsponding subgraph G k Undr ths circumstancs th worst cas dlay δ max would b δ max = δ M,with δ M =max{δ k,k=1,2,,n alt }, whr δ k is th dlay corrsponding to subgraph G k Howvr, this is not th cas as w do not assum any prdiction of th conditions at th start of th systm Thus, what w can say is only that 1 : δ max δ M A schduling huristic has to produc a schdul tabl for which th diffrnc δ max δ M is minimizd This mans that th prturbation of th individual schduls, introducd by th fact that th actual path is not known in advanc, should b as small as possibl W hav dvlopd a huristic which, starting from th schduls corrsponding to th altrnativ paths, producs th global schdul tabl, as rsult of a, so calld, schdul mrging opration Hnc, w prform schduling of a procss graph as a succssion of th following two stps: 1 Schduling of ach individual altrnativ path; 2 Mrging of th individual schduls and gnration of th schdul tabl W prsnt algorithms for schduling of th individual paths in [5] In this papr w concntrat on th gnration mchanism of th global schdul tabl 5 Th Tabl Gnration Algorithm Th input for th gnration of th schdul tabl is a st of N alt schduls, ach corrsponding to an altrnativ path, labld L k, through th procss graph Γ Each such schdul consists of a st of pairs (P i, τ Lk Pi ), whr P i is a procss activatd on path L k and τ Lk Pi is th start tim of procss P i according to th rspctiv schdul Th schdul tabl gnratd as output fulfills th rquirmnts prsntd in sction 3 Th schdul mrging algorithm is guidd by th lngth of th schduls producd for ach altrnativ path Whil progrssivly constructing th schdul tabl, at ach momnt, priority is givn to th rquirmnts of th schdul corrsponding to that path, among thos which ar still rachabl, that producs th largst dlay Thus, w induc prturbations into th short dlay paths and lt th long ons procd as similar as possibl to thir (nar)optimal schdul 5 1 Schdul Mrging Th gnration algorithm of th schdul tabl procds 1 This formula to b rigorously corrct, δ M has to b th maximum of th optimal dlays for ach subgraph along a binary dcision tr corrsponding to all altrnativ paths, which is xplord in a dpth first ordr Fig 2 shows th dcision tr xplord during gnration of Tabl 1 Th nods of th dcision tr corrspond to th stats rachd whn, according to th actual schdul, a disjunction procss has bn trminatd and th valu of a nw condition has bn computd Th algorithm is guidd by th following basic ruls: 1 Start tims of procsss ar fixd in th tabl according, with priority, to th schdul of that path which is rachabl from th currnt stat and producs th longst dlay 2 Th start tim τ Lk Pi of a procss P i is placd in a column hadd by th conjunction of all condition valus known at τ Lk Pi on th procssing lmnt M(P i ), according to th currnt schdul If such a column dos not yt xist in th tabl, it will b gnratd 3 Aftr a nw path has bn slctd, its schdul will b adjustd by nforcing th start tims of crtain procsss according to thir prviously fixd valus This can b th cas of a procss P i which is part of th currnt path lablld L k (L k X Pi ), and of a prviously handld path lablld L q (L q X Pi ) Whn handling path L q an activation tim for procss P i has bn fixd in a column hadd by xprssion EIfEdpnds xclusivly on conditions corrsponding to tr nods which ar prdcssors of th branching nod btwn th two paths, thn th schdul of th currnt path, L k, has to b adjustd by taking into considration th prviously fixd activation tim of P i 4 Furthr radjustmnts of th currnt schdul ar prformd in ordr to avoid violation of rquirmnt 2 in sction 3 This aspct will b discussd in subsction 52 At th bginning, start tims of procsss ar placd into Tabl 1 according to th schdul which corrsponds to th path labld D K Aftr th first back-stp, to nod K (Fig 2), th schdul corrsponding to path D K bcoms th actual on Nw start tims will b fixd into th schdul tabl according to an adjustd vrsion of this schdul Th nxt back-stp is to nod Two schduls ar now rachabl taking th branch, which ar lablld D K and D K rspctivly D K, which producs a largr dlay, will b slctd first as th actual schdul It will b followd until th nxt bck-stp has bn prformd Th algorithm for gnration of th schdul tabl is brifly dscribd, as a rcursiv procdur, in Fig 3 An ssntial aspct of this algorithm is that, aftr ach back-stp, a nw schdul has to b slctd as th currnt on Th slction rul givs priority to th path with th largst dlay, among thos which ar rachabl from th currnt nod in th dcision tr Furthr start tims of procsss will b K K Lngth of th optimal schdul for th altrnativ paths through th graph in Fig 1 K D K 39 D D K K D 39 tru D K 38 K D D K 32 D K 31 D 31 Fig 2 Dcision tr xplord for th graph in Fig 1

6 BuildSchdulTabl(currnt_schdul, back_stp) if back_stp thn Slct nw currnt_schdul Adjust currnt_schdul hck for conflicts and radjust currnt_schdul nd if whil not (EndOfSchdul or arrivd at momnt so that a disjunction procss is trminatd) do Tak following procss in currnt_schdul and plac start tim into SchdulTabl nd whil if EndOfSchdul thn rturn nd if BuildSchdulTabl(currnt_schdul, fals) BuildSchdulTabl(currnt_schdul, tru) nd BuildSchdulTabl Fig 3 Algorithm for gnration of a schdul tabl placd into th schdul tabl according to an adjustd vrsion of th nw currnt schdul Procsss which satisfy th condition of rul thr prsntd abov hav to b movd to thir prviously fixd start tim Thy ar considrd as lockd in this nw position As rsult of a simpl rschduling procdur th start tims of th othr, unlockd, procsss ar changd to th arlist momnt which is allowd, taking in considration data dpndncis Rlativ prioritis of unlockd procsss assignd to th sam non-hardwar procssor ar kpt as in th original schdul In Fig 4 w show th adjustmnt of th schdul lablld D K prformd aftr th back-stp to nod K Atthis momnt start tims of procsss P 1, P 2, P 11, P 3, P 12, P 18, P 27, and of th communication procsss for conditions D,, andkhav alrady bn placd in th tabl according to thschdulofpathd Kwhich is shown in Fig 4b Th activation tim of ths procsss has bn placd in columns hadd by xprssions tru, or D, and consquntly thy ar mandatory also for path D K (both nod and D ar prdcssors of nod K which is th branching nod btwn th two paths) Undr ths circumstancs som of th othr procsss hav to b movd from thir original position in this schdul, shown in Fig 4a, to thir position in th adjustd schdul of Fig 4c This adjustd vrsion is usd in ordr to fix start tims of furthr procsss until th nxt back-stp 5 2 onflict Handling at Tabl Gnration Suppos w ar currntly handling a path lablld L k According to th adjustd schdul of this path w plac an activation tim τ Lk Pi of procss P i into th tabl, so that th rspctiv column is hadd by an xprssion E Th problm is how to prsrv th cohrnc of th tabl in th sns introducd by rquirmnt 2 dfind in sction 3 If thr is no activation tim prviously introducd in th row corrsponding to P i no conflicts can b gnratd If, howvr, th rspctiv row contains activation tims, thr xists a potntial of conflict btwn th column hadd by E and columns which alrady includ activation tims of P i Lt us considr that such a column is hadd by an xprssion F According to rquirmnt 2, w hav a conflict btwn columns E and F if thr xists no condition so that E=q and F=q' Intuitivly, such a conflict mans that for two or mor paths th sam procss P i is schduld at diffrnt tims but th conditions known on th procssing lmnt M(P i ) do not allow to th schdulr to idntify th currnt path and to tak a dtrministic dcision on activation of P i If placmnt of an activation tim for procss P i in a column hadd by xprssion E producs a conflict, th currnt schdul has to b radjustd so that an xprssion E' will had th column that hosts th nw activation tim of P i and no conflict is inducd in th schdul tabl As shown in th algorithm prsntd in Fig 3, aftr adjustmnt of a schdul, unlockd procsss ar chckd if thir placmnt in th tabl producs any conflicts If this is th cas, th pro- Tim Procssor p 1 Procssor p AAAA A AAAA P1AAAA AAAA AAAA P2 AA AAAA AAAA P6 P9 AAAA AAAA P10 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA P3 P11 AAAA P14AA P17 Procssor p 3 (hardwar) P12 P8 P16 Bus p 4 P18 AAAA AA AAAA P21 AAAA P20AA D P27 AAAP23 KAAAA P25AAP28AAAA P31AA a) Optimal schdul of th path corrsponding to D K Procssor p 1 Procssor p 2 Procssor p 3 (hardwar) Bus p 4 AAAA A AAAA P1AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA P2 AA AAAA AAAA P6 P9 P10 A P11 P18 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA P3 D P27 P12 K P16 AA AAAA AAAA P15A P17 P8 AAAA P21 AA AAAA P29 AAAA AAAA P31 AA AAAA P23 AAAA AAAA P20 AA b) Optimal schdul of th path corrsponding to D K AAAA P25 AA Procssor p 1 AAAA A AAAA P1AAAA AAAA AAAA P2 AA AAAA AAAA P6 P9 AAAA AAAA P10 Procssor p 2 P11 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA P3 AAA P14AA P17 Procssor p 3 (hardwar) Bus p 4 P12 P16 AAAA AAAA AAAA AAAA P18 D P27 K AAAA P21AA AAAA P20AA AAAA P23 AAAA AAAA P25AAP28 AAA P31AA c) Adjustd schdul of th path corrsponding to D K Fig 4 Optimal and adjustd schduls for paths xtractd from th procss graph in Fig 1 P8

7 ) s ( m i t n o i t u c x E ) % ( v o s a r c n I M css will b movd to a nw activation tim and th schdul is radjustd by changing th start tim of som unlockd procsss (similar to th opration prformd at th initial adjustmnt) Th main problm which has to b solvd is to find th nw activation tim for P i so that conflicts ar avoidd In [5] w dmonstratd th following two thorms in th contxt of our tabl gnration algorithm: Thorm 1 onsidr a procss P i which is part of two paths, L k and L q, with activation tims τ Lk Pi and τ Lq Pi rspctivly If th st of prdcssors of P i is diffrnt in th two paths, thn no conflict is possibl btwn th columns corrsponding to th two activation tims As a consqunc of this thorm radjustmnts for conflict handling can not impos an activation tim of a procss which is not fasibl for th rspctiv path Thorm 2 onsidr a procss P i so that placmnt of its activation tim τ L Pi, corrsponding to th currnt path L, into th schdul tabl producs a conflict Thr xists an activation tim τ' of P i, corrsponding to on of th prviously handld paths with which th currnt on is in conflict, so that τ' has th following proprty: if P i is movd to activation tim τ' in th currnt schdul, all conflicts ar avoidd onsidr W th st of columns with which thr xists a conflict at placmnt of th activation tim for P i Basd on Thorm 2 w know that on of th tims τ F Pi placd in a column F W, rprsnts a corrct solution for conflict limination Thus, th following loop ovr th st W can produc th nw activation tim of a procss P i so that all conflicts ar avoidd: for all columns F W do if moving P i to τ F Pi all conflicts ar avoidd thn nd if nd for F rturn τ Pi 6 Exprimntal Evaluation Th stratgy w hav prsntd for gnration of th schdul tabl guarants that th path corrsponding to th largst dlay, δ M, will b xcutd in xactly δ M tim This, howvr, dos not man that th worst cas dlay δ max,corrsponding to th gnratd global schdul, is always guarantd to b δ M Such a dlay can not b guarantd in thory According to our schduling stratgy δ max will b wors than δ M if th schdul corrsponding to an initially fastr path is disturbd at adjustmnt or conflict handling so that its dlay bcoms largr than δ M For valuation of th schdul mrging algorithm w usd 1080 conditional procss graphs gnratd for xprimntal purpos 360 graphs hav bn gnratd for ach dimnsion of 60, 80, and 120 nods Th numbr of altrnativ paths through th graphs is 10, 12, 18, 24, or 32 Excution tims wr assignd randomly using both uniform and xponntial distribution W considrd architcturs consisting of rδ fδ o x a m nods 2 80 nods 1 60 nods Numbr of mrgd schduls Fig5Incras of th worst cas dlay nods 80 nods 60 nods Numbr of mrgd schduls Fig 6: Excution tim for schdul mrging on ASI and on to lvn procssors and on to ight busss [5] Exprimnts wr run on a SPARstation 20 Fig 5 prsnts th prcntag incras of th worst cas dlay δ max ovr th dlay δ M of th longst path Th avrag incras is btwn 01% and 763% and, practically, it dos not dpnd on th dimnsion of th graph but only on th numbr of mrgd schduls It is worth to b mntiond that a zro incras (δ max =δ M ) was producd for 90% of th graphs with 10 altrnativ paths, 82% with 12 paths, 57% with 18 paths, 46% with 24 paths, and 33% with 32 paths In Fig 6 w show th avrag xcution tim for th schdul mrging algorithm, as a function of th numbr of mrgd schduls Th tim ndd for schduling of th individual paths dpnds on th mployd algorithm As dmonstratd in [5], good quality rsults can b obtaind with a list schduling basd algorithm which nds lss than 0003 sconds for graphs having 120 nods Finally, w prsnt a ral-lif xampl which implmnts th opration and maintnanc (OAM) functions corrsponding to th F4 lvl of th ATM protocol layr [1] Fig 7a shows an abstract modl of th ATM switch Through th switching ntwork clls ar routd btwn th n input and q output lins In addition, th ATM switch also prforms svral OAM rlatd tasks In [4] w discussd hardwar/softwar partitioning of th OAM functions corrsponding to th F4 lvl W concludd that filtring of th input clls and rdircting of th OAM clls towards th OAM block hav to b prformd in hardwar as part of th lin intrfacs (LI) Th othr functions ar prformd by th OAM block and can b implmntd in softwar W hav idntifid thr indpndnt mods in th functionality of th OAM block Dpnding on th contnt of th input buffrs (Fig 7b), th OAM block switchs btwn ths thr mods Excution in ach mod is controlld by a

8 i 1 i 2 LI LI o 1 o 2 (to sw ntw) OAM clls to Managmnt Systm i n LI Procssor OAM from/to Phys Layr& block Managmnt Syst a) ATM switch Fig 7 ATM switch with OAM block b) OAM block statically gnratd schdul tabl for th rspctiv mod W spcifid th functionality corrsponding to ach mod as a st of intracting VHDL procsss Tabl 2 shows th charactristics of th rsulting procss graphs Th main objctiv of this xprimnt was to stimat th worst cas dlays in ach mod for diffrnt altrnativ architcturs of th OAM block Basd on ths stimations as wll as on th particular faturs of th nvironmnt in which th switch will b usd, an appropriat architctur can b slctd and th dimnsions of th buffrs can b dtrmind Fig 7b shows a possibl implmntation architctur of th OAM block, using on procssor and on mmory modul (1P/1M) Our xprimnts includd also architctur modls with two procssors and on mmory modul (2P/1M), as wll as structurs consisting of on rspctivly two procssors and two mmory moduls (1P/2M, 2P/2M) Th targt architcturs ar basd on two typs of procssors: 486DX2/ 80MHz and Pntium/120MHz For ach architctur, procsss hav bn assignd to procssors taking into considration th potntial paralllism of th procss graphs and th amount of communication btwn procsss Th worst cas dlays rsulting aftr gnration of th schdul tabl for ach of th thr mods, ar givn in Tabl 2 As xpctd, using a fastr procssor rducs th dlay in ach of th thr mods Introducing an additional procssor, howvr, has no ffct on th xcution dlay in mod 2 which dos not prsnt any potntial paralllism In mod 3 th dlay is rducd by using two 486 procssors instad of on For th Pntium procssor, howvr, th worst cas dlay can not b improvd by introducing an additional procssor Using two procssors will always improv th worst cas dlay in mod 1 As for th additional mmory modul, only in mod 1 th modl contains mmory accsss which ar potntially xcutd in paralll Tabl 2 shows that only for th architctur consisting of two Pntium procssors providing an additional mmory modul pays back by a rduction of th worst cas dlay in mod 1 Tabl 2: Worst cas dlays for th OAM block Modl Worst cas dlay (ns) mo 1P/1M 1P/2M 2P/1M 2P/2M d nr nr proc paths 486 Pnt 486 Pnt 486 Pnt Pnt 486 Pnt Pnt o q OAM clls (from LIs) 7 onclusions W hav prsntd an approach to procss schduling for th synthsis of mbddd systms Th approach is basd on an abstract graph rprsntation which capturs, at procss lvl, both dataflow and th flow of control A schdul tabl is gnratd by a mrging opration prformd on th schduls of th altrnativ paths Th main problms which hav bn solvd in this contxt ar th minimization of th worst cas dlay and th gnration of a logically and tmporally dtrministic tabl, taking into considration communication tims and th sharing of th busss Th algorithms hav bn valuatd basd on xprimnts using a larg numbr of graphs gnratd for xprimntal purpos as wll as ral-lif xampls Rfrncs from Phys Layr& Managmnt Syst Mmory [1] TM hn, SS Liu, ATM Switching Systms, ArtchHous Books, 1995 [2] P hou, G Borillo, Intrval Schduling: Fin-Graind od Schduling for Embddd Systms, Proc AM/IEEE DA, 1995, [3] EG offman Jr, RL Graham, "Optimal Schduling for two Procssor Systms", Acta Informatica, 1, 1972, [4] P Els, Z Png, K Kuchcinski, A Doboli, Systm Lvl Hardwar/Softwar Partitioning Basd on Simulatd Annaling and Tabu Sarch, Ds Aut for Emb Syst, V2, N1, 1997, 5-32 [5] P Els, K Kuchcinski, Z Png, A Doboli, P Pop, Procss Schduling for Prformanc Estimation and Synthsis of Embddd Systms, Rsarch Rport, Dpartmnt of omputr and Information Scinc, Linköping Univrsity, 1997 [6] R K Gupta, G D Michli, A o-synthsis Approach to Embddd Systm Dsign Automation, Ds Aut for Emb Syst, V1, N1/2, 1996, [7] H Kasahara, S Narita, "Practical Multiprocssor Schduling Algorithms for Efficint Paralll Procssing", IEEE Trans on omp, V33, N11, 1984, [8] K Kuchcinski, "Embddd Systm Synthsis by Timing onstraint Solving", Proc Int Symp on Syst Synth, 1997 [9] YK Kwok, I Ahmad, "Dynamic ritical-path Schduling: an Effctiv Tchniqu for Allocating Task Graphs to Multiprocssors", IEEE Trans on Par & Distr Syst, V7, N5, 1996, [10] Y S Li, S Malik, Prformanc Analysis of Embddd Softwar Using Implicit Path Enumration, Proc AM/IEEE Dsign Automation onfrnc, 1995, [11] S Prakash, A Parkr, SOS: Synthsis of Application-Spcific Htrognous Multiprocssor Systms, Journal of Paralll and Distrib omp, V16, 1992, [12] K Suzuki, A Sangiovanni-Vincntlli, Efficint Softwar Prformanc Estimation Mthods for Hardwar/Softwar odsign, Proc AM/IEEE DA, 96, [13] JD Ullman, "NP-omplt Schduling Problms", Journal of omput Syst Sci, 10, , 1975 [14] T Y Yn, W Wolf, Hardwar-Softwar o-synthsis of Distributd Embddd Systms, Kluwr Acadmic Publishr, 1997