Automata for Real-time Systems
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1 1/26 Automata for Real-time Systems B. Srivathsan Chennai Mathematical Institute
2 2/26 In this lecture An academic case-study that investigates methods to build more reliable pacemakers
3 3/26 Lecture 10: Towards reliable pacemakers
4 4/26 References Modeling and verification of a dual chamber implantable pacemaker Jiang, Pajic, Moarref, Alur, Mangharam. TACAS 12 Heart-on-a-chip: A closed-loop testing platform for implantable pacemakers Jiang, Radhakrishnan, Sampath, Sarode, Mangharam mlab.seas.upenn.edu
5 5/26 Heart and pacemaker basics Presentation of Zhihao Jiang (U Penn)
6 6/26 Pacemaker software In-built algorithms to detect and terminate various abnormal heart conditions
7 6/26 Pacemaker software In-built algorithms to detect and terminate various abnormal heart conditions At least 6 implanted medical devices were recalled in 2010 due to likely software defects Killed by Code: Software Transparency in Implantable Medical Devices Karen Sandler, Lysandra Ohrstrom, Laura Moy, Robert McVay
8 7/26 Two possible solutions for more reliable devices: Model-based system/software design Closed-loop testing
9 Model-based system/software design UPPAAL Heart automaton Pacemaker automaton Verification UPP2SF tool Simulink Simulink model Simulink model Simulation Code generation Testbench Heart on chip Pacemaker Conformance testing (Simulink is a commercial tool developed by Mathworks Inc.) 8/26
10 rdinates the conlation within our n and conduction n abnormal heart Rhythm managecemaker, are degnose the current apies to maintain etween the pacem a perfect examhe device opera- ated. This end-to-end tool chain guarantees the verified properties are preserved during model translation and code generation which can save significant debugging time. Closed-loop testing Boston Scientific Pacemaker Heart on FPGA iac devices were th consequences ice software, rehave been rising. A) require device the NSF CPS- Analog Interface Figure 1: The heart-on-a-chip testing platform consists of a heart im- plementation on an programmable chip (FPGA) and an analog interface for signal isolation and attenuation to interface with a pacemaker. Heart on Conformance In this figure, the platform is testing apacemaker Boston Scientific pacemaker. Testbench chip testing 9/26
11 Coming next: Modeling and verification of heart and pacemaker 10/26
12 Heart as a timed automaton 11/26
13 12/26 Abstract electrical conduction system of heart into nodes and paths Picture credits: A Simulink hybrid heart model for quantitative verification of cardiac pacemakers Chen et. al. HSCC 13
14 Time Zhihao Jiang et al.: Pacemaker Verification Time 7 ERP RRP ERP RRP ERP RRP ERP RRP Refractory Cond Cond Vout Original Originaltissue tissuemodel Model a t<=trest_max t<=trest_max bb t>trrp_min t>trrp_min Time RRP RRP ERP t<=trrp_max RRP ERPt<=Trrp_max RRP t>trest_min t>trest_min Act_node? Act_node? Act_node? Act_node? t>terp_min t>terp_min b t>trest_min Abstraction Abstraction11 t>trest_min t<=trest_max t>trrp_min t<=trest_max RRP t<=trest_max t<=trrp_max cond cond t<=tcond_max t<=tcond_max t>tcond_min t>tcond_min Act_next! Act_next! ERP ERP t<=terp_max t<=terp_max N0 N0 Cond Original tissue Model N0 N0 Act_node? Act_node? t>trest_min Act_node? t>terp_min Act_node? Act_node? N0 Act_node? N0 Act_path_1? Idle Act_path_2? Act_path_1? Idle Act_path_2? t1=0 t2=0 t1=0 t2=0 cond t<=tcond_max t>tcond_min temp Act_next! temp ERP t<=terp_max N1 N1 t>1 t>1t<=1 Conflict Conflict t2>tcond_min t<=1 Retro t1>tcond_min t1>tcond_min t2>tcond_min Retro t>trrp_min Act_node_2! Act_node_1! Act_path! t>trrp_min Act_node_2! Act_node_1! Act_path! t2<=tcond_max t1<=tcond_max Act_path_1? Idle Act_path_2? P1 Abstraction 1 t2<=tcond_max t1<=tcond_max N1 t>trest_min t1=0erp t2=0 t1+t2>tcond_min RRP t1+t2>tcond_min RRP temp t>terp_min ERP t>terp_min t>1 t<=trest_max t<=trrp_max Act_node? Act_node_2? Act_node_1? t<=terp_max Conflict t<=1 Ante Act_node_2? Act_node_1? t<=trrp_max t<=terp_max t1>tcond_min t2>tcond_min Retro Double t1+t2<=tcond_max Act_node? t>trrp_min Double t1+t2<=tcond_max Act_node_2! Act_node_1! Act_path! cc c RRP t>terp_min ERP Abstraction 22 Abstraction N1 t<=trrp_max N1 Node N1 t<=terp_max Ante Ante t1<=tcond_max t1+t2>tcond_min Act_node_2? Double t2<=tcond_max Act_node_1? t1+t2<=tcond_max Act_path_1? P1 Path P1 Act_path_2? Act_path_1? Act_path_2? t>trest_min Trrp_min, P1 acc. to node Parameters Trest_max, t>trest_minetc. chosen placement and patient history t<=trest_max Ante Retro Idle Ante Act_path_2? Retro Idle Abstraction 2 t<=trest_max Act_path_1? 13/26
15 14/26 Heart automaton H: N 1 P 1 N 2 P 2... N k N i P i Node automaton Path automaton k Number of nodes to which heart is abstracted Parallel composition (asynchronous product construction)
16 Pacemaker as a timed automaton 15/26
17 16/26 Heart-pacemaker interaction Aget! Heart AP! Vget! Pacemaker VP! N 1. Act_Path! Aget! N 2. Act_Path! Vget N 1 node at atrial lead N 2 node at ventricular lead
18 17/26 Pacemaker timing cycles 1 2 3
19 18/26 AS? VS? VP? LRI AP! AS? VS? VP? AVI VP! VS? VP? URI (a) LRI component (b) AVI component (c) URI component Aget? VS? VP? PVARP AS! AR! Vget? VP? VRP VS! (d) PVARP component (e) VRP component Pacemaker automaton P: LRI AVI URI PVARP VRP
20 Heart-pacemaker automaton: H P 19/26
21 An algorithm for Endless Loop Tachycardia 20/26
22 21/26 Endless Loop Tachycardia (ELT) Slides of Zhihao Jiang
23 22/26 ELT-detection: If VP-AS pattern within 500ms for at least 8 times ELT-termination: Increase PVARP to 500ms once VPAS 2 ELTct 3 PVARP Pacemaker P 1 : LRI AVI URI PVARP VRP ELTct VPAS
24 23/26 Is the modified pacemaker safe? Question 1: Are 2 ventricular events within time? wait_1st Vget? Vget? wait_2nd VP? VP? (a) Monitor PLRI test secv Check in UPPAAL if in H P 1 PLRItest, all paths satisfy PLRItest.t TLRI
25 24/26 Is the modified pacemaker safe? Question 2: Are 2 ventricular events very fast? wait_v VP? wait_vp VP? secv Vget? Vget? (b) Monitor PURI test Check in UPPAAL if in H P 1 PURItest, all paths satisfy PURItest.t TURI
26 Each time new algorithm is added, model it and check if basic safety properties are satisfied 25/26
27 26/26 Take-home Model-based system/software design Closed-loop testing
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