Computer Architecture ELEC2401 & ELEC3441

Transcription

1 Last Time Pipeline Computer Architecture ELEC2401 & ELEC3441 Lecture 6 Pipelining (2) Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Structural Control n On every cycle, the hardre needs to detect and resolve all types of hazards, while keeping pipeline as filled as possible to achieve CPI=1 In real systems, CPI suffers slightly in return for higher clock speed n Need to make sure hardre adheres to the ISA contract with the programmer difficult but worth it 2 Control n Control hazards occur as a result of branches and jumps next instruction not necessarily at +4 n Unconditional jumps: Next instruction is determined by the jump instruction n Conditional branches: Next instruction depends on result of branch comparison n Possible solutions: Stall Change ISA (forrd) Speculation n Important questions to ask yourself: When do know the ess of next instruction to execute? What happen to the instructions in the rest of the pipeline? 3 4

2 Pipelining Branches F D E M W Sel inst correct target depending on Bcomp Calc target Take branch? Challenge: Does not know target ess until EX stage 5 Not so good solution Stalling (I 3 ) 104: ADD (I 4 ) 108: ADD (I 5 ) 300: SUB IF 5 ID 5 EX 5 MA 5 WB 5 n Stalling: Wait 2 cycles Fetch the correct target after ess calculation is completed in EX stage n Stalling doesn t quite work: The hardre doesn t know it is a branch instruction until ID stage è What should happen at t2? Huge performance penalty if hardre alys stall 2 cycles regardless of instruction è 3x cycle 6 Solution 1: Change ISA n Expose the fact that there is pipeline in hardre n Change ISA: The 2 instructions following branch will ALWAYS be executed regardless of the branch comparison result n The extra cycle when an instruction is alys executed regardless of the comparison result is called a branch delay slot n Compiler may insert useful instructions in the branch delay slot or NOPs e.g. instruction that may be executed regardless of the branch target Branch Delay Slot Example addi x2, x1, 4! lw x4, 16(x2)! beq x1, x0, err! ok: add x5, x3, x4! ori x6, x0, 23!! err: sub x5, x3, x4! Original n ructions in delay slot must not affect the branch decision e.g. in above: they cannot modify x1 n Is the value of x4 ok? beq x1, x0, err! addi x2, x1, 4! lw x4, 16(x2)! ok: add x5, x3, x4! ori x6, x0, 23!! err: sub x5, x3, x4! Rearranged delay slot 7 8

3 Real Processor: MIPS-I n The first generation of MIPS processor has 1 delay slot defined n Brach decision is moved to ID stage Only support very simple branch: beqz on 1 register n Compiler must find instruction to fill the delay slot or put NOP Microprocessor without Interlocked Pipeline Stages Solution 2: Speculate + Kill n Step 1: Speculate that the instruction in delay slots will be executed. n Step 2: Determine at EX stage: if branch taken, then kill the instructions in IF and ID stage if branch not taken, then do nothing n Pro: Waste cycles only in cases when branch taken n Cons: complicate hardre interact with stall Branch/Jump in delay slots? 9 Killing instructions in IF, ID Branch taken (I 3 ) 104: ADD IF 3 ID (I 4 ) 108: ADD IF (I 5 ) 300: SUB IF 5 ID 5 EX 5 MA 5 WB 5 Kill instructions in pipeline Branch not taken ructions continue (I 3 ) 104: ADD IF 3 ID 3 EX 3 MA 3 WB 3 (I 4 ) 108: ADD IF 4 ID 4 EX 4 MA 4 WB new 4 (I 5 ) 112: SLL IF 5 ID 5 EX 5 MA 5 WB instruction Killing ructions F Sel D kill E M W inst Mem bubble kill correct target depending on Bcomp bubble Calc target Take branch? Note: kill signal stall signal as instruction in ID is invalid 12

4 Pipelining Jumps (JAL) n Unconditional jumps can be implemented similar to branches with the branch condition being alys true n JAL has additional requirements for storing return ess (+4) in the destination register rd Proceed until WB stage to write back data in register file Need to be careful with data forrding and stalling on rd n Alys kill instructions after JAL Pipelining JAL F Sel D kill E M W inst Mem bubble kill brjmp bubble Calc target Save +4 from JAL instruction Branch Delay Slots n Post 1990s processors rarely has branch delay slot n Performance: I-cache miss at delay slot causes significant performance penalty n Delay slot complicates advanced microarchitectures e.g. super scalar processors with multiple instructions issued per cycles n Difficult to find instructions to fill deeply pipelined processors Modern processors can have up to 30 pipeline stages n Other techniques helpful branch prediction, predicated instructions, etc In Conclusions n Control s are caused by branch and jump instructions Branch/jump destination is unknown until later stages n To solve ess control hazards: Stall Expose branch delay slots to softre Do nothing (speculate branch not taken) and kill instructions if needed n itional considerations with and data forrding 15 16

5 Acknowledgements n These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) n MIT material derived from course n UCB material derived from course CS152, CS252 17