MultiCycle MIPS. Motivation

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1 lticycle IPS otivation New path von Nemann instrction cycle Revisiting instrctions State diagram of processor Galen Sasaki EE 6 University of Hawaii otivation Instrctions take variable amont of processing, and variable time add $,$,$:. get instr. (fetch from RO). fetch $ and $ from reg. file. add. write sm into $ in reg. file lw $,($). get instr.. fetch $ from reg file. add and reg vale. read from 5. write into $ in reg file Galen Sasaki EE 6 University of Hawaii

2 add $,$,$ issing: pdating PC Instrction [5 ] Jmp address [ ] 6 8 PC+ [ 8] reslt RegDst Jmp Branch PC address Instrction [ ] Instrction. Fetch Instrction Instrction [ 6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction [5 ] Control Decode. to reg file em emtoreg Op em Src Reg Registers Instrction [5 ]. Get reg vales, decode instrction $ $ $ 6 Sign etend control Zero reslt. ress Data Galen Sasaki EE 6 University of Hawaii lw $,($) issing: pdating PC Instrction [5 ] Jmp address [ ] 6 8 PC+ [ 8] reslt RegDst Jmp Branch PC address Instrction [ ] Instrction. Fetch Instrction Instrction [ 6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction [5 ] Control Decode 5. to reg file em emtoreg Op em Src Reg Registers Instrction [5 ]. Get reg vales, decode instrction $ $ 6 Sign etend control Zero reslt.. ress Data Galen Sasaki EE 6 University of Hawaii

3 otivation Ideally, we want a processor that adjsts its clock period with the instrction it s eecting. Hard to bild. Alternative: make clock faster allow instrctions to take more than one clock period, and vary with instr. each clock period allows one fndamental step of processing step step step step step step step step step 5 add $,$,$ lw $,const($) Galen Sasaki EE 6 University of Hawaii 5 lw $,($) issing: pdating PC Instrction [5 ] Jmp address [ ] 6 8 PC+ [ 8] reslt RegDst Jmp Branch PC address Instrction [ ] Instrction. Fetch Instrction Register Instrction [ 6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction [5 ] Control Decode 5. to reg file em emtoreg Op em Src Reg Registers Instrction [5 ]. Get reg vales, decode instrction $ $ 6 Sign etend control Zero reslt.. ress Data Galen Sasaki EE 6 University of Hawaii 6

4 lti-cycle IPS PCCond PCSorce PC IorD em em emtoreg Otpts Control Op SrcB SrcA Reg PC ress emory emdata Instrction [-6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction Instrction [5 ] emory IR Instrction [5 ] Op [5 ] Instrction [5 ] RegDst 6 Registers Sign etend A B 6 8 control PC [-8] Zero reslt Jmp address [-] Ot Instrction [5 ] Galen Sasaki EE 6 University of Hawaii 7 lti-cycle IPS PCCond PCSorce PC IorD em em emtoreg Otpts Control Op SrcB SrcA Reg PC ress emory emdata One emory Instrction [-6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction Instrction [5 ] emory IR Instrction [5 ] Op [5 ] Instrction [5 ] RegDst 6 Registers Sign etend A B 6 8 control PC [-8] Zero reslt Jmp address [-] Ot One Instrction [5 ] Galen Sasaki EE 6 University of Hawaii 8

5 New Datapath itional s to hold intermediate reslts IR: instrction A,B: inpts to Ot: DR: emory Data Register does more work -- all of the adding more mltipleers at its inpts Only one for and program Galen Sasaki EE 6 University of Hawaii 9 What does the processor do? Designing the controller von Nemann instrction cycle fetch instr. decode instr. opcode Galen Sasaki EE 6 University of Hawaii

6 The instrctions R-type: e. add $,$,$ sw: e. sw $,($) lw: e. lw $,($) beq: e. beq $,$,offset j: e. j addr Galen Sasaki EE 6 University of Hawaii State Diagram -- sort of Step fetch instr Step decode instr. 5 opcode Step Step R-type lw sw beq j Step 5 Galen Sasaki EE 6 University of Hawaii

7 lti-cycle IPS PCCond PCSorce PC IorD em em emtoreg Otpts Control Op SrcB SrcA Reg PC ress emory emdata Step. IR = emory[pc] PC = PC + Instrction [-6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction Instrction [5 ] emory IR Instrction [5 ] Op [5 ] Instrction [5 ] RegDst 6 Registers Sign etend A B 6 8 control PC [-8] Zero reslt Jmp address [-] Ot Instrction [5 ] Galen Sasaki EE 6 University of Hawaii lti-cycle IPS PC ress emory emdata Step. IR = emory[pc] PC = PC + Instrction [-6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction Instrction [5 ] emory PCCond PC IorD Otpts em em Control emtoreg IR Instrction [5 ] Op [5 ] Instrction [5 ] PCSorce Op SrcB SrcA RegDst 6 Reg Registers Sign etend Instrction [5 ] A B 6 8 control PC [-8] Zero reslt Jmp address [-] Ot. Instrction decode Register fetch Compte branch target address (e.g., beq) Galen Sasaki EE 6 University of Hawaii

8 Step. Instrction Fetch IR = emory[pc] PC = PC+ Steps and Step. Instrction decode (and fetch) A = Reg[IR[5-]] B = Reg[IR[-6]] Ot = PC + (sign-etend (IR[5-] << ) (Comment: compting target address for branching) Galen Sasaki EE 6 University of Hawaii 5 R-Type, sw, lw R-Type Step. Ot= A op B Step. Reg[IR[5-]] = Ot sw Step. Ot = A + sign-etend(ir[5-]) Step. emory[ot] = B lw Step. Ot = A + sign-etend(ir[5-]) Step. DR = emory[ot] Step 5. Reg[IR[-6]] = DR same Galen Sasaki EE 6 University of Hawaii 6

9 State Diagram instr fetch R-type instr. decode lw,sw beq j Ot = A op B Reg[IR[5-]] = Ot Ot = A + sign-etend(ir[5-]) lw DR = emory[ot] Reg[IR[-6]] = DR sw emory[ot]= B Galen Sasaki EE 6 University of Hawaii 7 beq and j beq Step. if (A == B) PC = Ot j Step. PC = PC[-8] (IR[5-])<<) Galen Sasaki EE 6 University of Hawaii 8

10 State Diagram instr fetch Ot = A op B R-type Reg[IR[5-]] = Ot instr. decode lw,sw Ot = A + sign-etend(ir[5- ]) lw DR = emory[ot] Reg[IR[-6]] = DR sw beq emory[ot] = B j if (A == B) PC = Ot PC = PC[-8] (IR[5-])<<) Galen Sasaki EE 6 University of Hawaii 9 Controller Design Simple state machine Seqential circits types Controller types - straightforward - improvement - microprogramming Galen Sasaki EE 6 University of Hawaii

11 lti-cycle IPS Controller Design PCCond PCSorce PC IorD em em emtoreg Otpts Control Op SrcB SrcA Reg PC ress emory emdata Instrction [-6] Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction Instrction [5 ] emory IR Instrction [5 ] IR Op [5 ] Instrction [5 ] RegDst 6 Registers Sign etend A B 6 8 control PC [-8] Zero reslt Jmp address [-] Ot Instrction [5 ] Galen Sasaki EE 6 University of Hawaii Inpt Seqential Circits: ealy and oore ealy circit: Good: ost general. All seqential circits are ealy circits Bad: potential for loops of combinational circits. Potential for race conditions, instability, asynchronos. Comb Circit (CC). S.R. Otpt Comb Circit. Comb Circit. oore circit: Doesn t have the potential for these loops. Safer. CC SR CC All signals go throgh SR -- no loops S.R. S.R. State Register (SR) Oops! Galen Sasaki EE 6 University of Hawaii

12 Do we have a problem? IPS Controller control otpts Comb. Circ net state State opcode IR Galen Sasaki EE 6 University of Hawaii IPS Controller: Smaller CC Comb. Circ control otpts Comb. Circ net state State opcode IR Galen Sasaki EE 6 University of Hawaii

13 Eample: designing a simple seqential circit X [] [] Clock [] Y Otpt Y Straightforward approach icro-programming approach [] [] 5 [] 6 [] Galen Sasaki EE 6 University of Hawaii 5 X [] [] Eample: straigtforward approach [] Clock [] Y [] 5 [] Otpt Y 6 [] X Register Array of D flip flops State Galen Sasaki EE 6 University of Hawaii 6 CC CC NetState Y State X NetState etc State Y etc

14 Eample: Straightforward approach Dispatch X Focs on this part X Clock CC Register Y NetState State Reset Galen Sasaki EE 6 University of Hawaii 7 [] [] [] [] Seqence [] 5 [] 6 [] Dispatch CC State Disp Seq Res Seq Disp 5 Res 6 Res Disp Seq Reset NetState Disp Eample: Straightforward Dispatch approach X Focs on this part X Clock CC Register Y NetState State Reset Galen Sasaki EE 6 University of Hawaii 8 [] [] [] [] Seqence [] 5 [] 6 [] Dispatch CC State Disp RO Disp Seq Res Seq Disp 5 Res 6 Res + X NetState Disp RO X 5 6

15 Eample: icroprogramming [] [] [] [] [] It s like a program with jmps and conditional branches. Let s make a tiny compter for the controller. X Disp Rom Disp Rom X Clock + 5 [] State Y Seq Info 6 [] icro-instrctions Galen Sasaki EE 6 University of Hawaii 9 Reg Y icroprogram (RO) r Contents Disp, Seq, Reset, Seq, Disp, 5 Reset, 6 Reset, Back to IPS Controller Comb. Circ control otpts Comb. Circ net state State opcode IR Galen Sasaki EE 6 University of Hawaii

16 Straightforward Approach State Comb. Circ control otpts inpt otpt IR = emory[pc] PC = PC+ A = Reg[IR[5-]] B = Reg[IR[-6]] Ot = PC + sign-e(ir[5-])<< ot = A + sign-e(ir[5-]) DR = emory[ot] Reg[IR[6-6]] = DR 5 emory[ot]=b 6 Ot = A op B 7 Reg[IR[5-]] = Ot 8 if (A==B) PC = Ot 9 PC = PC[-8] (IR[5-]<<) Galen Sasaki EE 6 University of Hawaii Straightforward Approach opcode IR Comb. Circ net state State state opcode net state depends on opcode depends on opcode Galen Sasaki EE 6 University of Hawaii

17 Straightforward Approach state opcode net state = + dispatch dispatch = = dispatch dispatch m state C.C. 7 5 Galen Sasaki EE 6 University of Hawaii Simple State achine + m state dispatch dispatch C.C. opcode dispatch opcode otpt ld sw R-type 6 beq 8 j 9 dispatch opcode otpt ld sw 7 5 Galen Sasaki EE 6 University of Hawaii

18 icroprogramming state control otpt seqencing fetch, inc PC seq reg file, br addr dispatch A + const dispatch read seq store in reg file fetch 5 store in fetch 6 A op B seq 7 store in reg file fetch 8 cond. branch fetch 9 j fetch fetch: go to seq: go to net state dispatch: net state depends on opcode Galen Sasaki EE 6 University of Hawaii 5 icroprogramming icroprogramming: another way to describe controller sing programming lang. style Like machine code, bt where each instrction (called microinstrctions) corresponds to one clock cycle icroinstrction format: Reg. PC Label control SRC SRC control emory control Seqencing for dispatch to control path for seqencing: seq, fetch, dispatch Galen Sasaki EE 6 University of Hawaii 6

19 icroprogramming Reg. PC Label control SRC SRC control emory control Seqencing Sbt Fnc Code PC A DR Reg RegDst emtoreg PC em em IorD IR (e.g., PC=PC+) Ot-Cond Jmp ress PC PCCond PCSorce B Etend EtShft Galen Sasaki EE 6 University of Hawaii 7 icroprogramming Label Operations Seqencing Fetch IR=em[PC], PC=PC+ seq A = Reg[], B = Reg[], Ot = PC + offset dispatch em Ot = A + const dispatch LW DR = emory[ot] Reg[] = DR SW emory[ot] = B Rformat Ot = A op B Reg[] = Ot BEQ if (A==B) PC = Ot JUP PC = address in IR Galen Sasaki EE 6 University of Hawaii 8

20 icroprogramming Label Operations Seqencing Fetch IR=em[PC], PC=PC+ seq Reg. PC Label control SRC SRC control emory control Seqencing Fetch PC PC seq Label Operations Seqencing em Ot = A + const dispatch Reg. PC Label control SRC SRC control emory control Seqencing em add A Etend dispatch Galen Sasaki EE 6 University of Hawaii 9 Odds and Ends Single cycle IPS -- Clock rate Register transfer notation (RTN) or langage (RTL) One-hot encoding Galen Sasaki EE 6 University of Hawaii

21 Performance of Single Cycle IPS From Section 5. of the tetbook Instrctions R-type lw sw branch j Instrction [5 ] Jmp address [ ] 6 8 PC+ [ 8] Instrction [ 6] Control RegDst Jmp Branch em emtoreg Op em Src reslt Reg Assmptions! Delays emory nits: ns and adder: ns Register file: ns All other nits: ns PC address Instrction [ ] Instrction Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction [5 ] Registers Galen Sasaki EE 6 University of Hawaii Instrction [5 ] 6 Sign etend control Zero reslt ress Data Performance Signal paths start and end at seqential circits (s) Clock period >= delay along any signal path Comb Circit Register T Comb Circit Register Register Comb Circit Register Comb Circit Comb Circit Clock period >= T, assming settling time of = Galen Sasaki EE 6 University of Hawaii

22 Performance: R-type Delays emory nits: ns and adder: ns Register file: ns All other nits: ns ns Instrction [5 ] Jmp address [ ] 6 8 PC+ [ 8] reslt RegDst Jmp Branch Instrction [ 6] Control em emtoreg Op em PC address Instrction [ ] Instrction ns Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction [5 ] Src Reg Registers ns ns 6 Sign etend control ns Zero reslt ress Data 6 ns total Instrction [5 ] Galen Sasaki EE 6 University of Hawaii Performance: lw Delays emory nits: ns and adder: ns Register file: ns All other nits: ns ns Instrction [5 ] Jmp address [ ] 6 8 PC+ [ 8] reslt RegDst Jmp Branch Instrction [ 6] Control em emtoreg Op em PC address Instrction [ ] Instrction ns Instrction [5 ] Instrction [ 6] Instrction [5 ] Instrction [5 ] Src Reg Registers ns ns 6 Sign etend control ns Zero reslt ress ns Data 8 ns total Instrction [5 ] Galen Sasaki EE 6 University of Hawaii

23 Performance R-format 6 ns lw 8ns sw 7ns branch 5 ns jmp ns Clock period >= 8 ns Galen Sasaki EE 6 University of Hawaii 5 Register Transfer Notation (RTN) or Langage (RTL) It shows how flows from to E.g. IR = emory[pc] Ot = (A, B) Galen Sasaki EE 6 University of Hawaii 6

24 One-Hot Assignment Controllers have states One-hot assignment has states where there s eactly one and the rest zeros, e.g., Sometimes it leads to smaller circits Galen Sasaki EE 6 University of Hawaii 7 One-Hot Assignment A B D Q D Q D Q D Q D Q Clock OR [] [] [] [] [] Simple decoder becase of one-hot assignment state vales Galen Sasaki EE 6 University of Hawaii 8

EE457 Lab 6 Design of a Pipelined CPU Lab 6 Part 4 Questions 10/29/2006. Lecture by Gandhi Puvvada. University of Southern California

EE457 Lab 6 Design of a Pipelined CPU Lab 6 Part 4 Questions 10/29/2006. Lecture by Gandhi Puvvada. University of Southern California EE45 Lab 6 Design of a Pipelined CPU Lab 6 Part 4 Questions 0/29/06 Lecture by Gandhi Puvvada University of Southern California 0/29/06 / 32 C Copyright 06 Gandhi Puvvada Thanks to Ray Madani and Binh