Control Hazards. EE 457 Unit 6c. Option 1: Stalling. An Opening Example. Control Hazards

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1 Hazas EE 7 6c Hazas (branch) hazas are named such because they deal with issues related to program control instructions (branch, jump, subroutine call, etc) There is some delay in determining a branch or jump instruction and thus incorrect instructions may already be in the pipeline : BEQ $,$,8 : AND $,$,$ 8: OR $,$6,$ : ADD $,$,$ 7: LW $,($7) An Opening Example Option : ing : BEQ $,$,8 : AND $,$,$ 8: OR $,$6,$ CC CC CC CC CC CC6 CC7 CC8 CC9 Beq=true BEQ outcome known in MEM stage (CC) Option : Sta stalling the pipeline as soon as you detect that it is a branch and keep stalling until you know the outcome : BEQ $,$,8 : AND $,$,$ CC CC CC CC CC CC6 CC7 CC8 CC9 BEQ=true Disadvantage: Penalty of for branch and HW is Still need to the following instruc : ADD $,$,$ 7: LW $,(7) instructions enter the pipeline by CC 8: OR $,$6,$ : ADD $,$,$ How can we solve this problem? 7: LW $,(7)

2 6 Option : Flushing Option : Flushing Option : Pipeline assumes sequential execution by default Optimistically assume sequential execution Since the incorrectly fetched instructions are still in stages [IF, ID, EX] that do not (write a register or memory) they can be safely flushed Let us add suppo for this flushing Option : Pipeline assumes sequential execution by default Optimistically assume sequential execution Since the incorrectly fetched instructions are still in stages [IF, ID, EX] that do no alter processor state (write a register or memory) they can be safely flushed Let us add suppo for this flushing CC CC CC CC CC CC6 CC7 CC8 CC9 BEQ=true CC CC CC CC CC CC6 CC7 CC8 CC9 BEQ=false : BEQ $,$,8 : BEQ $,$,8 : AND $,$,$ Still have a clock penalty when the branch outcome is true : AND $,$,$ when the branch outcome is false 8: OR $,$6,$ 8: OR $,$6,$ : ADD $,$,$ : ADD $,$,$ 7: LW $,(7) 7 8 Flushing Strategy Late Determination To flush we merely override the pipeline control signals to similar to the stall logic can be re-used and triggered by a successful branch ( AND = ) ing only dealt with ID and subsequent stages, not stage Successful branch requires that the instruction in IF be, but on the next cycle how will the stage know that the bits in the register are not a instruction but a instruction When a branch outcome is true we will out the control signals in the ID,EX,MEM stages Set a control bit in the register that will tell the stage on the cycle that the instruction is INVALID IR IFFlush Reg # Reg # Reg # data data 6 Ex Mem SelA SelB Forwaing Sh Res Mem Prior Mem & Mem Mem or result

3 9 Late Determination Late Determination w/ fix IR Reg # Reg # Reg # data data What if declares a STALL at the same time a is taken? 6 When we stall, = and IFFlush Ex Mem SelA SelB Forwaing Sh Res Mem Prior Mem & Mem Mem or result IR Reg # Reg # Reg # data data 6 Fix the s by OR ingwith the Flush signal so that will be whenever a branch is taken IFFlush Ex Mem SelA SelB Forwaing Sh Res Mem Prior Mem & Mem Mem or result Early Determination The stage distance between and and determines how many instructions are flushed Define this number as the (how many instructions/clock cycles are wasted when a branch is taken) If we can determine the branch outcome and target computation earlier, we can this penalty Observation: All necessary information for both branch outcome and target computation are available (late) in the stage Move comparison and disp operations to the stage Requires moving since branch instructions may need data from later in the pipe Early Determination IR IFFlush Reg # Reg # Reg # data data 6 EXReg EXRegDst Sh SelB SelA = Forwaing Ex Mem Add a comparator to the Decode stage and move the forwaing into this stage We now forwa from the of one stage to the of the previous Res RegDst Mem Mem Mem, Prior Mem & Mem Mem or result

4 Early Determination w/ Predict NT Delay Slots BEQ $a,$a,l (NT) L: ADD $s,$t,$t SUB $t,$t,$s OR $s,$t6,$t7 BNE $s,$s,l (T) L: AND $t,$t6,$t7 SW $t,($s) LW $s,($s) C Fetch (IF) BEQ Decode (ID) C ADD BEQ Exec (EX) C SUB ADD BEQ Mem (ME) C OR SUB ADD BEQ Using early determination & predict NT keeps the pipeline full when we are correct and has a instruction penalty for our -stage pipeline C BNE OR SUB ADD BEQ C6 C7 C8 C9 C Problem: After a branch we fetch instructions that we are not sure should be executed Idea: Find an instruction(s) that should be executed (independent of whether branch is or ), move them to directly after the branch, and have HW just let them be no matter what the branch outcome is delay slot(s) = that the HW will execute after a branch and not flush Assuming early branch determination (ie in decode), only need delay slot 6 Delay Slot Example Implementing Delay Slots lw $s,($s) add $s,$s,$s beq $s,$t8, NEXT delay slot instruc Assume a single instruction delay slot (as with our updated early determination pipeline) Taken Path Code T Before Code lw $s,($s) add $s,$s,$s BEQ Delay Slot NT Not Taken Path Code After Code Flowcha pepective of the delay slot Move an ALWAYS executed instruction down into the delay slot and let it execute no matter what HW will define the number of branch delay slots (usually a small number or ) Compiler will be responsible for arranging instructions to fill the delay slots Must find instructions that the branch does NOT DEPEND on If no instructions can be rearranged, can always inse NOP instructions and just waste those cycles lw $s,($s) add $s,$s,$s beq $s,$t8, NEXT delay slot instruc Cannot move lw into delay slot because beq needs the $s value generated by it lw $s,($s) add $t8,$s,$s beq $s,$t8, NEXT nop If no instruction can be found a nop can be inseed by the compiler

5 7 8 Early Determination w/ Delay Slot How Good is the Compiler? XOR $s,$s,$s L: ADD $s,$t,$t SUB $t,$t,$s6 OR $s,$t6,$t7 BNE $s,$s,l (T,NT) L: AND $t,$t6,$t7 SW $t,($s) LW $s,($s) C C C C C C6 C7 C8 C9 C Fetch (IF) XOR Decode (ID) Exec (EX) Mem (ME) By scheduling the delay slot with an earlier instruction we incur no stalls/bubbles and don t have to predict the branch Source: Hennessey and Patteon, Computer Architecture A Quantitative Approach, nd Ed Pg 69 How many delay slots should be use? While delay slots seem to improve performance, the benefit depends on the compiler s ability to fill them with useful instructions One of more NOP s in the delay slots but increase the instruction count # of Delay Slots Compiler Fills #Useful #NOPs Loss of Cycles if taken Lossof Cycles if not taken Assume 6%Taken % Not Taken Loss of Cycles Compiler filling prob Lossof cycles (Expectation) *6 *=8 % 8 Use NOP 6% Use NOP % Use NOP % Use NOP % Use NOP % Use NOP % Use NOP 8% Use NOP % Use NOP % Instruction increasing factor Other Delay Slots? Recall that a LW followed by a dependent instruction requires our logic to inse bubble (stall for cycle) The MIPS ISA could declare a delay slot This means the compiler schedule a dependent instruction into the delay slot after a LW If necessary compiler can follow the LW with a nop If the ISA declares a LW delay slot do we need the?