Interrupts in Detail. A hardware and software look at interrupts

Transcription

1 Interrupts in Detail A hardware and software look at interrupts

2 Blackfin MASKS and Latches Same hardware in concept as previous slides

3 The standard instruction cycle RESET THE PROCESSOR RESET* (ACTIVE low) EXECUTING YOUR PROGRAM UNTIL POWER IS REMOVED INSTR PHASE 1 FETCH AN INSTRUCTION FROM PROGRAM MEMORY INSTR PHASE 4 WRITE BACK THE RESULT INSTR PHASE 2 DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY INSTR PHASE 3 EXECUTE THE INSTRUCTION

4 The standard instruction cycle with external device having important data RESET THE PROCESSOR RESET* (ACTIVE low) 16-bits INSTR PHASE 1 FETCH AN INSTRUCTION FROM PROGRAM MEMORY INSTR PHASE 4 WRITE BACK THE RESULT EXTERNAL HARDWARE This is the data Control signal Thanks Processor has received data INSTR PHASE 2 DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY INSTR PHASE 3 EXECUTE THE INSTRUCTION Check if ready Control signal I have data for you

5 The wait till ready approach of reading data from external device In decode phase read control register value In execute phase check if 1 -- keep waiting (fetch-decode-execute-writeback instruction cycle) until the control value changes from 0 (device not ready) to 1 (device ready) When 1 go to a different part of your program code to read the data e.g. call ReadData( ) Then your program must send an acknowledge back to device that the data has been read. e.g. call AcknowledgeReadData( ). The device can then go and get more values for you. PROBLEM: You have no time to do anything else other than wait Not a problem if waiting for this device is the only thing you want to do with the processor

6 The Poll approach of getting data Not much waiting but a lot of doing read control register value of device 1 -- if 1 go to a different part of the code to read the data (ReadData1( ) ) after reading the data send an acknowledge signal back to device 1 (AcknowledgeReadData1( ) ) -- if 0 go and read the control value of device 2 don t worry about device 1 for some time read control register value of device 2 -- if 1 go to a different part of the code to read the data (ReadData2() ) after reading the data send an acknowledge signal back to device 2 (AcknowledgeReadData2( ) ) -- if 0 go and read the control value of device 3 don t worry about device 2 and 3 for some time ETC PROBLEM: What happens if, while you are handling device 2, device 1 has time sensitive information that will disappear if device 1 is not serviced immediately

7 Interrupt Approach basic idea Extra phase in instruction cycle RESET THE PROCESSOR RESET* (ACTIVE low) CONTINUE AS BEFORE DO ISR yes Acknowledge Request done NO PHASE ANY- TIME CHECK IF AN INTERRUPT REQUEST HAS OCCURRED PHASE 1 FETCH AN INSTRUCTION FROM NORMAL (NOT ISR) PROGRAM MEMORY PHASE 4 WRITE BACK THE ANSWER CONTROL SIGNAL DATA READY SIGNAL BECOMES INTERRUPT REQUEST PHASE 2 DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY PHASE 3 EXECUTE THE INSTRUCTION 16-bits data EXTERNAL HARDWARE

8 Simple model of interrupts INT Every instruction has four phases that execute in turn Next instruction s phase is stopped ISR executed Blocked Instruction is restarted after ISR RTI instruction ISR Instr1 ISR Instr2 ISR Instr3 RTI

9 Real Life -- Processor has pipelined instructions Decod Execut Writebac Pipelining still means that each instruction takes 4 cycles to complete However a new instruction only takes an extra 1 cycle to complet So overall the processor is running 4 times faster

10 Blackfin 10 stage Pipeline

11 Real Life -- Processor has pipelined instructions Writebac INT

12 Real Life -- Processor has pipelined instructions e e k ISR F1 ISR F2 ISR D1 ISR ISR D2 ISR E1 RTI F ISR ISR E2 ISR W1 RTI ISR ISR W INT

13 Real Life -- Processor has pipelined instructions h de te ck ISR F1 ISR F2 ISR D1 ISR ISR D2 ISR E1 RTI F ISR ISR E2 ISR W1 RTI D ISR ISR W2 RTI E Fe Dec RT INT After RTI phase (RETI register has been recovered) The processor know enough to be able to restart the pipeline

14 Real Life -- Processor has pipelined instructions RTI F ISR ISR E2 ISR W1 RTI D ISR ISR W2 RTI E RTI W W E After RTI phase RETI register has been recovered It can be REGISTER FORWARDED TO THE PC Without waiting to actually be stored somewhere The processor know enough to be able to restart the pipeline

15 Blackfin interrupt pipeline looks like this (see reference sheet)

16 Real Life -- What happens if Interrupt occurs between CC = R1 <= R2 F CC = F IF CC D CC = D IF CC E CC = E IF CC W CC = IF CC JUMP AFTER ISR We must be able to complete IF CC operation Condition code bit CC is therefore a INT F IF CC RTI E D IF CC RTI W E IF CC D E WriW non-volatile register Part of the Blackfin STAT register

17 Your Assignment 2 Watchdog time ISR DEFECT written as subroutine by mistake WATCHDOG EXAMPLE NOT CORE- TIMER NEEDED FOR ASSIGNMENT 2

18 CLI stop interrupts (CLear IMASK a Makes sense as SSYNC means finis STI -- restart interrupts (STore R

19 This is not ending in RTI but RTS If you put this into EVT (Event Vector Table) It will fit BUT CRASH THE SYSTEM WHEN USED

20 Your Assignment 2 Watchdog time ISR -- Correctly written

21 Save CC (ASTAT) and then any register used (P0 Compare uses R7 but does not cha Always jump So R7 is never actually loaded usin Recover P0 And then CC This code is simply to fix the AN pipeline code

22 Compiler knows that going to Call a subroutine during ISR So saves every register that might get changed as all registers are non-volatile during ISR

23 SUB code ISR code body

24 ISR Must be fast Step 1 turn on C++ Optimizer

25 Turn on optimizer for ISR No optimizations possible

26 Look at new version of ISR code without UpdateSimulation call

27

28 Writing an ASM ISR for Post Lab 3 Quiz Step 1 Write the subroutine version of the code to be used inside the ISR Step 2 Identify all registers being used All volatile AND non-volatile Step 3 Start ASM code as follows.section program.global _ISR _ISR: Special code to handle silicon race issues (State don t include

29 .section program.global _ISR _ISR: Special code to handle silicon race issues (State don t include code) Link 0x0 (Saves RETS and FP) [--SP] = ASTAT Show the volatile AND nonvolatile registers being saved to stack (eg. [--SP] = R0; [--SP] = P0; [--SP] = R1; [--SP] = P2 etc.) Essentially the subroutine code (optimized as much as possible) REMOVE RTS Show the registers being recovered from the stack (reverse order) (eg. Etc. P2 = [SP++]; R1 = [SP++]; P0 [SP++]; R0 = [SP++]) ASTAT = [SP++]; UNLINK RTI -- and the most important difference REMEMBER FAST ISR means only save registers used no more

30 NMI interrupt Looks the same But different hardware causes interrupt Means use RETN register not RETI