FLYSIG: Dataflow Oriented Delay-Insensitive Processor for Rapid Prototyping of Signal Processing 1

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1 FLYSIG: Dataflow Orintd Dlay-Insnsitiv Procssor for Rapid Prototyping of Signal Procssing 1 Wolfram Hardt, Brnd Klinjohann -mail: {hardt,brnd}@c-lab.d ooprativ omputing & ommunication Laboratory Simns Nixdorf Informationssystm AG & Univrsität-GH Padrborn Fürstnall 11, D Padrborn, Grmany Abstract: As th on-chip intgration of HW-moduls dsignd by diffrnt companis bcoms mor and mor popular rliability of a HW-dsign and valuation of th timing bhavior during th prototyp stag ar absolutly ncssary. On way to guarant rliability is th us of robust dsign styls,.g., dlay-insnsitivity. For arly timing valuation two aspcts must b considrd: a) Th timing nds to b proportional to tchnology variations and b) th implmntd architctur should b idntical for prototyp and targt. Th first can b mt also by dlay-insnsitiv implmntation. Th lattr on is th ky point. A unifid architctur is ndd for prototyping as wll as implmntation. Our nw approach to rapid prototyping of signal procssing tasks is basd on a configurabl, dlay-insnsitiv implmntd procssor calld FLYSIG 2. In ssnc, th FLYSIG procssor can b undrstood as a complx FPGA whr th LBs ar substitutd by bit-srial oprators. In this papr th gnral concpt is dtaild and first xprimntal rsults ar givn for dmonstration of th main advantags: dlay-insnsitiv dsign styl, dirct corrspondnc btwn prototyping and targt architctur, high prformanc and rasonabl shortning of th dsign cycl. 1 Introduction Rapid prototyping for automatically gnratd dsigns as wll as for manually dvlopd dsigns has found a lot of intrst during th last yars [21]. Most approachs map th systm s gat-lvl ntlist onto fild-programmabl gat arrays (FPGAs) mainly du to th rprogramability of th hardwar function, that is functionality is asy to chang. But in many cass a singl FPGA s capacity is not sufficint to covr th complt synthsizd ntlist and only by additional ntlist partitioning an implmntation bcoms possibl [28]. Bsid th computation ovrhad for this partitioning I/O-rstrictions must b mt [13, 30]. Partitioning and I/O-routing ar both highly dpndnt on th FPGA typ, th FPGA intrconnctions, and 1. Th authors would lik to acknowldg th support providd by Dutsch Forschungsgminschaft DFG, projct SPP RP. 2. dataflow orintd dlay-insnsitiv SIGnal procssing th communication protocols. Som providrs of multipl FPGA boards offr softwar for ntlist partitioning and gnration of communication structurs [30, 13]. But ths algorithms do not start from an abstract gat-lvl ntlist. Th ntlist must b mappd onto a concrt gat-library known to th providr,.g. th LSI10K library [26] and is than automatically rmappd onto th multipl FPGA board (figur 1). gat-lvl ntlist FPGA gat-lvl ntlist gat-library FPGA FPGA FPGA FPGA oprator-lvl ntlist (c) Figur 1: Dsign stps from gat-lvl ntlist to singl FPGA, multipl FPGA board and (c) FL- YSIG procssor basd implmntations. In othr words, for rapid prototyping th gat-lvl ntlist is mappd to a ddicatd FPGA architctur. Thus lmnts of th ntlist ar dirctly dcomposd by lmnts of th FPGA architctur (figur 1 ) or by lmnts of a standard gat library and ths lmnts ar dcomposd by lmnts of th FPGA architctur (figur 1 ). This doubl dcomposition is th rason for additional costs (numbr of gat clls, intrconnction). It points out that th advantags of FPGA tchnology ar paid by additional dsign tasks and difficult to mt dsign rstrictions. W considr an ntirly nw approach to rapid prototyping solving th mntiond abov trials. Th main ida is to driv a prototyping architctur from a domain spcific optimizd targt architctur. This architctur is implmntd as configurabl procssor namd FLYSIG-prototyp procssor. Th FLYSIG must b onc providd as chip, i.. a nw prototyping chip. figur 2 illustrats th comparison of our approach with th dscribd standard approachs.

2 FPGA prototyp 2 Rlatd work Rsarch in synchronous dsign mthods has takn plac for svral dcads. A good summary is givn in [17]. Basic concpts of asynchronous circuit dsign ar prsntd.g. in [15]. A lot of ffort has bn invstd in data protocols and data ncoding. In [12] a tru-singl-phas protocol has bn prsntd. Th two-phas protocol is usd by [7] and also th dsign of th asynchronous vrsion of th ARM procssor calld AMULET1 [29] is basd on th twophas protocol. In a latr vrsion, th AMULET3 procssor, th four phas protocol has bn usd [8] bcaus convrsion from two-phas protocol to fourphas protocol is rathr costly. Svral data ncoding styls ar known. Dual-rail ncoding provids two singl data lins, on for th logic tru valu and on for th logic fals valu of a on bit data itm. This ncoding is rathr complx but thr ar no problms bcaus of hazards [7]. Rcntly, a combination of singl-rail and dual-rail data ncoding has bn suggstd [18]. On approach to rduc th numbr of data lins ncssary for dual-rail ncoding is bundld data ncoding [22]. To a st of data bits, calld bundl, a pair of acknowldg/rqust bits is addd for indication of valid data. Thus th ovrhad for th bundl is liminatd but th dlay of th control lins must b adaptd to th dlay of th data lins [23]. This limitd slction of rfrncs shows that a varity of ncoding styls and communication protocols hav bn dvlopd and ar usd for circuits of rasonabl complxity. Bsid data ncoding and communication protocols dsign mthodologis hav gaind a lot of intrst. An ovrviw is givn in [11]. In 1989 Suthrland prsntd th concpt of micropiplins [25] which has found a lot of intrst worldwid. Many invstigations hav bn basd on this concpt [19, 9, 5, 6, 2]. Th concpt of multi-ring structurs introducd by Staunstrup [24] uss no dlay lmnts but suffr by th complxity of th gnratd circuits. Th prformanc of multi-ring structurs is highly influncd by th availability of data itms and fr placs rady to hand data itms on. Fr placs ar commonly calld bubbls [10]. In th prsntd approach, w us th dual-rail data ncoding styl and th four phas data protocol. W adaptd th concpt of multi-ring structurs and solvd th circuit complxity problm by our own fspcification synthsis gat-lvl ntlist ASI spcification synthsis oprator-lvl ntlist ASI prototyp ASI Figur 2: Rapid prototyping approachs: synchronous, FPGA basd and dlay-insnsitiv FLYSIG-prototyp procssor basd. Th targt-architctur itslf is spcializd to th application domain of fixd digital signal procssing algorithms. It is a wll known stratgy to adaptd th dsign mthods to a spcific application domain. Diffrnt approachs for partitioning and synthsis as wll as for targt architcturs hav bn proposd,.g., for control orintd dsigns [4, 1], data flow orintd dsigns [14, 3], and ral tim constraind dsigns [20, 27]. W applid this principl of spcialization to prototyping, i.., th prototyping-architctur is spcializd in rspct of th targt-architctur. This ida brought us to th FLYSIG-approach. Th main advantags ar: th limination of all dsign tasks rlatd to FP- GA-prototyping from th dsign flow. This shortns th dsign cycl drastically. Th additionally introducd dsign stp which drivs th FLYSIGtargt form th FLYSIG-prototyp is an asy to automat task of much lowr complxity. th dlay-insnsitiv dsign styl usd for th FLY- SIG-procssor. Th wll known gains of dlay-insnsitiv dsigns ar th limination of th clock signal, powr savings, and a vry robust modularization. Dlay-insnsitivity is of major importanc for rapid prototyping bcaus timing analysis on th prototyp basis within a complx nvironmnt is ssntial for rliabl systm validation and short tim to markt priods. W hav xamind th synthsis of dlay-insnsitiv moduls [16] and found that th timing bhavior of such moduls can b analyzd in an arly dsign stag, that is th tchnology impact can b approximatd quit wll. th high prformanc achivd by th FLYSIG-procssor, i.., sampling rats of 50 MHz and mor. This papr is structurd as followd. W prsnt th FLYSIG-procssor concpt in chaptr 3 and illustrat th bnfits by th fifths ordr lliptic filtr xampl in chaptr 4. Final conclusions ar givn in chaptr 5. First of all som background information is providd (chaptr 2)

3 ficintly implmntd oprator library basd on th tchnology dscribd in [16]. Bubbls ar intgratd in a fixd mannr into th oprators. Additional bubbls ar insrtd in btwn th oprators during th dsign procss. Th oprators ar th ssntial part of th FLYSIG-procssor architctur, which is dscribd in th nxt chaptr in som dtail. 3 Th FLYSIG-procssor architctur Th FLYSIG-procssor architctur allows th fficint implmntation of priodic, a priori fixd algorithms. Such algorithms ar common practic in digital signal procssing, and in ral-tim controllr componnts,.g., for ractiv robotic systms. All algorithms ar also constraind by high sampling rats which ar dtrmind by rathr complx nvironmnts. In this sction th architctur itslf and th adaptation to prototyping ar prsntd. 3.1 Ovrviw Figur 3 illustrats th dataflow within th FLYSIGprocssor which is build out of th thr dpictd componnts. In addition intrconnction to th nvironmnt is providd. Th configuration and status-control componnt allows th comfortabl configuration of th FLYSIG-procssor. Th schduling information is fd into th local mmory (rgistrs) and into th routing componnt for initial oprand and rsult forwarding. In addition th initial oprands ar stord into th mmory. All information can b providd by a configuration host bfor xcution. Th mmory and routing componnt handls th oprands and th computation rsults. A data itm in th mmory is rfrrd to as tokn, thus it is not distinguishd if it is an oprand or a rsult. Th tokns flow from th mmory into th opration componnt via th tokn valuation. This block dtrmins if a mmory cll contains a valid tokn. routing tokn valuation local mmory guard valuation configuration and status-control componnt opration distributor ation & status control mmory and routing componnt data schduling I/O port D/A-A/D-Port opration componnt Figur 3: Dataflow within th FLYSIG-procssor. Th FLYSIG-procssor is initializd by th configuration and status-control componnt. Th mmory and routing componnt is intrconnctd with th opration componnt to a cyclic structur. Within this structur th multi-ring concpt is mbddd. Furthrmor, this ring-structur is opn, that is, additional FLYSIG-procssors can b adaptd. Thus procssor ntworks can b build asily. 3.2 Procssor concpt Th application which is to b implmntd by th FLYSIG-procssor is spcifid by its control/data flow graph. Each opration is rprsntd by a nod in th data flow graph. By opration schduling ach dataflow nod is assignd to an oprator of th opration componnt of th FLYSIG-procssor. Thn th intrconnction task, known from synchronous dsign must b prformd. For th FLYSIG-prototyp vrsion this mans to initializ th routing componnt. For th targt-vrsion th chosn routing configuration is hardwird. In figur 4 som dtails ar shown:... Figur 4: oncpt of th FLYSIG-procssor with th configuration and status componnt, th mmory and routing componnt and (c) th opration componnt. In this cas th routing block dircts th tokn to th corrsponding oprator. Each tokn consists of th opration id (idntifying th opration), a valid-flag sgmnt (indication th availability of oprands) and a guard-flag sgmnt (dtrmining whr th rsult valus ar ndd). (c) Th opration componnt implmnts th oprators for all possibl computations. In th prototyp-vrsion a larg st of oprators is providd in ordr to support as many diffrnt algorithms as good as possibl. Oprators rad th tokns from mmory or from prvious involvd oprators. Thus, oprator piplining is possibl. Bcaus of th bit-srial implmntation styl this lads to dp piplins with vry fw hazards and thus to high throughput rats. Th computation rsults ar writtn into th local rgistrs or dirctly to th rgistrs of a furthr FLYSIG-procssor. This is an - 3 -

4 important fatur which allows to distribut th implmntation of a singl algorithm ovr svral FLYSIG-procssors. Also prototyp-vrsions may b connctd with targt-vrsions which ar alrady availabl. This is of high practical importanc bcaus a stpwis migration from th prototyp nvironmnt to th targt implmntation bcoms fasibl. 3.3 Prototyping Th prototyp vrsion of th FLYSIG-procssor diffrs from th targt vrsion only by th implmntation of th routing componnt and th complxity of th opration componnt. Bcaus th concpt of th FLYSIG-prototyp vrsion has bn drivd form th targt vrsion th oprator concpt and th dataflow rmains unchangd. Just th hardwird schduling implmntation is xchangd by a configurabl on. This allows th mapping of svral diffrnt algorithms onto th sam FLYSIG-prototyp procssor. In this contxt a configurabl schduling can b implmntd by simpl associativly controlld crossbar switchs. Furthrmor, in th FLYSIG-prototyp procssor a st of oprators is providd with most common oprators. This oprator st is only rstrictd by th dsign siz. Onc an algorithm has bn mappd onto th prototyp vrsion and hardwar-in-th-loop simulation has bn succssful th FLYSIG-targt procssor can b drivd from th prototyp vrsion asily by liminating all unusd oprators and rplacing th configurabl schduling by a hardwird implmntation. This liminations and rplacmnts can b prformd automatically. 3.4 Oprators Th FLYSIG s opration componnt provids oprators with control, storag lmnts and arithmtic functionality ontrol oprators For control of dlay-insnsitiv multi-ring basd architcturs svral oprators hav bn prsntd by Staunstrup [24] including asymmtric switchs, join, and fork oprators. W xtndd this st of control oprators by slct oprators which allow th communication btwn diffrnt rings. Th block symbol and th rgistr-transfr lvl ntlist of th rad-slct oprator ar prsntd in figur 5. Th RSELET oprator is controlld by th diamond input which dtrmins from which input th data is rad. Th opposit bhavior is ralizd by th WSELET oprator rading form th only input and writing to th indicatd output. Both oprators ar ssntial to implmnt control flow. S A Tru Fals RSELET Y B Figur 5: a) Block symbol and RT-ntlist of radslct oprator Storag lmnts Thr basic rgistr typs ar ndd. All ar drivd from an uninitializd minimal rgistr. In addition a 0-initializd rgistr and a 1-initializd rgistr is ndd.ths basic rgistr lmnts can b quud to shift rgistrs. Is is important that for ach data bit within th shift rgistr an xtra mpty basic rgistr lmnt should b providd thus optimal throughput can b rachd Fixpoint arithmtic oprators Oprators for fixpoint arithmtic can b constructd out of c-gats and synchronous OR gats. Such circuits can b gnratd by standard two lvl synthsis tchnics whrby th AND-plan is substitutd by a c- gat plan [24]. This dsign styl is calld DIMS 1 and lads to a mixtur of synchronous and asynchronous gat-lvl componnts and mploys larg numbrs of c-gats. S A B Figur 6: Add-oprator: DIMS and complt dual-rail implmntation. W build oprators basd on dual-rail compatibl implmntation of logic gats. This liminats th larg numbr of c-gats and nsurs a compltly tim invariant dsign. In figur 6 both implmntations ar compard. Th complxity of a c-gat (circl) and a dual-rail AND-gat is comparabl. By this bit-srial add-oprator and svral basic rgistr lmnts a complt bit-srial full-addr can b constructd. Th RT-lvl ntlist is givn in figur 7. EX & EX & OR ack Y 1. Dlay/Insnsitiv Min-trm Synthsis - 4 -

5 Figur 7: omplt bit-srial full-addr ntlist. Th modularity is quit obvious and bcaus of th dual-rail data ncoding dlay-insnsitivity is maintaind on ach hirarchy lvl. By this oprator implmntation styl furthr oprators ar implmntd and simulatd on RT-lvl. Simulation is basd on a VHDL bhavioral dscription of ach basic ntity. Dtaild timing data from transistor-ntlist simulation is usd within th RT-lvl VHDL dscriptions which allows vry fast ralistic valuation of timing Optimization Th implmntation styl for FLYSIG-oprators allows high optimizations for th implmntation of opration quus. For illustration, w considr th computation for th trm x = a + x + x + x. A straight forward implmntation is shown in figur 8. Thr full-addrs and thr basic rgistrs ar allocatd. a x + Figur 8: Straight forward and optimizd implmntation of th trm x =a+x+x+x A much chapr solution with xactly th sam functionality is givn in figur 8. Only two fulladdrs and two basic rgistr lmnts ar ndd, whrby on rgistr lmnt has bn initializd. This insrtd data itm implmnts a shift oprator with vry low costs. 4 Exampl For dmonstration of th FLYSIG-procssor s concpt and bnfits w prsnt an xampl. It is takn from th wll known high lvl synthsis bnchmark suit. Th fifths ordr lliptic filtr rquirs rasonabl computation prformanc and is simpl nough for dmonstration. From this filtr smallr subcomponnts hav bn drivd for dtaild cas studis. xampl # oprations # rgistrs #fdback cycls lliptic_filtr filtr_ab filtr_ab filtr_ab filtr_abc_ filtr_abc_ filtr_abc_ filtr_abcd_ filtr_abcd_ filtr_abcd_ Tabl 1. haractristics of filtr bnchmarks All filtr bnchmarks hav bn mappd onto th FLYSIG-prototyp procssor. Basd on this prototyp timing valuation has bn prformd. As a first stp w hav implmntd a VHDL nvironmnt for simulation of th FLYSIG-prototyp procssor. This includs VHDL dscriptions of all gat-lvl clls, oprational units and complt oprators. Th timing charactristics of a th usd gat lvl clls hav bn obtaind from analog simulation of th transistor ntlists and whr importd in th VHDL implmntations. Basd on this two lvl simulation ralistic timing and functional valuation can b prformd vry quickly. All simulations up to svral thousand ns xcution tim of th FLYSIG-procssor could b prformd within som cpu sconds which is ngligibl fw compard to othr approachs.g., basd on ptri-nt simulation or singl transition graph simulation. onsidring th timing charactristics, th circuit s latncy and throughput ar important. W hav both xamind for th FLYSIG-implmntations of th filtr applications of tabl 1. Latncy is dtrmind by th longst oprational path within th circuit. In addition th numbr of rgistrs is important bcaus rgistrs ar usd to implmnt bubbls. Thus highr latncy valus ar found for th sam filtr-functionality implmntd with fwr rgistrs. Of cours, this is a prformanc/siz trad-off. Th dtrmind latncy valus ar dpictd in figur 9. But throughput is of much highr importanc bcaus latncy can b rgardd as systm stup tim. In figur 10 th bst throughputs for all xamind filtr applications ar shown which ar rachd by an optimal numbr of bubbl rgistrs

6 ns Figur 9: Latncy of filtr applications implmntd by FLYSIG-oprators. All filtrs show th sam throughput rat although th numbr of oprations diffr. This is du to th dply piplind oprators and th dlay-insnsitiv dsign styl. Th throughput is only rstrictd by th oprator s throughput which is rathr high bcaus of th fficint implmntation of th dual-rail gats. ns No1 No2 No3 lliptic filtr_ab filtr_abc filtr_abcd filtr latncy filtr_ab filtr_abc filtr_abcd 1 throughput Figur 10: Throughput of filtr applications implmntd by FLYSIG-oprators. 5 onclusion In this papr w prsntd a nw mthodology for rapid prototyping of cyclic signal procssing applications. Th FLYSIG procssor was dvlopd for prototyping. From th FLYSIG-prototyp implmntation th Flysig-targt can b drivd asily. It has bn shown on simulation bas that this prototyping mthodology provids vry fast prototyp nvironmnts whrin hardwar-in-th-loop simulation is possibl. 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