Design Note: HFDN Rev.2; 04/08. Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator

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1 Design Note: HFDN-3.0 Rev.; 04/08 Loop-Filter Coniguration or the MAX3670 Low-Jitter PLL Reerence Clock Generator

2 Loop-Filter Coniguration or the MAX3670 Low-Jitter PLL Reerence Clock Generator Introduction The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses an external high-q voltage-controlled oscillator (VCO) to create a very low jitter clock signal phase-locked to a system clock input. It is ideal or SONET OC- 48 or OC-9 applications requiring a very low jitter 56MHz or 6MHz clock signal. The contribution o the MAX3670 to total system jitter is typically small compared to that o the external VCO. When used with a low-jitter voltage-controlled SAW oscillator (VCSO) or a voltage-controlled crystal oscillator (VCXO), the total system jitter can be less than ps rms. can be selected or pd using the GSEL inputs, which also control a portion o the eedback divider ratio. The loop ilter, with transer unction F(s), operates on the phase detector output current to generate the control voltage to the VCO. This ilter, in conjunction with the eedback divider, establishes the key characteristics o PLL operation, including bandwidth, output jitter, and PLL stability. The VCO then translates the ilter output voltage to requency, and the VCO output is ed back through the dividers to the phase-requency detector. The external VCO transer unction is vco /s, where vco (Hz/volt) is the VCO requency gain, and /s represents the integration o requency to phase. Figure is a block diagram o the MAX3670. The system clock input to the PLL is typically 78MHz, 56MHz, or 6MHz, and the VCXO or VCSO typically operates at 56MHz or 6MHz. The PLL bandwidth is adjustable rom 0Hz to 0kHz by means o selectable on-chip dividers, phase detector gain selection, and external resistor values. The MAX3670 PLL jitter peaking can be held to less than 0.dB with an external ilter capacitor no larger than.uf. An on-chip op amp provides loop-ilter gain, and an optional clock output divider is oered. A lock detect output can be used to indicate the status o the system clock input. This design note provides analysis and examples that address optimal PLL coniguration, including external component values, internal divider settings, and internal phase detector gain or low-jitter applications. VCXO vco REFCL+ REFCL- RSEL VSEL VCOIN+ VCOIN- C3 LOL_N R3 THADJ //8 //8 Main Divider Decode Logic LOL CTH VC VCOMP POLAR OPAMP- /N /N C C //4/8 Opamp R R PFD/CP pd OPAMP+ CN CP MOUT+ MOUT- POUT+ POUT- GSEL GSEL GSEL3 PSEL PSEL MAX3670 Reerence Clock Generator PLL Model Figure. MAX3670 low-jitter reerence clock generator block diagram Figure is a simpliied model o the MAX3670 PLL in closed-loop operation. The phase-requency detector converts phase error into current with a gain o pd (A/UI). In the MAX3670, one o two settings Design Note HFDN-3.0 (Rev.; 04/08) Page o 5

3 C R R C C Vre θin M Divider + Σ - θerr pd Phase Detector - F(s) + Filter R3 C3 Vre vco s VCO θ out N Divider Figure. Idealized PLL phase-domain model 3 Closed-Loop PLL Model When the PLL is in closed-loop operation, the small signal behavior is well characterized as a secondorder linear system. The ollowing is a brie summary o the relationships that govern the operation o the MAX3670 PLL. The external VCO is the irst integrator in the PLL transer unction, vco /s. To control static phase error, the loop ilter provides a second integrator, implemented via the internal op amp and capacitor C. For stability, a zero is added to the loop in the orm o resistor R in series with C. The location o this zero can be approximated as = z πr C A high order pole (HOP) is also needed to reduce spurious noise rom the phase detector. It can be implemented either by providing a compensation capacitor C, which produces a pole at hop =, π ( 0kΩ)( C ) or by adding a lowpass ilter, consisting o R 3 and C 3, directly on the VCO tuning port, which produces a pole at = hop πr C. 3 3 Using R 3 and C 3 may be preerable, because it ilters more noise in the PLL; but, in that case, it may still be necessary (particularly when using large values or R and N) to provide iltering via C in order to prevent clipping in the op amp. Finally, the external VCO adds a HOP, due to the modulation bandwidth o the tuning input. In order or the analysis presented here to model true system behavior, the pole associated with the VCO should be well above the other poles. 4 Factors Governing Closed-Loop PLL Behavior The PLL phase transer unction relates the phase at the clock output o the MAX3670, θ out, to the phase at the system clock input, θ in. This transer unction describes how phase noise (jitter) is attenuated rom the PLL input to the PLL output, and is shown in the bode plot o Figure 3. An important closed-loop perormance speciication is the loop bandwidth (in Hz), which is given by pd R vco =. πn Jitter present on the reerence clock input is attenuated or requencies higher than the loop bandwidth,. I the total output jitter is dominated by the noise in the clock input, then lowering the loop bandwidth will reduce system jitter. Design Note HFDN-3.0 (Rev.; 04/08) Page 3 o 5

4 θout θin -0dB/dec hop Design Note HFDN-3.0 (Rev.; 04/08) -40dB/dec Figure 3. PLL phase transer unction, θ out /θ in () The VCO phase transer unction relates the phase at the output o the PLL, θ out, to the phase o the VCO. This transer unction describes how phase noise in the external PLL oscillator (VCXO or VCSO) is attenuated in the MAX3670 output, and is shown in Figure 4. VCO phase noise is attenuated at requencies lower than the loop bandwidth (conversely, VCO phase noise at requencies greater than the loop bandwidth is not attenuated). I the total output jitter is dominated by phase noise in the VCO, then raising the loop bandwidth will reduce system jitter. θ out θ vco 40dB/dec z 0dB/dec Figure 4. VCO phase transer unction, θ out /θ VCO () Finally, any additional noise present at the VCO tuning input port, in the band between z and, will be transmitted to the output o the PLL with a gain o N/ pd R (UI/V). 5 PLL Coniguration and External Component Selection This section provides a brie explanation o the design choices that can be made to achieve the desired perormance rom the MAX3670 PLL. This process begins by choosing the PLL closed-loop bandwidth, VCO requency, and system clock and eedback divider ratios, depending on the application. The external VCO might be a low-jitter VCXO or 55MHz applications or a low-jitter VCSO or 6MHz applications. Consult the vendor or minimum, maximum, and typical values o VCO gain, VCO. I possible, the system clock divider, RSEL, and the VCO divider, VSEL, should be set so that the compare requency at the LOL sample point is 78MHz, to provide optimum LOL detection. The next step is to set the values or the discrete resistors and capacitors to implement the desired pole locations. In some important applications, it may be desirable to limit the jitter peaking in the PLL phase transer unction bandpass region to less than 0.dB. This can be achieved by setting the zero requency lower than the loop bandwidth by a actor o approximately 00, which produces a large damping coeicient. In this case, the jitter peaking, in db, is given by = + z Peaking 0 log. The next step in the PLL coniguration is the selection o the HOP requency. As noted beore, a HOP is useul in cutting down high-requency spurious noise rom the digital phase detector. This is addressed by choosing the HOP requency to be much less than the phase detector compare requency. A good choice is 0*hop < vco/n, where N is the total eedback division ratio. It should, however, be placed high enough in requency that it does not decrease the overall loop phase margin and impact jitter peaking. This objective can be accomplished by making certain that hop > 4. This will ensure that the contribution to jitter peaking rom the HOP is less than 0.08dB. The next section shows how a spreadsheet can be used as a tool to optimize the design. 6 Component Selection or Minimum Jitter For a particular choice o loop bandwidth, VCO gain, and divider ratios, the values o the passive components C, C, and R can be selected in a manner to minimize the intrinsic and spurious jitter components at the reerence clock generator output. O course, this does not include the unattenuated Page 4 o 5

5 jitter due to the VCO or transmitted through the PLL rom the system clock input, as described above. Intrinsic PLL noise is associated with the loop-ilter eedback resistor, R. This noise in the MAX3670 scales with the value o R, and it rolls o below the zero requency, z, and above the loop bandwidth,, as discussed above. When measured in a khz to 0MHz bandwidth, the intrinsic random jitter, in UI rms with respect to the VCO requency, can be approximated by θ rms 9 ( R ) vco 4 =, π where the actor o 4 corresponds to hop = 4. Spurious noise results rom unavoidable osets in the MAX3670 op amp and elsewhere. In normal operation, the phase detector generates up and down pulses on each rising edge o the phase detector inputs, and these edges occur at the compare requency vco /N. Any osets in the loop cause either the up or down pulse to be slightly longer, which produces spurious noise. Subject to some reasonable assumptions, and i hop << vco /N, then the worstcase spurious output jitter, in UI rms with respect to the VCO requency, is given by π hop pd vcorδ θ rms = 0.3, 4 compare where δ = 0.0 is a actor that characterizes the osets in the actual part. Table shows how a spreadsheet can be used to acilitate selection o speciic component values, given a particular VCO and loop bandwidth selection. In this example, the value o C was limited to.uf, in order to restrict the physical coniguration to 0805 size. Otherwise, the values o R, C, and C were chosen manually to minimize calculated intrinsic and spurious jitter contributions. In general, the least-intrinsic noise results rom using lower values o R and the eedback divider N. Reerences For additional inormation on the MAX3670 low-jitter reerence clock generator, see the product data sheet ( For urther inormation on using the MAX3670, contact Maxim s Applications Technical Support at Table. Spurious and Intrinsic Noise Spreadsheet PLL Parameters or Typical 55MHz/6MHz Oscillators Optimized or Output Noise Freq Loop Spurious Intrinsic VCO vco vco BW comp pd R z hop C C Jitter Noise (MHz) (ppm/v) (khz/v) (Hz) N N (MHz) (ua/ui) (kohms) (Hz) (Hz) (uf) (nf) (ps rms) (ps rms) Assumptions:) Must have C <.uf ) z = LoopBW/00 3) hop = LoopBW*4 4) No other signiicant higher-order poles 5) Jitter ater khz (SONET) highpass jitter ilter Design Note HFDN-3.0 (Rev.; 04/08) Page 5 o 5

PLL. The system blocks and their input and output signals are as follows:

PLL. The system blocks and their input and output signals are as follows: PLL This is the most complicated of the three optional labs - but is definitely the coolest system and if you can get it working, you should be able to learn a lot. The top level block diagram of the PLL