Implementation of a Multi bit VCO based Quantizer using Frequency to Digital Converter

Transcription

1 International Journal of Electronics Engineering Research. ISSN Volume 9, Number 6 (2017) pp Research India Publications Implementation of a Multi bit VCO based Quantizer using Frequency to Digital Converter [1] Anjali Jain and [2] Pankaj M. Gulhane [1] M.Tech (Scholar) Dept. of ETE, DIMAT, Raipur, India. [2] Asst. Prof. Dept. of ETE, DIMAT, Raipur, India. Abstract Voltage Controlled Oscillator (VCO) based ADC is unlike other ADCs. Input analog signal is converted into timing information via VCO then quantized in time. This paper demonstrates the multi bit VCO based quantizer using Frequency to Digital converter (FDC). Simulation result achieve in terms of SNR, SNDR and power dissipation. VCO based quantizer design using Cadence Virtuoso in GPDK 90nm technology. Keywords: VCO, FDC, SNR, SNDR, GPDK. I. INTRODUCTION Recently, there are difficulties in design of analog and mixed signal based design with scale down of technology and decreases of supply voltage. But time resolution has better under 90nm technology by reduced the effect of parasitic component. Therefore, time to digital converter (TDC) and FDC VCO based quantizer is of great choice for design ADCs. VCO based quantizer is used to improve the time resolution in ADC. An ideal VCO output is a sinusoidal signal with amplitude and phase explicit in a (1) VCOout(t) = AVCOsinθVCO(t) (1) θvco(t) = 2π 0 fc+ KVx(τ)dτ (2) Where phase is the integral of VCO frequency depends on the VCO parameters such

2 890 Anjali Jain and Pankaj M. Gulhane as center frequency ( fc), VCO gain (KV) and input signal means control voltage x(τ) to VCO. Basic block diagram of VCO based quantizer shown in fig. 1, where time quantizer is digital reset counter used for count the VCO transition with in sampling frequency (fs) to give the representation of analog input signal of VCO [1]. Fig. 1. Block diagram of VCO based quantizer II. PREVIOUS WORK The main design difficulty of VCO based quantizer is pulled to the nonlinearity of the VCO gain. The voltage to frequency quantizer moreover provide inherent Dynamic Element Matching (DEM) without any extra circuits and pass on the nonlinear VCO characteristic as only source of reduce SNDR with minimum power and short excess delay [2]. Digital calibration is used to resist nonlinearity in open loop VCO based quantizer but first order noise shaping gets high over sampling ratios (OSRs) thus power consumption increased [3]. Linearity performance of VCO based quantizer has to be improve by using feedback, in the presence of high gain before the quantize minimize the nonlinearity of quantizer by using feedback path [4]. Frequency-to-current feedback (FC) structure effectively reduces the nonlinearity of VCO through negative feedback and also reduced harmonic distortion in the VCO based quantizer [5]. Single path multi feedback architecture decimates the need for static and dynamic element matching and degraded the requirement of OSR makes VCO based quantizer worthy for high frequency [6]. Soft rail approach provides inherent linearity and supply noise rejection also achieve high SNR in ring oscillator (RVCO). In this design phase noise of RVCO is reduced by increased in power dissipation. Thus TDC is used in the place of RVCO and maintains the power dissipation [7]. Quadrature voltage controlled oscillator (QVCO) is achieve low phase noise with high performance and minimum power consumption due to two parallel differential LC-tank VCOs with the coupling transistor instead of switch transistor [8]- [9]. Pulse frequency modulator (PFM) based VCO quantizer purposed novel architecture based on transconductor integrator with two different paths first is input

3 Implementation of a Multi bit VCO based Quantizer using Frequency 891 signal and second is oscillation frequency with low power dissipation [10]. Fig. 2. VCO based ADC [1] III. VCO BASED QUANTIZER USING FDC FDC VCO based quantizer built by using ring oscillator with parallel connection of several FDCs which are summed together and gives multibit VCO based quantizer as shown in Fig. 3. A. Ring Oscillator Fig. 3. Multibit VCO based quantizer Single ended ring oscillator used for designing VCO based quantizer in which inverter used as a delay. Single ended ring VCO has the highest frequency of oscillation and achieves minimum power. The VCO phase taps are delayed by 2π/None from to another, wheren shows the number of stages.single ended ring oscillator depicts in Fig. 4.

4 892 Anjali Jain and Pankaj M. Gulhane B. Design of FDC Fig. 4. Schematic of ring VCO Architecture of FDC consist two positive edge triggered D-flip flop and one 2 input XOR gate. FDC operates by clock signal, when a rising clock edge occur input signal samples by the first D-flip flop and gives output Q1, second D-flip flop takes the output of first D-flip flop before the next rising edge of clock signal. Outputs of both flip flop takes as inputs of XOR gate and give FDC output. Therefore, the FDC like an edge detector with some delay when transition is occur. In a positive edge triggered clock signal is connected to gate terminal of PMOS_1 and NMOS_2 respectively. When positive edge of clock signal is detected input signal D invert from PMOS_2 and NMOS_1 transistor and pass to the gate terminal of PMOS_3 and NMOS_3 transistor, at next stage when clock signal is low input signal invert from PMOS_3 and NMOS_3 transistor and gives output of D-flip flop which is improved by using output buffer. Positive edge triggered D-flip flop depicts in Fig. 5. Fig. 5. Positive edge triggerded D-flip flop

5 Implementation of a Multi bit VCO based Quantizer using Frequency 893 Another part of FDC is XOR gate build by using 4 transistors. 4 transistor XOR gate consumes less power and perform faster. Schematic of XOR gate depicts in Fig. 6. Fig transistor XOR gate FDC is the combination of D-flip flops and XOR gate as shown in Fig. 7. Fig. 7. FDC block C. FDC VCO based quantizer The FDC VCO-based quantizer is modeled and dissects using linear modeling to specify the resolution. As declared before, the FDC differentiates the VCO phase to obtain the VCO frequency. Here ring VCO provides the multiphase output to the FDC. The schematic of FDC VCO based quantizer depicts in Fig. 8.

6 894 Anjali Jain and Pankaj M. Gulhane Fig. 8. FDC VCO based quantizer IV. SIMULATION AND RESULT All design is to be simulated using cadence spectre at 90nm technology with power supply 1.2V. Fig. 9 shows the simulation result of FDC. First output occurs when input of FDC changes 0 to 1. At the high clock signal after this transition output of positive edge triggered DFF1Q1, changes from 1 to 0. The value of the second DFF2 output, Q2, takes on the value of Q1 before that high clock signal. The XOR gate takes Q1 andq2 as an input and gives output when Q1 and Q2 is 0 and 1 vice versa; output of XOR gate shows the quantization error thus FDC work as an edge detector with some delay. Fig. 9. Waveform of FDC Fig. 10 shows the waveform of multi-bit VCO based quantizer. The FDC VCO based quantizer design using linear modeling to ascertain resolution.

7 Implementation of a Multi bit VCO based Quantizer using Frequency 895 Fig. 10. Waveform of multi-bit VCO based quantizer FDC linear modeling compresses the nonlinearity of quantizer and improves the resolution by using FDC block as a feedback. Fig. 11 shows the Discrete Fourier transform of output signal. FDC reduce the harmonic distortion and improve the SNR and SNDR. Fig. 11. DFT of multi-bit VCO based quantizer SNDR of VCO based quantizer at input frequency 10MHz is 66.38DB and at 20MHZ is 46.37dB, thus SNR of VCO based quantizer is reducing with increasing input frequency. TABLE I. enlists the parameters of VCO based quantizer in terms of input bandwidth, sampling frequency (fs), SNDR and power dissipation.

8 896 Anjali Jain and Pankaj M. Gulhane TABLE I. SUMMARY OF FDC VCO BASED QUANTIZER Design Specification Input badwidth Sampling frequency (fs) SNDR/SNR Parameter Value 10MHz 100MHz 66.38dB/72.21dB Power Dissipation 158.3µW Comparison of FDC VCO based quantizer with previous work is shown in TABLE II in which power dissipation reduces81% and also improved SNDR. Fig. 12 shows the layout of multi-bit VCObased quantizer. TABLE II. COMPARISION OF PREVIOUS WORK WITH FDC VCO BASED QUANTIZER Ref. No. Input bandwidth SNDR Power Dissipation [3] 4MHz 78dB 16mW [4] 10MHz 72dB 40mW [5] 20MHz 65dB 10mW [8] 1MHz 56dB 5mW This Work 10MHz 66dB 158µW Fig. 12. Layoutof multi-bit VCO based quantizer

9 Implementation of a Multi bit VCO based Quantizer using Frequency 897 V. CONCLUSION In this paper, VCO based quantizer design using FDC at 90nm technology. FDC used as a feedback and improve the SNR/SNDRand resolution improves by using ring oscillator. VCO based quantizer achieves low power at 10MHz input bandwidth. FDC design by using linear modeling and reduced nonlinearity of VCO based quantizer. FDC VCO based quantizer has single order noise shaping. FDC VCO based quantizerhas some drawbacks such as VCO nonlinearity and phase noise along with sampling clock jitter. REFERENCES [1] S. Yoder, MD Ismail and W. Khalil, VCO-Based Quantizers Using Frequency-to-Digital and Time-to-Digital Converters, SpringerBriefs in Electricaland Computer Engineering, 2011, pp [2] B. Yousefzadeh, MD Sharifkhani An Audio Band Low Voltage CT-ΔΣ Modulatorwith VCO-Based Quantizer, IEEE International Conference on Electronic, Circuits and system, 2011, pp [3] K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar and P. K. Hanumolu, A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC UsingResidue- Cancelling VCO-Based Quantizer, IEEE Solid State Circuit Conference, February 2012, pp [4] Z. Matthew. Straayer and Michael H. Perrott, Member, A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΔΣ, ADC With a 5-Bit, 950-MS/s VCO-Based QuantizerMultiplexer and Pass Transistor Logic, IEEE JOURNAL OF SOLID-STATE CIRCUITS,April 2008, pp [5] S. Park, H. Ryu, Eun-Taek Sung, and D. Baek, A Multi-bit VCO-based Linear Quantizer with Frequencyto-current Feedback using a Switchedcapacitor Structure, IEIE Transactions on Smart Processing and Computing, June 2015, pp [6] R. Naiknaware and T. Fiez, Time-Referenced Single-Path Multi-bit ΔΣ ADC using avco based Quantizer, IEEE, 1999, pp [7] N. Narasimman and T. Tae-Hyoung Kim, Design Challenges for VCO based ADCs for Ultra-Low Power Operation, IEEE ISOCC, 2013,pp [8] Y.-H. Chuang, S.-H. Lee, R.-H. Yen and S.-L. Jang, A Low-Voltage Quadrature CMOS VCO Basedon Voltage-Voltage Feedback Topology, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, DECEMBER 2006, pp [9] S-L Jang, Chia-Wei Chang, Chih-Chieh Shih, andching-wen Hsue,

10 898 Anjali Jain and Pankaj M. Gulhane QUADRATURE VCO BASED ON ANLC-RING IN 0.18-lm CMOS TECHNOLOGY, MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, February 2012, pp [10] E. Gutierrez, L. Hernandez and Ulrich Gaier, Sergio Walter, Liang Zou, A Low Power and Low Distortion VCO based ADCusing a Pulse Frequency Modulator, IEEE, 2014, pp