FPGA-based Low Latency Inverse QRD Architecture for Adaptive Beamforming in Phased Array Radars

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1 RADIOENGINEERING, VOL. 6, NO. 3, SEPTEMBER FPGA-baed Low Lateny Invere QRD Arhiteture for Adaptive Beamforming in Phaed Array Radar Raafia IRFAN, Haroon ur RASHEED, Waqa Ahmed TOOR Dept. of Eletrial Engineering, Pakitan Int. of Eng. and Applied Siene (PIEAS), Nilore, Ilamabad-45650, Pakitan Dept. of Eletrial Engineering, Capital Univerity of Siene and Tehnology (CUST), Expre Way, Zone 5, Ilamabad-45650, Pakitan Submitted November 7, 06 / Aepted July 7, 07 Abtrat. The main objetive of thi paper i to failitate the adaptive beamforming whih i one of the mot hallenging tak in phaed array radar reeiver. Reurive leat quare (RLS) i onidered a the mot well uited adaptive algorithm for the appliation where beamforming i mandatory, beaue of it good numerial propertie, high onvergene rate and low miadjutment. In thi paper, ome RLS variant are diued and the mot numerially uitable algorithm Invere QR deompoition (IQRD) i eleted for effiient adaptive beamforming. A novel arhiteture for IQRD RLS i alo preented, whih offer low lateny and low area oupation for Field Programmable Gate Array (FPGA) implementation. Thi approah redue the omputation by utilizing the tandard pipelining methodology. Hene, effiient adder and multiplier and Look Up Table (LUT) baed olution for quare root and diviion, ha highly enhaned the performane of the algorithm. The propoed IQRD RLS arhiteture ha oded in Verilog and analyzed it performane in term of throughput, hardware reoure and effiieny. Keyword Adaptive filter, beamforming, phaed-array radar, Reurive Leat Square (RLS), Invere QR Deompoition (IQRD), Field Programmable Gate Array (FPGA). Introdution Radar ignal proeing i one of the ative area of reearh due to it vat appliation in radar ytem like target traking, navigation. Mot of the radar ytem are ompoed of multiple tranmitting and reeiving phaed array antenna, known a phaed array radar. Thee phaed array antenna are deigned to tranmit and reeive the patially propagating ignal and to fou on the arriving diretion of deired ignal a well a uppreed the interfering ignal [], []. Beamforming i an important ignal proeing tehnique in phaed array radar for diretional ignal tranmiion or reeption []. Figure how a generalized blok diagram of four-hannel adaptive beamformer reeiver having a uniform linear array truture (ULA) and an adaptive weight alulation (AWC) unit. In ULA, phaed array radar, all the antenna element are arranged along a line with uniform paing, to attenuate interferene oming from different diretion along with deire ignal [3]. AWC unit i baed on an over determined ytem of equation in many ae and variou algorithm ha been developed to olve thee equation. Suh a ytem i alo known a adaptive antenna ytem. AWC uually baed on gradient baed adaptive algorithm like Leat Mean Square (LMS), Normalized Leat Mean Square (NLMS), Reurive Leat Square (RLS), Kalman filter, auming all the input ignal to ULA ytem are unorrelated with eah other [3], [4]. But, RLS i onidered a the mot ommonly ued algorithm a it ha the fat onvergene rate to find an appropriate olution and good numerial propertie, but it ha omplex mathematial operation like matrix inverion. Hene, it limit it appliation in real time ytem [5]. In numerial method, a well-known method known a QR deompoition (QRD) i ued to deompoe any matrix into orthogonal matrix Q (QQ T = I), and upper triangular matrix R ( = QR). So, to overome the omputational omplexity, variou QR deompoition baed RLS variant (QRD, Invere QRD, Fat QRD) were developed, whih are widely ued in variety of appliation, whih lead to more effiient arhiteture, tability and auray [5], [6]. In the paper, the omparion of few RLS variant are performed and elet IQRD RLS a the leat omputationally expenive algorithm for hardware appliation. The primary goal of thi paper i to propoe and develop a high-throughput arhiteture of the eleted RLS variant, by minimizing it lateny and devie area oupation for adaptive beamforming appliation. The peed of the beamformer i limited due to reurive operation baed AWC unit, therefore, minimizing lateny i a ritial iue [4], [7]. In thi paper, a novel arhiteture i propoed for IQRD RLS to redue the omputational omplexity by uing the tandard pipelining methodology and mapped into Virtex5 FPGA beaue it provide the powerful om- DOI: 0.364/re SYSTEMS

2 85 R. IRFAN, H. RASHEED, W. A. TOOR, FPGA-BASED LOW LATENCY IQRD ARCHITECTURE FOR ADAPTIVE BEAMFORIMG ignal x x x 3 x 4 w 4 w 3 w w + AWC Core Fig.. Adaptive beamformer reeiver with ULA truture. putational arhiteture feature for floating point arithmeti. The paper i organized a follow: firt of all, a brief introdution of adaptive beamforming i preented in Se.. Further, in Se. 3, a thorough tudy i performed to elet IQRD a the mot uitable RLS variant. Setion 4 deribe the onventional ytoli array arhiteture and the propoed new arhiteture baed on low lateny module. Finally, in Se. 5, AWC unit implementation in Virtex 5 FPGA i diued to onfirm the advantage of the new truture.. Adaptive Beamforming The ore of adaptive beamformer reeiver i to detet and etimate the target ignal at the input of adaptive antenna array. Suh ytem are uually onited of an antenna array along with adaptive proeor (AWC) to adjut it weight in real time, uh that the main lobe of the radar i foued on the arriving diretion of target ignal and uppree undeired ignal [3], [6]. The output of beamformer in Fig. i given a: e( k) d( k) z ( k) () where z be the vetor array of etimated ignal given a w z () where w (m ) be weight vetor, (m N, m > N) i the input data matrix, d (N ) i the deired training ignal and e (N ) i the additive noie error vetor. The primary goal of the adaptive beamformer i to minimize the mean quare error, uh that z(k) d(k) and find out the optimized value of unknown weight vetor w. k k i T d w x e (3) i0 ( k) () i () i ( k) ( k) where λ i a forgetting fator in onventional RLS [4]. 3. RLS Variant for Adaptive Beamforming In thi etion, a detail tudy of RLS variant i performed to elet the mot effiient one for the AWC unit in z d + e adaptive beamformer. But, firt of all a brief introdution of QR deompoition baed on Given Rotation (GR) method i given. A GR rotation matrix G i ued to premultiply a two-row matrix and tranformed it into upper triangular matrix. Let two-row matrix be given a: r r... r m A. (4) x x... xm Premultiplying matrix A with G we get where r r... r r r... r m m x 0 x... x x... x m m r x (5) r, (6) r r x x, (7). (8) r x In [7], a numerially table RLS variant QRD RLS, i deribed whih avoid the omplex matrix inverion operation. Moreover, it ha the poibility of implementation in ytoli array arhiteture (pipelined arhiteture). Hene, many reearher onidered QRD RLS a the mot uitable adaptive algorithm for hardware implementation [8 0]. The QRD deompoe input data matrix through an orthogonal triangularization approah like Given rotation (GR), Houeholder tranformation or Gram Shmidt orthogonalization [] QR. (9) In mot of the ae GR i onidered a the mot numerially well-onditioned method. Q be the unitary matrix (QQ T = I) generated a the equene of Given rotation matrie in [], and R i the upper triangle matrix whih i alo the Choleky fator of autoorrelation matrix R= T []. So, equation (9) an be written a: Q R (0) Premultiplying () with Q we get Qe Qd Qw. () Let e = Qe and d = Qd, o equation () an be written a e d Rw. () From () the weight update equation an be written a w R d, e 0. (3) The above equation i the olution of leat quare problem whih i obtained by bak ubtitution proe. Hene, the QRD RLS algorithm i ompoed of two tep: firt the QR

3 RADIOENGINEERING, VOL. 6, NO. 3, SEPTEMBER x 0 tart BC r_new x tart x d Algorithm Computational Weight Update Complexity Proedure QRD RLS O(N ) Bak Subtitution IQRD RLS O(N ) Within Sytoli array FQRD RLS O(N) No Proedure r 00 r 0 r 0 z 0 Tab.. Propertie of RLS variant. tart BC r_new r Fig.. QRD RLS ytoli array. tart r tart BC r_new r 00 z Bak Subtitution w z tart r_new deompoition of data matrix (9) i performed and ha ytoli realization. In tep, bak ubtitution proe begin for weight alulation (3), a hown in Fig.. IQRD RLS i another important variant of RLS propoed by Alexander and Ghirnikar [], to avoid the numerially tediou bak ubtitution proe for weight alulation. The ore idea i to update the invere matrix R (3) in eah iteration of ytoli array. So, the weight of filter are omputed within ytoli array. In [], a new weight update equation i derived whih i given a: T ( k) ( k ) ( k) w w e R ( k) R ( k) x ( k) (4) where the term R - (k)r -T (k)x(k) i known a the Kalman gain. The ytoli realization of IQRD RLS will be diued in Se. 3. Hene, IQRD RLS i le omputationally expenive a ompared to QRD RLS. In Fat QRD (FQRD) RLS, matrix update equation i replaed by vetor update equation. In [] detail derivation of thee equation are given, whih further redue the numerial omplexity a ompared to QRD RLS and IQRD RLS algorithm. Although, FQRD RLS i numerially le omplex, but it ha no weight update proedure, o it i limited to appliation whih try to etimate the output error vetor [3]. In thi etion, three important RLS variant and their propertie are diued and ummarized in Tab. I. It i worth mentioning that QRD and IQRD are omputationally more omplex than FQRD, but FQRD ha no weight update proedure. So, we annot onider it for adaptive beamforming appliation. On the other hand, QRD involve more omputation (two tep proedure) o it i alo not preferable. Due to above reaon, IQRD RLS i the well-uited algorithm for hardware implementation. 3. Performane Analyi of Adaptive Beamforming in Term of Radiation Pattern The performane analyi of adaptive beamforming, uing RLS adaptive algorithm i done by varying different beamformer parameter. Reearher have performed the analyi of adaptive beamformer for mart antenna baed on adaptive algorithm Leat Mean Square (LMS), Sample Matrix Inverion (SMI), Reurive Leat Square (RLS) and Conjugate Gradient Method (CGM). The analyi i done by varying the inter element paing and the number of antenna element for eah algorithm and tudying the radiation pattern, amplitude repone, mean quare error and abolute weight for adaptive beamforming algorithm [4], [5]. We aume a ULA beamformer with an operating frequeny of GHz. It reeive an eho ignal from the ingle target at azimuth of 30 and an interferene ignal at 45. Simulation how that the RLS adaptive algorithm rejet the interferene at 45 and enhaned the target ignal at 30. The following proedure are adopted for further analyi of RLS baed adaptive beamformer: Change the number of antenna element. Change the antenna element inter pae. Figure 3 depit the performane of beamformer with different number of antenna element. The eleted number of antenna are 0, 5 and 0. It i lear from the radiation pattern that when the number of antenna inreae the main lobe of the beamformer i hrinked and pointed aurately toward the target angle and the ide lobe are muh uppreed. On the other hand, the perfor- Fig. 3. Radiation pattern with different number of antenna N.

4 854 R. IRFAN, H. RASHEED, W. A. TOOR, FPGA-BASED LOW LATENCY IQRD ARCHITECTURE FOR ADAPTIVE BEAMFORIMG Reearher have performed a lot of work to find a quareroot and diviion free BC unit for ytoli array. In [9], the following data tranformation are applied to eek the quare-root and diviion free expreion for tranformed data. r a, x b, r a, j,,..., m,(7) j j j j j j xj bj, j,3,..., m. (8) Fig. 4. Radiation pattern with different inter antenna element pae D. mane i alo judged in term of hanging antenna element inter pae. The eleted inter pae are 0.5,.5 and.5 mm. Figure 4 i the reulting radiation pattern in whih the performane of the adaptive beamformer i improved a the ditane between the antenna element are inreaed. The ide lobe are alo uppreed in a muh better way. Hene, the RLS baed adaptive beamformer ha a good performane and auray a the number of antenna element are inreaed a well a the ditane between eah antenna element i alo inreaed. 4. IQRD Sytoli Array Arhiteture Sytoli array are the well-known onept for matrix triangularization and inverion [6], [7] and the ame idea i adopted for IQRD-RLS algorithm. Figure 5 how the onventional ytoli realization of the IQRD-RLS algorithm. The IQRD ytoli triangular array onit of four type of proeing ell; Boundary Cell (BC), Internal Cell (), Invere Internal Cell (I) and Final Cell (FC). A Boundary Cell determine the rotation parameter o α and in α to perform the rotation on input omplex data row x, from data matrix and update the orreponding row value of R matrix whih i an upper triangular matrix. It alo end the rotation parameter to the right neighboring Internal Cell [6], [8]. The orreponding equation (6), (7) and (8) are modified a: o in r r x r x x, (5). (6) BC i more omplex than, I and FC beaue it perform quare-root and invere operation. All the other ell perform only multipliation and invere operation. However, the number of multipliation i inreaed due to thee tranformation, but it i a good approah to improve the ytem lateny and redue number of omputation. In [8], another ingle yle look-up table (LUT) baed approah i ued to replae the quare root and invere operation and to optimize the QRD RLS lateny. Thi approah give muh improvement in overall performane of QRD RLS algorithm. An Internal Cell () reeived the rotation parameter o α and in α from the Boundary Cell (BC) in eah row, and performed the rotation on the input value of data matrix and updated the x and r value. The orreponding update equation are given a follow [6], [7]: r r x, (9) n x x r. (0) n Invere Internal Cell reeive the ine and oine value of the rotation angle from the internal ell in the ame row. Some part of the invere internal ell operation i imilar to the internal ell; i.e. it rotate the input data by multiplying it with input rotation angle. Along with thi operation, Invere internal node of IQRD-RLS ue λ ( ½) in () and (3). In thi paper, we onider the ae when λ =, o that I i equivalent to unit. Final Cell (FC) perform two funtion: it reeived the rotation parameter o α and in α to rotate the input data and generate the updated filter weight uing the following relation [0] w ( ) r x () where γ i omputed uing the following relation N ( k) o ( k). () i0 A deign methodology ha been propoed to optimize the throughput and lateny of the IQRD-RLS arhiteture. In Fig. 6, a blok diagram of the propoed arhiteture i preented, whih utilize the tandard pipelining methodologie and ha 50% redution in number of BC, and I unit (Tab. ). We have further optimized the IQRS RLS arhiteture, by omitting the quare-root and diviion operation in BC, in term of ingle yle ingle yle look up table (LUT) a hown in Fig. 7. Generally, a look up table i

5 RADIOENGINEERING, VOL. 6, NO. 3, SEPTEMBER Fig. 5. Conventional IQRD ytoli array. Fig. 6. The propoed IQRD arhiteture.

6 856 R. IRFAN, H. RASHEED, W. A. TOOR, FPGA-BASED LOW LATENCY IQRD ARCHITECTURE FOR ADAPTIVE BEAMFORIMG (LUT) i a table that determine what the output i for any given input. In FPGA truth table are ued to implement any digital logi. In [8], the ame methodology i adopted for QRD RLS algorithm. Thi heme avoid the omplex hardware implementation with oniderable dereae in lateny and improve the peed of overall ytem. In ome previou work the onventional implementation of BC i baed on CORD algorithm, for non-reurive appliation [0], []. But, digital beamforming i a reurive proedure, o, the onventional approah would not pay off beaue it lead to oniderable lateny. In the propoed arhiteture, the pipelined regiter (R_reg, x_reg, Rinv_reg) are introdued whih not only hold the updated value, but alo feedbak them to BC, and I ell. The ontroller CON handle the ontrol ignal a well a feedbak timing. Hene equation (5) and (6) an be modified a: i r A r x r x x, (3) x, (4) A A r, Ai r A i, (5) x A, x A. (6) i i i r r r The unit reeived the, i and r value from neighboring BC to ompute (9) and (0) and update the value of x ni, x nr and r n. Thee omputation required only adder and multiplier unit a hown in Fig. 8. The updated value x ni, x nr are tored in pipelined regiter x_reg and alo feedbak to module, and updated r n i tored in internal memory of. The, i and r are alo ent to the neighboring (Fig. 8). One of the major differene between the LUT implemented in [8] and in thi paper, i the floating-point repreentation format. In [8], the lateny optimization of LUT i diued with a defined N bit fixed point number format, inluding ign bit, i integer bit (i > ) and f fra- Data matrix [ize] Fig. 8. Internal ell () arhiteture. Conventional Arhiteture No. of BC No of No of I Propoed Arhiteture Conventional Arhiteture Propoed Arhiteture Conventional Arhiteture Propoed Arhiteture Tab.. Comparion between the propoed and onventional IQRD arhiteture. tion bit (f > ). But, the floating-point multiplier and adder are not diued with the new defined number format. In thi paper, we have utilized the ame LUT approah for IQRD RLS arhiteture with ingle preiion IEEE 754 format due to it wider range over fixed point. The ingle-preiion number are tored in 3 bit: for the ign, 8 for the exponent, and 3 for the fration []. In the propoed arhiteture, the omputation of A i and A are handled in ingle LUT, wherea A i the 3-bit input addre field to the LUT a hown in Fig. 7. Simulation reult how that 97% of the A value are greater than a Fig. 7. Boundary Cell (BC) arhiteture. Fig. 9. (a) Hitogram of A. (b) Hitogram of A i.

7 RADIOENGINEERING, VOL. 6, NO. 3, SEPTEMBER hown in Fig. 9a, when the all input variable in (3) have a typial uniform ditribution within the range of [ 4, 4], and their orreponding output value (A i ) are very mall (Fig. 9b). Hene, probability of ourring a value le than i very low thu redue the range of input value A for LUT. The output of the LUT A i ha 3-bit bandwidth, whih i ued to ompute the, i and r value, for the unit. 5. Implementation and Reult In thi paper, we have optimized the BC module of ytoli array in term of omplex mathematial operation. Many reearher alo performed a lot of work in ingle preiion floating point multiplier whih i alo a omplex mathematial operation in hardware [3 5], but we keep our fou in divider and quare-root operation and ue the multiplier ore of the FPGA. ilinx Virtex 5 FPGA i the eleted platform for hardware implementation. A we have already diued, adaptive algorithm i a bai part of the beamforming ytem and we elet the IQRD-RLS algorithm a the mot uitable algorithm. Three type of arhitetural module are deigned to judge the performane of algorithm in term of lateny, throughput (ample/lok Time lok yle), error and effiieny (throughput/number of lie). The detail are:. MD 0 (module 0), a onventional ytoli array arhiteture with ingle preiion floating point multiplier, divider and a quare root module (generated with Coregen oftware).. MD (module ), a propoed ytoli array arhiteture with ingle preiion floating point multiplier, divider and a quare root module (generated with Coregen oftware). 3. MD (module ), a propoed ytoli array arhiteture with LUT baed BC for divider and quare root operation. where MD tand for module. A radar target detetion enario i imulated in MATLAB to generate the data point for the teting of MD 0, MD and MD. Firt, a radar reeived ignal i modelled having one target at azimuth angle 30, and two interferene at azimuth 5 and 45, repetively. Aume that both target and radar lie at the ame; i.e. elevation angle i equal to zero. Figure 0 how the radiation pattern. The reeived ignal i impinged on 3 element ULA beamformer baed phaed array radar to generate almot 0 4 data point. In adaptive beamforming appliation, lateny i an important performane metri whih affet the overall ytem throughput. To judge the LUT effet on algorithm performane we ompare the latenie and throughput of the arhitetural module. Table 3 detail the lateny of eah unit in ytem individually, and throughput of adaptive filter (3-tap) for IQRD-RLS algorithm with three different arhitetural module; i.e. MD 0, MD, MD. Thee module are modelled uing Verilog and their behavior deription i plaed and routed on Virtex5 devie by ISE4.i tool. It i lear from Tab. 3, the propoed arhiteture baed module MD module ha offered 9 time redution in lateny a ompared to MD 0 and MD module beaue of it optimized ingle yle LUT baed arhiteture. On the other hand, MD module of IQRD-RLS ha a higher throughput a ompared to QRD-RLS M module. It i again important to notify that in [8], QRD- RLS i implemented uing a new floating point format, wherea we implement the IQRD-RLS with tandard IEEE-754 ingle preiion floating point repreentation. Hene, it i again proved that IQRD-RLS i the mot uitable algorithm for adaptive beamforming appliation. Algorithm auray of the propoed arhiteture and in preene of LUT i found out by meauring the differene between the weight oeffiient of the ideal method and the propoed method in MD with 0 4 imulated ample. Thi i alo known a weight error. Reult how that the weight error i le than for 96% ample. Figure illutrate the filter weight of the ideal and propoed method for 3 tap beamformer (For larity of the image we plot only 00 iteration). The devie utilization detail or hardware ummary are given in Tab. 4. It i noteworthy that MD outperform in term of area effiieny and throughput. The onventional arhiteture MD 0 ha the highet area effiieny, while MD oupie muh leer area a ompared to MD 0. The hardware effiieny and throughput are found out to draw a reaonable omparion between the arhiteture. To the bet of our knowledge, thi i the firt implementation of IQRD RLS algorithm in FPGA, o, the performane of MD i alo meaured, after it i yntheized for different target FPGA a hown in Tab. 5. The throughput of the IQRD propoed arhiteture in all FPGA i better than the QRD [8]. Hene, imulation reult have learly indiated that the IQRD RLS i the mot uitable algorithm for adaptive beamforming due to it better throughput, hardware effiieny and lateny. Fig. 0. Radiation pattern.

8 858 R. IRFAN, H. RASHEED, W. A. TOOR, FPGA-BASED LOW LATENCY IQRD ARCHITECTURE FOR ADAPTIVE BEAMFORIMG Referene [] FENN, A. J. Adaptive antenna and phaed array. Leture MIT Linoln Laboratory, Available at: /leture8/leture.pdf [] MAILLOU, R. J. Phaed Array Radar Handbook. nd ed., rev. London (UK): Arteh Houe, 005. ISBN: [3] FLORENS, C., RAIDA, Z. Adaptive beamforming uing geneti algorithm. Radioengineering, 998, vol. 7, no. 3, p. 6. [4] HAYKIN, S. O. Adaptive Filter Theory. 4 th ed., Prentie Hall, 003. (p , ) ISBN: Fig.. Weight error. Algorithm IQRD RLS QRD RLS [8] Module MD 0 MD MD Module M BC BC FC Total Total 76 Throughput [MSample/e] Throughput [MSample/e] Tab. 3. Comparion between IQRD and QRD [8] lateny and throughput. Hardware Reoure MD 0 MD MD Slie 6% 8% 3% 4-input LUT 8% 4.4% 5% DSP48 55% 4% 5% ROM 0% 0% 5% Avg. Area 38.%.6% 3.9% Area Effiieny Tab. 4. Hardware reoure. No. Sytem Slie. Throughput. Spartan-3 (ex3500) Virtex-4 (vx55) Virtex-5 (vtx50) Tab. 5. Comparion between FPGA. 6. Conluion.45 A low lateny arhiteture i preented that implement the IQRD algorithm for beamforming appliation uing ytem level hardware tool. The propoed arhiteture improve the divider and quare root operation via LUT approah. Moreover, it i mapped in Virtex5 FPGA by ilinx and ahieved the minimum error between the real and ideal weight value. Hene, the propoed arhiteture i outperforming in term of area effiieny, throughput, and lateny, and the mot uitable algorithm for adaptive beamforming. In future work, the multiplier and adder unit an be implemented via LUT, for further improvement in lateny and throughput. [5] DINIZ, P. S. R. Adaptive Filtering: Algorithm and Pratial Implementation. nd ed. USA: Kluwer Aademi Pre, 997. (p ). DOI: 0.007/ [6] JIAN LI, STOA, P. Robut Adaptive Beamforming. Wiley Serie in Teleommuniation and Signal Proeing, 006, (p ). ISBN: [7] MCWHIRTER, J. G. Reurive Leat Square Minimization uing a Sytoli Array. Pro SPIE 043, Real-time Signal Proeing VI, 983, vol. 43 (p. 05 ). DOI: 0.7/ [8] ALIZADEH, M. S., BAGHERZADEH, J., SHARIFKHANI, M. A low lateny QRD RLS arhiteture for high throughput appliation. IEEE Tranation on Ciruit and Sytem, 06, vol. 63, no. 7 p DOI: 0.09/TCSII [9] DESHPANDE, A. P., MURTHY. N. S., GOVIND RAO, D., et al. Effiient filter implementation uing QRD-RLS algorithm for phaed array radar appliation. In IEEE International Conferene for Tehnologial Advane in Eletrial, Eletroni and Computer Engineering (TAEECE). Konya (Turkey), 03. DOI: 0.09/TAEECE [0] MARTINEZ, M. E. I. Implementation of QRD RLS algorithm on FPGA: Appliation to Noie Caneller Sytem. IEEE Latin Ameria Tranation, 0, vol. 9, no. 4, p DOI: 0.09/TLA (in Spanih) [] APOLINARIO Jr., J. A. (Ed.) QRD RLS Adaptive Filtering. New York (USA): Springer Media, 009. (p. 5 3). DOI: 0.007/ [] ALEANDER, S. T., GHIRNIKAR, A. L. A method for reurive leat quare filtering baed upon an invere QR deompoition. IEEE Tranation on Signal Proeing, 993, vol. 4, no., p DOI: 0.09/TSP [3] SHOAIB, M., WERNER, S., APOLINARIO JR., J. A., et al., Equivalent output-filtering uing Fat QRD-RLS algorithm for burt-type training appliation. In IEEE International Sympoium on Ciruit and Sytem (ISCAS). Iland of Ko (Greee), 006, DOI: 0.09/ISCAS [4] SAENA, P., KOTHARI. A. G. Performane analyi of adaptive beamforming algorithm for mart antenna. IERI Proedia (peial iue International Conferene on Future Information Engineering), 04, vol. 0, p DOI: 0.06/j.ieri [5] AZIZ, A., QURESHI, M. A, JUNAID IQBAL, J., et al. Performane and quality analyi of adaptive beamforming algorithm (LMS, CMA, RLS & CGM) for mart antenna. In IEEE 3 rd International Conferene on Computer and Eletrial Engineering (CEE). Chengdu (China), 00, p. V6-30 V ISBN: [6] GENTLEMAN, W. M., KUNG, H. T, Matrix triangularization by ytoli array. Pro. SPIE Real-time Signal Proeing, 98, vol. 98, p DOI: 0.7/.93507

9 RADIOENGINEERING, VOL. 6, NO. 3, SEPTEMBER [7] MILOVANOV, E. I., STOJCEV, M. K., MILOVANOV, I. Z., et al. Deign of linear ytoli array for matrix multipliation. Advane in Eletrial and Computer Engineering (AECE), 04, vol. 4, no., p DOI: 0.436/AECE [8] TANG, C. E. T., LIU, K. J. R., TRETTER, S. A. Optimal weight extration for adaptive beamforming uing ytoli array. IEEE Tranation on Aeropae and Eletroni Sytem, 994, vol. 30, no., p DOI: 0.09/7.76 [9] FRANTZESKAKIS, E. N., LIU, K. J. R. A la of quare root and diviion free algorithm and arhiteture for QRD baed adaptive ignal proeing. IEEE Tranation on Signal Proeing, 00, vol. 4, no. 9, p DOI: 0.09/ [0] KARKOOTI, M., CAVALLARO, J. R., DK, C. FPGA implementation of matrix inverion uing QRD-RLS algorithm. In Conferene Reord of IEEE 39th Ailomar Conferene on Signal, Sytem and Computer. Paifi Grove (CA, USA), 005, p. 65 to 69. DOI: 0.09/ACSSC [] YHONG, T. M., MADHUKUMAR, A. S., CHIN, F. QRD-RLS adaptive equalizer and it CORD-baed implementation for CDMA ytem. International Journal on Wirele and Optial Communiation, 003, vol., no., p DOI: 0.4/S [] HOLLASCH, S. IEEE Standard 754 Floating Point Number. Available at: [3] RAMESH, A. P, TILAK, A. V. N., PARSAD, A. M. An FPGA baed high peed IEEE-754 double preiion floating point multiplier uing Verilog. In 03 International Conferene on Emerging Trend in VLSI Embedded Sytem, Nano Eletroni and Teleommuniation Sytem (EVENT). Tiruvannamalai (India), 03. DOI: 0.09/EVENT [4] KODALI, R. K, GUNDABATHULA, S. K., BOPPANA, L. FPGA implementation of IEEE 754 floating point Karatuba multiplier. In International Conferene on Control, Intrumentation, Communiation and Computational Tehnologie (CCT). Kanyakumari (India), 04. DOI: 0.09/CCT [5] PALDURAI, K., HARIHARAN, K. FPGA implementation of delay optimized ingle preiion floating point multiplier. In IEEE International Conferene on Advaned Computing and Communiation Sytem (ACCS). Coimbatore (India), 05. DOI: 0.09/ACCS About the Author... Raafia IRFAN ha reeived her MS degree in Eletroni from Quaid-e-Azam Univerity (QAU) in 004 and done her MS Sytem Engineering from the Pakitan Intitute of Engineering and Applied Siene (PIEAS) in 006. Currently, he i working toward the Ph.D. degree in Eletrial Engineering from PIEAS. For lat 0 year, he i working a a enior ientit in a reearh organization. Her expertie and reearh interet are FPGA baed ommuniation ytem deign, radar ignal proeing and high peed VLSI deign. Haroon-ur-RASHEED i a enior faulty member at the Department of Eletrial Engineering, Pakitan Intitute of Engineering and Applied Siene (PIEAS). He ha done hi Bahelor in Eletrial Engineering from the Univerity of Engineering and Tehnology (UET) Lahore in 990 and ompleted hi mater from Iowa State Univerity (ISU), USA. He ompleted hi Ph.D. from the Shool of Computer Siene & Tehnology, Beijing Intitute of Tehnology in 009. At PIEAS he ha taught oure in Digital Deign in Verilog, Digital Communiation, Miroproeor baed Deign and Digital Image Proeing. He ha upervied many final year projet at NUST a well a PIEAS during hi areer a a teaher. He and hi tudent have publihed a number of reearh paper in international onferene before tarting PhD tudie at BIT. He i alo a profeional member of IEEE. Waqa Ahmed TOOR did hi Bahelor in Eletrial Engineering from NUST in 003. He reeived hi MS Sytem Engineering degree from PIEAS in 006. Now he i doing hi MS leading to Ph.D. in Eletrial Engineering from the Capital Univerity of Siene and Tehnology (CUST). For lat ten year, he i working in an R&D organization a a Senior Engineer. Hi reearh interet are high power mirowave devie and their appliation, power eletroni and radar ignal proeing.