DIGIT-SERIAL COMPUTATION

Transcription

1 DIGIT-SERIAL COMPUTATION

2 TIlE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING Consulting Editor Jonathan Allen Other books in the series: FORMAL SEMANTICS FOR VHDL, Carlos Delgado Kloos ISBN: ON OPTIMAL INTERCONNECTIONS FOR VLSI, Andrew B. Kahng, Gabriel Robins ISBN: SIMULATION TECHNIQUES AND SOLUTIONS FOR MIXED-SIGNAL COUPLING IN INTEGRATED CIRCUITS, Nishath K. Verghese, Timothy J. Schmerbeck, David J. Allstot ISBN: MIXED-MODE SIMULATION AND ANALOG MULTILEVEL SIMULATION, Resve Saleh, Shyh-Jye, A. Richard Newton ISBN: CAD FRAMEWORKS: Principles and Architecutres, Pieter van der Wolf ISBN: PIPELINED ADAPTIVE DIGITAL FILTERS, Naresh R. Shanbhag, Keshab K. Parhi ISBN: TIMED BOOLEAN FUNCTIONS: A UNIFIED FORMALISM FOR EXACT TIMING ANALYSIS, William K. C. Lam, Robert K. Brayton ISBN: AN ANALOG VLSI SYSTEM FOR STEREOSCIPIC VISION, Misha Mahowald ISBN: ANALOG DEVICE-LEVEL LAYOUT AUTOMATION, John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley ISBN: VLSI DESIGN METHODOLOGIES FOR DIGITAL SIGNAL PROCESSING ARCHITECTURES, Magdy A. Bayoumi ISBN: CIRCUIT SYNTHESIS WITH VHDL, Roland Airiau, Jean-Michel Berge, Vincent Olive ISBN: ASYMPOTIC WAVEFORM EVALUATION, Eli Chiprout, Michel s. Nakhla ISBN: WAVE PIPELINING: THEORY AND CMOS IMPLEMENTATION, C. Thomas Gray, Wentai Liu, Ralph K. Cavin, III ISBN: CONNECTIONIST SPEECH RECOGNITION: A Hybrid Appoach, H. Bourlard, N. Morgan ISBN: BiCMOS TECHNOLOGY AND APPLICATIONS, SECOND EDITION, A.R. Alvarez ISBN: TECHNOLOGY CAD-COMPUTER SIMULATION OF IC PROCESSES AND DEVICES, R. Dutton, Z. Yu ISBN: VHDL '92, THE NEW FEATURES OF THE VHDL HARDWARE DESCRIPTION LANGUAGE, J. Berge, A. Fonkoua, S. Maginot, J. Rouillard ISBN: APPLICATION DRIVEN SYNTHESIS, F. Catthoor, L. Svenson ISBN :

3 DIGIT-SERIAL COMPUTATION by Richard Hartley General Electrical erd Keshab K. Parhi University 0/ Minnesota " ~. SPRINGER SCIENCE+BUSINESS MEDIA, LLC

4 ISBN DOI / ISBN (ebook) Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. Copyright 1995 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers, New York in 1995 Softcover reprint ofthe hardcover 1st edition 1995 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC Printed on acid-free paper.

5 Contents 1 Digit-Serial Architecture Data-Flow Architectures Synchronous Circuits Bit-Serial Architecture Comparison of Bit-Serial and Bit-Parallel Computation Bit-Serial Circuit Architecture Scheduling Timing Previous Values Digit-Serial Architecture Example Digit-Serial Circuit Digit-Serial Operators Arithmetic Operators Comparison Operators Logic Operators Constants Delay Operators Shift Operators Converters Timing Signal Generation Special Cells Layout Overview Bit-Slicing the Standard Cells Complete Chip Layout Digit-Serial Cell Design Digit-Serial Layout The Standard Template Delay Cells Deviation From The Standard Template The Add/Subtract/Compare Cell Division... 34

6 VI CONTENTS 2.3 Digit-Serial Shifting 2.4 Cordie Operators Multipliers Multipliers Parallel Array Multiplier Bit-Serial multiplication Signed Multiplication Serial Multiplication with Constant Word Length Size of the Multiplier Constant Multiplication Serial-Serial Multiplication Software Support Digit-Serial Multiplication Low Latency Multiplication 56 4 Digit-Serial Input Language Cells Leaf Cells Stack Cells Composite Cells Symbolic Cells Function Calls Adding New Functions Control Structures Standard Libraries Data Conversion Parallel/Serial Conversion Serial/Parallel Conversion Latches ROMs Static and Periodic Signals Examples Square Root Complex Arithmetic 90 5 Layout of Digit-Serial circuits Digit-Serial Cell Layout Conventions Layout of the Complete Chip Linear Layout Two-Dimensional Placement Chip Examples

7 CONTENTS vii 6 Scheduling Scheduling Solving The Programming Problem Previous Values and Feedback Loops Alternative Scheduling Method For z-l Operators Earliest-Possible Scheduling Swapping Multiplier Inputs Trees of Associative and Commutative Operators Algorithm for Optimizing Single Adder Trees Rearranging General Data-Flow Graphs Handling Subtractors Examples Why not other optimizations? Digit-Serial Performance Ripple-Carry Operators Look-Ahead Operators Improved Performance Through Unfolding An Example Bit-Level Unfolding Introduction Description of the Technique Operators With Latency Collapsing Outputs Automatic Unfolding Unfolding to Arbitrary Digit Sizes Parallel to Digit-Serial Converter The Folding Transformation Introduction Digit-Serial Design Using Folding Pipelining and Retiming For Folding Folding of Bit-Parallel to Bit-Serial and Digit-Serial Architectures Folding of Regular Data-Flow Graphs Digit-Serial Architectures by Unfolding Wavelet Transform Architectures Introduction The Wavelet Computation The Analysis Wavelet Architecture Life-Time Analysis Register Allocation

8 Vlll CONTENTS Digit-Serial Building Block The Synthesis Wavelet Architecture 11 Digit-Serial Systolic Arrays 11.1 Introduction Digit Serial Systolic Arrays 11.3 Design Examples Convolution Band Matrix Multiplication 11.4 The General Case - Theory Cell Specification Timing of the Whole Array Generating Digit-Serial Arrays Expanding the Period Finding the Minimum Digit-Size 12 Canonic Signed Digit Arithmetic 12.1 Canonic Signed Digit Format CSD Multiplication Pushing Subtractions Towards the Root Size of Adders Error Computation Bypassing Adders Sub-Expression Sharing Finding Common Sub-expressions Choice of Sub-expression An Example Routability Using the Two Most Common Sub-expressions 12.4 Carry-Save Arithmetic Carry-Save Subtraction Speed of a Carry-Save Multiplier Circuit Filters using Carry-Save Arithmetic 12.5 Asymptotic Occurrence of Pairs Number of n-bit CSD integers Number of non-zero bits in CSD integers Restricting the range of CSD integers Asymptotic frequency of non-zero bits Frequency of pairs Asymptotic frequency of pairs

9 CONTENTS IX 13 Online Arithmetic Redundant Data Formats Reduction of the Range of Digits Addition An Alternative Implementation Data Range and Overflow Reduction without Overflow Inhibition Reduction with Overflow Inhibition Overflow with the Alternative Reduction Scheme Radix-2 Carry-Free Addition Data Format Conversion Radix-2 Format Conversion Radix-2 Multiplication Architectures Doubly-Redundant Multiplier Architectures Singly-Redundant Multiplier Architectures Radix-4 and Higher Radix Multiplication Constant Multiplication Generalization to Higher Radices Variable-by-Variable Multiplication.. 288

10 Preface Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of realtime hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digitserial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory. Parsifal constitutes a complete design environment, including capabilities for simulation, fault-simulation, chip layout, layout verification and timing verification. However, this book limits itself to a description of the digit-serial architecture and design and layout synthesis methods used in Parsifal. The book goes beyond a description general digit-serial architectures (as embodied for instance in Parsifal) to discuss some wider-ranging issues in digitserial design. We discuss systematic methods for the design of digit-serial architectures and design elements in chapters on "folding" and "unfolding". In addition we include chapters on systolic arrays, canonic-signed-digit number representation and carry-save arithmetic from the viewpoint of digit-serial arithmetic. The emphasis of the book is on least-significant-digit (LSD) first digit-serial computation. However, much of the material applies as well to most-significantdigit (MSD) first arithmetic. MSD-first digit-serial arithmetic is often called online arithmetic, and has been a popular area of research. In on-line arithmetic, a redundant number representation is necessary to allow computation to proceed in a most-significant-bit first manner. The carry-free property of redundant number based architectures makes them ideal for high-speed implementation of DSP algorithms involving feedback loops, where minimization of loop latency is

11 important. Without attempting a comprehensive survey we include a chapter on on-line arithmetic as a way of introducing the reader to this interesting area. The book is organized as follows. The first five chapters relate most closely to the Parsifal design system. Chapter 1 introduces the digit-serial architecture and implementation methodology. Issues related to the design of digit-serial computational units, or cells are discussed in Chapter 2, leaving to Chapter 3 the discussion of design of digit-serial multipliers. The bit-serial language "BSL" used for describing DSP circuits in Parsifal is described in Chapter 4, and Chapter 5 describes the method of layout generation. Chapter 6 describes the scheduling algorithms used in Parsifal. These algorithms are also generally applicable to a wider class of synchronous designs. The remaining chapters are concerned with more general aspects of digitserial and related architectures. Chapter 7 analyzes the performance of digitserial circuits. Chapters 8 and 9 explore formal approaches to the design of digit-serial circuits using architecture transformations. They present methods for systematic design of digit-serial circuits from bit-serial and bit-parallel designs using unfolding and folding techniques, respectively. Chapter 10 presents a case study where the digit-serial methodology is shown to be ideal for implementation of discrete wavelet transforms. This chapter also considers approaches to register minimization in architectures using life-time analysis. Systolic arrays are considered in Chapter 11 where it is shown that they offer special advantages over bit-parallel implementations. In particular, complete hardware utilization may be achieved by replacing bit-parallel processing elements with digit-serial ones. This also reduces the area by the hardware under-utilization factor. Chapter 12 presents canonic signed digit representation and carry-save arithmetic as techniques for design of DSP circuits which consume less area and power. Finally, Chapter 13 addresses on-line arithmetic. xu Acknowledgment The authors gratefully acknowledge their colleagues who have contributed to the development of the Parsifal compiler or helped with the preparation of this book. The GE bit-serial compiler (BSSC, or Parsifal I) was developed at the GE Corporate Research and Development center by Sharbel Noujaim, Richard Hartley and Jeffrey Jasica with layout help particularly from Dan Locker. The Parsifal compiler is an extension of BSSC implementing the digit-serial design methodology. It was developed by Richard Hartley and Peter Corbett with design assistance from Steve Karr, Phil Jacobs and Kathy Panton. Richard Hartley thanks all these people for their help, but wishes to single out Sharbel Nouj aim, Peter Corbett and Jeff Jasica for particular thanks, and acknowledgment of their contribution to the development of the ideas presented in this book. Indeed much of the material of the book is derived from our joint publications. In addition, the section on tree-height reduction is derived from joint work with Albert Casavant. Thanks are also gratefully given to managers Ron

12 xiii Jerdonek and Manuel d'abreu for their support of this project, and to the many users of BSSC and Parsifal, particularly Fathy Yassa, for their suggestions and feedback. Keshab Parhi acknowledges Ching-Yi Wang's contributions to the unfolding algorithm and his help in preparation of the index. He is also grateful to Tracy Denk who generated many figures used in this book. Finally, we would like to thank Bob Holland and Kluwer Academic Publishers for their encouragement and help in producing this book.