Low Power Integrated Scan-Retention Mechanism

Transcription

1 Low Power Integrted cn-etention echnism Victor Zyun I T.J. Wtson eserch enter, Yorktown Heights, NY zyun@us.im.com tephen V. Kosonocky I T.J. Wtson eserch enter, Yorktown Heights, NY stevekos@us.im.com TT This pper presents methodology for unifying the scn mechnism nd dt retention in ltches which leds to scnnle ltches with the dt retention cpility chieved t very low power overhed during the ctive mode. detiled nlysis of power nd re overhed is presented, with lyout exmples for vrious common ltch styles. Implictions of using different power gting techniques for reducing lekge during sleep mode on the design of retention ltches re considered, including well ising for lekge control nd shring wells etween gted logic nd retention ltch devices. tegories nd uject escriptors.2.1 [esign tyles]: Pipeline;.6.1 [esign tyles]: equentil circuits;.7.1 [Types nd esign tyles]: VL Generl Terms esign Keywords dt retention, TO, suthreshold, lekge, low power, ltch, scn, lloon ltch Introduction s O process technology is scling, power supply voltge scles down s well, nd so do trnsistor threshold voltges to mintin high-speed opertion. lthough lowering the threshold voltge reduces circuit delys, it lso exponentilly increses the suthreshold lekge currents. These lekge currents led to power dissiption even when the circuit is not doing ny useful computtions which presents serious prolem for ttery operted devices. The complexity of modern designs hs reched point where sving power y implementing non-scnnle design is not vile. cnnle ltches re prt of the stndrd testing methodology, however trditionl methods for implementing scnnle designs hve power overhed tht is not negligile [11]. In this Permission to mke digitl or hrd copies of ll or prt of this work for personl or clssroom use is grnted without fee provided tht copies re not mde or distriuted for profit or commercil dvntge nd tht copies er this notice nd the full cittion on the first pge. To copy otherwise, to repulish, to post on servers or to redistriute to lists, requires prior specific permission nd/or fee. ILPE 02, ugust 12-14, 2002, onterey, liforni, U. opyright /02/ $5.00. pper we propose n integrted scn-retention mechnism tht hs much smller totl power overhed in the ctive mode thn the comintion of the prior rt scn nd retention mechnisms, implemented independently. We show how the proposed mechnism cn e pplied to vriety of ltch styles, including those recently reported. We prove the concept with developed lyout nd test chips mnufctured in stte of the rt 0:13µ technology, nd mesure the exct vlues for the power nd re overheds of the proposed mechnism. 1. PIO T LLOON LTH ETENTION EHNI stndrd method of reducing the lekge power during inctive intervls is to use the multi-threshold O (TO) technology, together with sleep or power down modes. ccording to this methodology, ll logic is uilt of low-threshold trnsistors, with high-threshold trnsistor serving s footer or heder to cut lekge during the quiescence intervls. uring the norml opertion mode, the TO circuits chieve high performnce, resulting from the use of low-threshold trnsistors. uring the sleep mode, high threshold footer or heder trnsistors re used to cut off lekge pths, reducing the lekge currents y orders of mgnitude. uring the power-down mode the stte of ll circuits, connected to the power supply (or ground) through the heder or footer is lost. In most cses the stte of the circuit needs to e restored on returning from the power-down mode, to resume the opertion. The stte of sequentil circuits is stored in ltches or flip-flops, consequently, to resume the opertion of the sequentil circuit fter returning from the stndy mode, the stte of ll ltches or flip-flops needs to e restored. prior rt technique for sving nd restoring the stte of ltches during the power-down mode in TO sequentil circuits is sed on duplicting every regulr ltch or flip-flop in the circuit with shdow or lloon ltch, nd providing pth to move dt from the regulr flip-flop to the shdow, nd ck [2, 7]. The lloon, or shdow ltch, shown in Fig. 1, is uilt of high-threshold devices, nd connected to rel power nd ground (ypssing the footer nd heder trnsistors). ince the lekge currents through the high threshold devices re orders of mgnitude smller thn those through the low-threshold trnsistors, the lekge currents through the lloon ltch during the power-down mode re smll, nd cn e neglected. Fig. 1 shows tht dding the lloon ltch dds ten extr trnsistors, to the flip-flop, incresing the trnsistor count from 16 to 26. Two inverters nd trnsmission gte T7, comprising the lloon ltch dd 6 trnsistors to the circuit. Trnsmission gtes T5 nd T6 dd 4 more trnsistors to the circuit, tht provide the pth for moving dt etween the min ltch nd the lloon ltch. Thus, the trnsistor count overhed of the lloon ltch is t estimted

2 LK IN inverter uilt of low-vt trnsistors inverter uilt of high-vt trnsistors trnsmission gte uilt of low-vt trnsistors trnsmission gte uilt of high-vt trnsistors LK_ LK T1 T2 lloon ltch LK_ 10 1 T3 2_ 11 2_ 1_ T6 T4 2 T5 T7 2 OUT LK LK_ Figure 1: Prior rt lloon ltch. 2 2_ to lloon ltch s 10=16 = 63% (the ctul re overhed my e smller though, ecuse of the smll size of trnsistors in the lloon ltch). dding the lloon ltch lso leds to n increse in dely through the ltch nd its ctive power, ecuse of the extr prsitic cpcitnce of the two trnsistors of trnsmission gte T6 tht gtes dt to nd from the lloon ltch, nd the two trnsistors in trnsmission gte T5 in the feedck pth of the slve ltch. For the minimum size trnsistors, the totl introduced cpcitnce tht is chrged/dischrged during the ctive mode of opertion is = 6 d +2 g + w,where d nd g re source nd drin cpcitnces of minimum size trnsistors, nd w is the wiring cpcitnce overhed. This introduced cpcitnce switches every time new dt is ltched. For ltch working with non-overlpping phses of the clock, it is not ffected y glitches t the ltch input. Thus, the power overhed of the dt retention feture in the ctive mode cn e estimted s P r = 1 2 α f 2,where f is the clocking rte nd α is the ctivity fctor. imultions show tht for 0:13µ ulk technology with V dd = 1V, f = 250Hz nd α = 0:3 the power overhed of the lloon ltch in design tht hs 4000 ltches is pproximtely P r = 0:5mW, which is not negligile in stte of the rt low power designs. If the feedck pth in the slve ltch is uilt s shown in Fig. 1, however, the trnistors in the trnsmission gte T5 do not introduce ny cpcitnce tht switches during the norml opertion mode, which reduced the introduced cpcitnce to = 2 d + w If there is the scn requirement in ddition to the dt retention, nd the scn mechnism is implemented independently of the retention mechnism, then the comined overhed of the scn-retention mechnism gets more significnt. Even for the stte of the rt lowpower scn mechnism in [13] the power overhed of the scn feture, for the sme ssumptions is P s = 0:3mW, nd the totl power overhed of the retention nd scn mechnisms, implemented independently is P s+r = P s + P r = 0:8mW, which my exceed 5% of the ctive power of stte of the rt low power low-power product of this size. In this pper we propose n integrted scn-retention mechnism tht hs much smller totl power overhed in the ctive mode thn the comintion of the prior rt scn nd retention mechnisms, implemented independently. We show how the proposed mechnism cn e pplied to vriety of ltch styles, including those in the recently reported works. We prove the concept with developed lyout nd test chips mnufctured in stte of the rt 0:13µ technology, nd mesure the exct vlues for the power nd re overheds of the proposed mechnism. 1 1_ T6 OUT 2. NEW INTEGTE N-ETENTION EHNI The proposed integrted scn-retention mechnism is sed on prior rt low-power overhed level-sensitive scn mechnism [13], shown in Fig. 2. The mster ltch in Fig. 2 cn e ny type of single phse ltch, or two-phse ltch, for exmple, edge-triggered ltch, pulsed ltch [8, 10], or dul edge triggered flip-flop [5, 3]. The scn ltch is low-re slow level-sensitive ltch, controlled y clock. The output of the scn ltch is the scn output of the entire flip-flop. It is connected to the scn input of nother ltch in the scn chin. uring norml opertion mode, clock nd clock re kept t the low level, nd the flip-flop works s conventionl ltch, wheres scn ltch is in the non-trnsprent stte, so tht the scn output does not toggle, nd the internl cpcitnces inside the scn ltch do not toggle either. This reduces the power dissiption in the norml opertion mode. uring the scn mode, clock is kept t the low level, nd the flip-flop works s mster-slve ltch, controlled y non-overlpping clocks nd, providing roust, level-sensitive scn opertion. clock clock clock TE LTH T_IN clock N_IN clock run scn dt in run scn dt out clock N LTH T_OUT N_OUT Figure 2: Prior rt low power scn mechnism. Fig. 3 nd 6 show implementtion exmples of the ove scn mechnism, pplied to some of the recently pulished ltches [8, 10, 5, 3]. For utted ltches in custom dtpths scn outputs nd of ltch re connected to scn inputs nd of n djcent ltch. For distnt scn connections single-ril connection is used, nd input is loclly inverted. uch connection scheme reduces the trnsistor re overhed of the scn mechnism without incurring significnt routing overhed. The power overhed of this scn mechnism is reduced to the gte nd drin cpcitnce of two minimum-sized trnsistors, connected to the output nodes plus some wiring overhed. This extr cpcitnce is chrged or dischrged t most once per clock cycle, nd is not ffected y spurious trnsitions t the dt input. Fig. 4 shows the proposed extension to the ove scn mechnism to provide the low-overhed dt retention cpility. The new flip-flop with retention uses the scn ltch s low-lekge storge for retining dt during the power-down mode, nd provides n extr pth for restoring the dt from the retention ltch to the min flip-flop. The retention ltch is uilt of low-lekge devices, such s high threshold trnsistors, or regulr trnsistors with the ck is cpility. If gte lekge is n issue, trnsistors in the retention ltch cn e implemented s thick gte oxide devices. el ground nd re used s power terminls in the retention ltch. The rest of the flip flop is uilt of fst low threshold, thin gte oxide trnsistors, nd it my use either virtul with heder, or virtul ground with footer, to cut the lekge pth during the power-down mode. uring the norml opertion mode clocks nd re kept t the low level, nd the ltch opertes s the conventionl ltch. uring

3 ETOE LEEP T_IN clock LEEP_ TE LTH N_IN clock gnd N / ETENTION LTH clock gnd T_OUT N_OUT LEEP clock clock T_IN _sve_in undefined _sve_in _OUT _sve_out undefined _sve_out Figure 4: cnnle ltch with dt retention. c d Figure 3: cnnle ltches: - ep-ff; - PL; c - ep- FF; d - PFF. T_ N8 N4 T Figure 5: cnnle HLFF ltch with dt retention. the scn mode the ETOE signl is kept t the low level, nd the ltch work s mster-slve ltch, controlled y clocks nd, s descried erlier. When entering the sleep mode, high level t clock sves dt in the retention ltch, Fig. 4. On returning from the sleep mode, high level is pplied to the ETOE signl, nd high level t clock restores dt from the retention ltch to the min flip-flop. Fig. 5 nd 6d show exmples of implementing the proposed dt retention mechnism in the scnnle HLFF nd sense mplifier ltches. The pth for restoring dt from the retention ltch to the min ltch is implemented s stck of NFETs or nd N4. The proposed scn-retention mechnism cn e pplied to vriety of ltches [1, 4, 8, 9], including those in Fig. 3. The dditionl power nd dely overhed of the retention mechnism over the scn mechnism is reduced to minor increse in cpcitnces of internl wires, due to some increse in the re of the flip flop. No extr cpcitnce of trnsistor gtes, sources or drins is dded to ny nodes tht re switching during the norml opertion mode. This feture mkes the proposed retention mechnism prticulrly ttrctive for low-power pplictions, where minimizing oth ctive nd stndy power is importnt 3. NLY OF THE OVEHE OF T ETENTION To determine the re, dely nd power overheds of the proposed dt retention mechnism we developed the lyout in 0.13um technology for the four versions of the sense mplifier ltch [6, 13]: non-scnnle ltch without dt retention, Fig. 6, scnnle ltch without dt retention, Fig. 6, non-scnnle ltch with dt retention, Fig. 6c, nd scnnle ltch with dt retention, Fig. 6d. The lyout for the non-scnnle ltch without retention fits into 9 trcks, Fig. 7, while the lyouts for the scnnle ltch, nd ltch with dt retention were designed to fit into 12 trcks, Fig. 8 nd 9. For the design in Fig. 9, the retention ltch is uilt out of regulr trnsistors, plced in seprte wells for the ck ising cpility. This design choice leds to somewht higher re overhed ecuse of the miniml spcing requirement etween wells ised to different potentils. lso, there is n dditionl re overhed due to well contcts in the retention ltch, which cn e shred y djcent ltches if they re flipped ppropritely. The re overhed for the retention ltch tht uses high threshold devices is smller y t lest one trck in width, ut the mnufcturing cost is higher. Tle 1 gives res for the four ltches in Fig. 6. lthough the scnnle ltch with dt retention hs four trnsistors more thn the nonscnnle ltch with dt retention, they hve the sme re, ecuse the height is determined y the height of the retention ltch, nd the width cnnot e reduced ecuse of the miniml well seprtion ground rule. The scnnle ltch without dt retention hs 2 trcks smller width thn the one with dt retention ecuse wells of the trnsistors in the mster nd scn/retention ltches do not need to e seprted. To determine the exct mount of the power nd performnce overhed of the scn nd dt retention mechnisms we developed the lyout for multi-it dtpth registers with scn chin nd lo-

4 V I I V V V V Figure 8: cnnle ltch without dt retention. Fig. 6. I I T_ N8 V N4 T V V c Figure 6: ense mplifier ltch: - non-scnnle ltch; - scnnle ltch; c - non-scnnle ltch with dt retention; d - scnnle ltch with dt retention. d Figure 9: cnnle ltch ltch with dt retention. Fig. 6d. cl clock distriution network, Fig. 10, nd rn simultions on the extrcted netlists, ccording to the methodology descried in [13]. Tle 1 summrizes results of the simultions. For mesuring delys ll ltches were loded with three minimumsize inverters nd wiring cpcitnce. The dditionl overhed of the dt retention feture over the scn mechnism is very smll (no more thn 1%), nd so is the dditionl overhed of the scn feture over the dt retention mechnism. For the implemented designs the increse in dely compred to the non-scnnle ltch is 15% ecuse very smll lod cpcitnces were used in simultions, typicl of ultr low power designs, nd ltch trnsistors were tuned ccordingly. The dely overhed is much smller in highperformnce designs, where trnsistor sizes re tuned for smller delys. The power of the developed ltches ws mesured using the methodology in [12, 13, 9]. The dt in Tle 1 correspond to the switching fctor α = 0:3 nd the glitching fctor β = 0:16. The power of the locl clock distriution ws included into the ltch power mesurements, nd so ws the cpcitnces of metl wires to get from the ltch oundry to the dt input pin nd from the dt output pin to the other oundry. 9-trck cell height design ws ssumed for the non-scnnle ltch without retention, wheres 12-trck cell height design ws used for mesuring the power of the other three ltches, which resulted in somewht lower power numers for the non-scnnle ltch without retention. If the sme itstep is used for ll ltches, the power overhed of the scn/retention mechnism is only 3%. The power overhed of the scn/retention mechnism is 3 times smller thn the dely overhed, ecuse the introduced cpcitnce switches only when new dt is ltched, which ws ssumed to hppen on the verge once every 3.33 cycles (α = 0:3). s discussed erlier, the power overhed is even smller in designs tuned for higher performnce. Figure 7: Fig. 6. Non-scnnle ltch without dt retention, Figure 10: 16-it dt register (not ll lyers re shown).

5 Tle 1: re, dely nd verge energy per cycle of ltches with nd without scn nd dt retention mechnisms ( = 0.9V). ltch re dely energy design µ 2 % ps % fj %, scn, retention scn, retention , scn + retention scn + retention ONLUON methodology for unifying the scn nd dt retention mechnismsin ltches ws presented which leds to scnnle ltches with the dt retention cpility chieved t very low power overhed during the ctive mode. The exct mount of the power nd performnce nd re overhed ws mesured using netlists extrcted from the lyouts uilt in stte of the rt 0.13um technology. The dditionl overhed of the dt retention feture over the scn mechnism is very smll, nd so is the dditionl overhed of the scn feture over the dt retention mechnism. The proposed integrted scn-retention mechnism chieves oth fetures t the cost of one. ymposium on Low Power Electronics nd esign, pges , ugust [10] J. Tschnz et l. omprtive dely nd energy of single edge-triggered nd dul edge-triggered pulsed flip-flops for high-performnce microprocessors. In IEEE ymposium on Low Power Electronics nd esign, pges , ugust [11]. We et l. 400-Hz /390 microprocessor. IEEE Journl of olid-tte ircuits, 32(11): , Novemer [12] V. Zyun nd P. Kogge. ppliction of T to ltch-power estimtion. IEEE Trnsctions on VL ystems, 7(1), rch [13] V. Zyun nd. eltzer. locking strtegies nd scnnle ltches for low power pplictions. In IEEE ymposium on Low Power Electronics nd esign, pges , ugust cknowledgment The uthors would like to thnk their collegues. Kneel, G. Gristede nd. Hen for the design flow support; K. Wrren nd J. oreno for the mngement support. 5. EFEENE [1] F. Klss et l. new fmily of semidynmic nd dynmic flop-flops with emedded logic for high-performnce processors. IEEE Journl of olid-tte ircuits, 34(5): , y [2]. utoh et l. 1v multi-threshold voltge O P with n efficient power mngement technique for moile phone pplictions. In I, pges , [3] N. Nedovic,. leksic, nd V. Oklodzij. Timing chrcteriztion of dul-edge triggered flip-flops. In I, ugust [4] N. Nedovic nd V. Oklodzij. ynmic flip-flop with improved power. In Proceedings of the Interntionl onference on omputer esign, eptemer [5] N. Nedovic nd V. Oklodzij. Hyrid ltch flip-flop with improved power efficiency. In Proceedings of the ymposium on Integrted ircuits nd ystems esign, [6]. Nikolic et l. Improved sense-mplifier-sed flip-flop: esign nd mesurements. IEEE Journl of olid-tte ircuits, 35(6): , June [7]. higemtsu,. utoh, Y. tsuy, Y. Tne, nd J. Ymd. 1-v high-speed TO circuit scheme for power-down ppliction circuits. IEEE Journl of olid-tte ircuits, 32(6): , June [8] V. tojnovic nd V. Oklodzij. omprtive nlysis of mster-slve ltches nd flip-flops for high-performnce nd low-power systems. IEEE Journl of olid-tte ircuits, 34(4): , pril [9] V. tojnovic, V. Oklodzij, nd. jw. unified pproch in the nlysis of ltches nd flip-flops for low-power systems. In Proceedings of the Interntionl