Technical Report GIT-CC Some Layouts Using the Sleepy Stack Approach

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1 Technicl Report GIT-CC Some Lyouts Using the Sleepy Stck Approch Philipp Pfeiffenerger, Jun Cheol Prk nd Vincent J. Mooney III Center for Reserch on Emedded Systems nd Technology Georgi Institute of Technology, Atlnt, Georgi, U.S.A. June 2004

2 1. Introduction This technicl report elortes on the methodology nd findings presented in Sleepy Stck Reduction of Lekge Power y J.C. Prk, V. J. Mooney III nd P. Pfeiffenerger [1]. The scope of this report includes test procedures nd dt on dely, dynmic nd sttic power for ll considered pproches nd implementtions s well s schemtics nd lyouts for ll considered pproches nd implementtions. 2. Bse cse We chose to evlute the sleepy stck pproch on three flvors of gtes: n inverter, full dder nd 4-input multiplexer [1]. These gtes were chosen to exemplify strightforwrd "memory-like" cse (the inverter, which is the sis of SRAM), ddition, nd complex gte using NAND, NOR nd INV gtes (the multiplexer). The four lekge current reduction pproches considered in this report re compred to sic CMOS implementtion. In ll pproches, trnsistors re plced in two rows, ech prllel to continuous Vdd nd Gnd contcts. When possile, corresponding Euler pths re chosen from the pull up nd pull down networks in the schemtic. Using these pths, trnsistors re plced so tht NMOS nd PMOS trnsistors driven y the sme input cn e connected with verticl strip of poly nd single contct. Trnsistor sizes re specified s rtio of Width / Length (W/L). In the cse of the North Crolin Stte University (NCSU) [8] design kit trgeting the Tiwn Semiconductor Mnufcturing Compny (TSMC) 0.18 µm process, the smllest possile trnsistor hs width of 270nm nd length of 180nm, resulting in rtio of W/L = 270nm / 180nm = 1.5. This rtio of signifies the smllest fesile trnsistor size throughout this report. Trnsistors re initilly sized so tht ll circuits hve rise nd fll times equl to those of n inverter with NMOS W/L = 1.5 nd PMOS W/L = 3. Two of the considered sttic current reduction pproches explined in Section 3 i.e., the stck [2][3] nd sleepy 2

3 stck [1] pproches, typiclly use two trnsistors ech hlf the width of prticulr single trnsistor in the seline pproch. Since oth NOR nd INV gtes contin trnsistors with W/L = 1.5, the widths of ll trnsistors composing NOR (Appendix D) nd INV (Appendix A), s well s NAND (Appendix C) (for uniformity in the multiplexer) re douled. This douling is not pplied to the Cout nd Sum circuits of the full dder (Appendix B). The Cout nd Sum circuits do not contin ny miniml width gtes when sized to hve rise nd fll times equl to one inverter nd would yield unresonly lrge gte sizes if douled. Schemtics for the networks nd pproches mentioned in this section cn e found in the respective Appendices. 3. Sttic current reduction pproches The sleepy stck [1] pproch is compred to the se cse s well s three estlished sttic power reduction techniques: trnsistor stcking [2][3], Vdd gting vi sleep trnsistors [4] nd selective Vdd gting vi lternting sleep trnsistors (the so-clled zigzg pproch) [5]. In order to firly ssess the re needed to implement ech pproch we chose to lwys plce ll trnsistors in single line long Vdd nd Gnd. 3.1 Stck The stck pproch is implemented y duplicting every trnsistor in the se cse network, with oth the originl nd duplicte ering hlf the originl trnsistor width. We chose to lwys plce ll trnsistors in single row long Vdd nd Gnd. Therefore, n increse of the numer of trnsistors nd slight decrese in trnsistor width forces n increse in row length nd decrese in row height. E.g., n inverter in the se cse (Appendix A.1.) hs height of 4.7 µm nd width of 5.0 µm while n inverter implemented using the stck pproch (Appendix A.2.) hs height of 4.0 µm nd width of 6.7 µm Creting duplicte trnsistors in series with the originl presents the dvntge of mintining the sme lyout structure s the se cse, with oth the originl nd newly formed trnsistor gtes ccessile vi the sme strip of poly. Appendices A.2., B.2., 3

4 C.2. nd D.2. illustrte how the se cse lyout in Appendices A.1., B.1., C.1. nd D.1. is lrgely mintined fter pplying the stck pproch. 3.2 Sleep For the sleep pproch, the trnsistor sizes of the se cse re mintined with dded trnsistors gting the Vdd nd Gnd of the circuit. The PMOS sleep trnsistor etween Vdd nd the rest of the pull-up network is driven y the Sleep (S) signl, forming pth to Vdd when S is low. The NMOS sleep trnsistor etween Gnd nd the rest of the pulldown network is driven y the Sleep (S ) signl, direct inverse of S. Both of these gting trnsistors will from hereon out e collectively referred to s sleep trnsistors nd will tke the width of the lrgest trnsistor in their respective se cse network. Vdd nd Gnd re disconnected from the circuit when S is high (the circuit is idle), reducing suthreshold lekge ut lso losing stte. Suthreshold lekge cn further e reduced y rising the threshold voltge of sleep trnsistors. The re penlty incurred with the sleep pproch is greter thn tht of the se cse, stck or zigzg pproch. In trnsistor level lyout, dditionl spce is required for sleep trnsistors s well s S nd S signl lines. Additionlly, the gted Vdd/Gnd signl my run etween Vdd/Gnd contcts nd trnsistors, further incresing cell height. Lyout structure is lrgely mintined (Appendix B.1. vs. B.3.) lthough the horizontl S nd S lines force use of t lest second metl lyer even in simple designs, such s the inverter in Appendix A Zigzg The zigzg pproch relies on plcement of lternting Vdd/Gnd gting trnsistors in wy tht minimizes lekge for set of most prole input vectors. In order to firly ssess the effectiveness of this pproch, the miniml sttic power dissipted (nd ssocited input vector) is chosen for comprison. In lyout, the lternting pull-up / pull-down Vdd/Gnd gting trnsistors should plced on utting ends of djcent circuits (Appendix A.4..). The gting trnsistors of these utting circuits llow for routing scheme similr to tht of the sleep pproch in Section 3.4. This rings smll ut noticele svings in re over sleep pproch. 4

5 3.4 Sleepy stck: The sleepy stck pproch comines the stck nd sleep pproches y dividing every trnsistor in the network nd plcing sleep trnsistors in prllel with one of the divided trnsistors [1]. Following the methodology of the sleep pproch, sleep trnsistors re plced on the split trnsistor closest to the Vdd in the pull up, while the pull down network hs sleep trnsistors plced in prllel with the trnsistor closest to Gnd. A pth from either Gnd or Vdd to output exists in sleep mode, formed y the trnsistors prllel to the sleep trnsistors. The sleep trnsistors reduce resistnce when the circuit is switching. As seen with even simple exmples (NAND, Appendix C.1 vs. C.5) the network of the Sleepy stck pproch ers little resemlnce to tht of the se cse. In lyout, re is incresed considerly y the tripling of ll trnsistors. The ddition of nodes with n odd numer of vertices (y prllel plcement of sleep trnsistors) cn led to elimintion of Euler pths nd reks in n nd p type regions. As in the stck pproch, stcked trnsistors re ccessile y single contct to ridging strip of poly (Appendix C.1..) Due to plcement of the sleep trnsistor, the stcked trnsistors cn no longer e implemented s one ctive region with two fingers. As in the sleep pproch, sleep signls should e routed horizontlly cross source/gnd contcts to conserve spce. (Appendix B.5..i) 4. Experimentl Methodology Schemtics for ll models nd pproches re creted in Cdence Virtuoso Schemtic Editor [7] nd sized in ccordnce with the pproches outlined in Section 2. Netlists re extrcted from the schemtic using Cdence Virtuoso Anlog Environment. These netlists re ugmented with prmeters extrcted from the Tiwn Semiconductor Mnufcturing Compny (TSMC) 0.18 µm process, s well s those of the Berkeley Predictive Technology Model (BPTM) [9] 0.18, 0.13, 0.10 nd 0.07 µm processes. The mesurements outlined in Sections 4.1, 4.2 nd 4.3 were performed using Avnt! HSPICE [6]. Unless otherwise specified, input wveforms hve 4 ns period nd rise/fll times of 100 ps. 5

6 4.1 Dely Input vectors nd input nd output triggers re chosen to mesure dely cross given circuit s criticl pth. Fll time is mesured s the time etween the trigger input edge reching 50% supply voltge nd circuit output edge flling to 50% supply voltge. Likewise, the time etween the input edge reching 50% nd circuit output edge rising to 50% supply voltge is recorded s the rise time. This method of mesuring dely is crried on throughout ll experiments, with only the high/low ptterns of the input vectors vrying nd triggers vrying. 4.2 Dynmic power Dynmic power is mesured y sserting clocked semi-rndom input vectors for period of 20ns nd clculting the verge power dissipted during this period. 4.3 Sttic power Sttic power is mesured y sserting set of input vectors s DC sources in HSPICE nd mesuring the verge power dissipted y the circuit during period of 20 ns. 4.4 Are Are is mesured from full trnsistor level lyouts for the se cse s well s stck, sleep, zigzg nd sleepy stck pproches. The lyouts re creted using Cdence Virtuoso lyout tool nd North Crolin Stte University s (NCSU s) Cdence design toolkit for 0.18µm [8]. Lyouts re verified with Virtuoso s Digitl Rule Checking (DRC) nd Lyout Versus Schemtic (LVS). Becuse design kit for su 0.18µm sizes is unville t time of puliction, lyout sizes re scled y rtio of squres with 10% penlty pplied for nonliner technology components. 5. Test Circuits Three test circuits of vrying complexity re implemented s descried in Sections 2 nd 3. A chin of three inverters is chosen s the most sic of logic gtes nd is indictive of single trnsistor level ehvior nd effectiveness. To ssess effectiveness using 6

7 complex rrngement of simple logic locks, 4-1 MUX is ssemled from NAND, NOR nd INV gtes. Finlly, full dder is chosen s representtion of complex logic, composed of two complex logic gtes nd two inverters. The effectiveness of the five sttic power reduction pproches considered in this pper were ssessed y pplying the experimentl methodology of Section 4 to test circuits in Sections 5.1, 5.2 nd Three Inverter chin Three inverters, eqully sized (NMOS W/L = 3, PMOS W/L = 6 for the se cse) re connected in series s shown in Figure 1. Mesurements re mde cross the inverter chin, from the first inverter s input to the lst inverter s output. Figure 1. Three inverter chin. Dely A squre wve is set s input signl for the 3-inverter chin. After four periods, the dely etween the input nd inverted output is mesured.. Sttic power Sttic power for the inverter is mesured y sserting high nd low DC signls nd verging the power dissipted y ech input fter period of 20 ns. c. Dynmic power Dynmic power for the inverter is mesured y sserting the sme squre wve used in dely ssessment (Section 5.1..) to the inverter chin input. Agin, the verge power dissipted over period of 20ns is recorded s the Dynmic power of the 3 inverter chin. d. Are A full lyout for three inverter chin cn e seen in Appendix A. 7

8 Mux The 4-1 Mux in Figure 2 is implemented using nine 2-input NAND gtes, six 2-input NOR gtes nd two inverters s shown in Figure 2. In the se cse, ll gtes re sized to hve rise nd fll times equl to n inverter with NMOS W/L = 3 nd PMOS W/L = 6. X0 X1 X2 X3 S1 S0 E Figure 2. Logic gte network nd criticl pth for 4-1 MUX. Dely The 4-1 Mux dely is mesured cross the criticl pth shown in Figure 2, from S 1 (symmetric to S 0 ) to the output. Before dely is mesured cross the criticl pth, the input X 0 is set high nd input X 2 is set low. Dely cross the criticl pth is mesured y sserting low to S 1. The output signl is driven high cross the pth in Figure 2 nd the dely is mesured s in Figure. 3. X 0 X 2 S 1 S 0 Out Figure 3. Input/Output wveform used to mesure the criticl pth dely. 8

9 . Dynmic power Dynmic power is mesured y sserting rndom vlues on ll inputs for period of 20ns. The verge power during this period is recorded s dynmic power. c. Sttic power From the set of 128 possile inputs, smple of 8 is chosen nd the sttic power dissipted y the DC signls over period of 20ns mesured. These smple inputs re listed in Tle 1. Tle 1. Sttic power ssessment inputs used for 4-1 MUX. X 0 X 1 X 2 X 3 S 0 S 1 E d. Are The re for MUX lyout is estimted y creting full lyouts of components used, i.e. NAND, NOR nd INV, nd dding the res of needed components. This sum-of-prts estimtion does not tke into ccount extr re needed to wire ll components, ut the sence of wiring penlty eqully ffects ll considered pproches. To estimte the re, ech component width is multiplied with the height of the tllest component for ech pproch. For exmple, if for the stck pproch the NOR gte hs the lrgest height, n djcent inverter would hve to use the sme source nd drin nd therefore hve n re equl to its se multiplied y the height of the NOR gte. 9

10 5.3 4-it Adder A series of full dders (Figure 4) is creted from four logic locks, one complex logic lock tht genertes inverted Crry out (Cout ), one complex logic lock tht genertes n inverted Sum (Sum ) nd two inverters to crete non-inverted signls from the outputs of the two complex locks. While the inverters re sized to twice the originl size (similr to the inverters in Section 5.1), the complex logic locks re sized to hve rise nd fll time equl to n inverter with NMOS W/L = 1.5, PMOS W/L = 3. A B Cin A B A Cin Cout Cout B Cout Cin Sum Sum Figure 4. Network of complex gtes nd inverters composing 1-it full dder. Dely The criticl pth of the 4-it dder is formed y the propgtion of crry signls. To mesure dely, crry propgtion is forced cross the chin s shown in Figure 5. The dely etween dder input signls nd the formtion of the lst Cout is tken s the worst cse dely A B C in C out A B A B A B C in C out C in C out C in Sum Sum Sum Sum C out Figure 5. Inputs of 4-it dder for criticl pth dely mesurement 10

11 . Dynmic power To ssess the dynmic power dissipted y the circuit, test vector covering every possile input is formed nd sserted. A low signl is sserted on ll inputs efore ny high signls to minimize sttes in which sttic power is dominnt. The resulting wveform (Figure 6) is sserted cycliclly for 20ns nd the verge power dissipted during this period recorded s dynmic power. A B C Sum Cout Figure 6. Dynmic power ssessment wveform for full dder c. Sttic power All eight possile inputs re in turn imposed s DC source. The verge of the power dissipted for ech input fter 20ns is recorded s the sttic power dissiption of the circuit. d. Are A full trnsistor-level lyout is creted for 1-it dder. The re for four-it dder is tken s the sum of res for four 1-it dders. 5. Conclusions In terms of re, the sleepy stck pproch is etter suited for simple logic gtes thn complex logic gtes, s shown in Figure 7. The reson tht simple networks re fvored y the pproch rises out of the sleepy stck structure. The structure of sleepy stck trnsistor group consists of the originl trnsistor, stcked duplicte nd sleep trnsistor 11

12 connected etween the originl trnsistor nd stcked duplicte. The center node connecting ll three trnsistors hs n odd numer of vertices. Nodes with n odd numer of vertices cn e included in Euler pth, ut only s strting or ending points of the pth. Therefore, Euler pth cn include t most two sleepy stck trnsistor groups, forcing seprte pths for ll other pirs of sleepy stcks. Since continuous ctive regions depend on Euler pths in the pull-up/pull-down network, the numer of seprte ctive regions will e proportionl to hlf the numer of sleepy stcked trnsistors. The sleepy stck pproch could fesily e implemented in stndrd cell lirry of simple logic locks. Due to the re penlty, the sleepy stck pproch cn e etter used for pplictions where sttic power consumption is criticl nd cost cn e pid in re nd dely. Are for Sttic Power Reduction Implementtions 1000 Are (µm^2) Bse cse Stck Sleep Zigzg Sleepy stck 3 Inverter Chin MUX Full Adder Figure 7. Ares for considered sttic power reduction implementtions nd respective test circuits. 12

13 6. References [1] J.C. Prk, V. J. Mooney III nd P. Pfeiffenerger, Sleepy Stck Reduction of Lekge Power, To e pulished in PATMOS 2004 [2] Z. Chen, M. Johnson, L. Wei nd K. Roy, Estimtion of Stndy Lekge Power in CMOS Circuits Considering Accurte Modeling of Trnsistor Stcks, Interntionl Symposium on Low Power Electronics nd Design, pp , [3] S. Ndr, S. Borkr, V. De, D. Antonidis nd A. Chndrksn, Scling of Stck Effect nd its Appliction for Lekge Reduction, Interntionl Symposium on Low Power Electronics nd Design, pp , August [4] M. Powell, S.-H. Yng, B. Flsfi, K. Roy nd T. N. Vijykumr, Gted-Vdd: A Circuit Technique to Reduce Lekge in Deep-sumicron Cche Memories, Interntionl Symposium on Low Power Electronics nd Design, pp , July [5] K.-S. Min, H. Kwguchi nd T. Skuri, Zigzg Super Cut-off CMOS (ZSCCMOS) Block Activtion with Self-Adptive Voltge Level Controller: An Alterntive to Clock-gting Scheme in Lekge Dominnt Er, IEEE Interntionl Solid-Stte Circuits Conference, Vol. 1, pp , Ferury [6] Avnt! Corportion, [7] Cdence Design Systems, [8] NC Stte University Cdence Tool Informtion, [9] Berkeley Predictive Technology Model (BPTM), 13

14 Appendices A) 3 Inverter Chin 1) Bse pproch ) Schemtic ) Lyout 2) Stck pproch ) Schemtic ) Lyout 3) Sleep pproch ) Schemtic ) Lyout 4) Zigzg pproch ) Schemtic ) Lyout 5) Sleepy stck pproch ) Schemtic ) Lyout 6) 3 inverter chin Dt B) Full Adder 1) Bse pproch ) Schemtic ) Lyout 2) Stck pproch ) Schemtic (i) Cout (ii) Sum ) Lyout 3) Sleep pproch ) Schemtic (i) Cout (ii) Sum ) Lyout 4) Zigzg pproch ) Schemtic (i) Cout (ii) Sum ) Lyout (i) Cout (ii) Sum (iii) Full Adder 5) Sleepy stck pproch ) Schemtic (i) Cout (ii) Sum ) Lyout 14

15 (i) Cout (ii) Sum (iii) Full Adder 6) Adder Dt C) NAND 1) Bse cse ) Schemtic ) Lyout 2) Stck pproch ) Schemtic ) Lyout 3) Sleep pproch ) Schemtic ) Lyout 4) Zigzg pproch ) Schemtic (i) PMOS Sleep (ii) NMOS Sleep ) Lyout (i) PMOS Sleep (ii) NMOS Sleep 5) Sleepy stck pproch ) Schemtic ) Lyout D) NOR 1) Bse cse ) Schemtic ) Lyout 2) Stck pproch ) Schemtic ) Lyout 3) Sleep pproch ) Schemtic ) Lyout 4) Zigzg pproch ) Schemtic (i) PMOS Sleep (ii) NMOS Sleep ) Lyout (i) PMOS Sleep (ii) NMOS Sleep 5) Sleepy stck pproch ) Schemtic ) Lyout E) MUX Dt 15

16 A.1.. Bse pproch 3 inverter chin schemtic 16

17 A.1.. Bse pproch 3 inverter chin lyout 17

18 A.2.. Stck pproch 3 inverter chin schemtic 18

19 A.2.. Stck pproch 3 inverter chin lyout 19

20 S S S S S S A.3.. Sleep pproch 3 inverter chin schemtic 20

21 A.3.. Sleep pproch 3 inverter chin lyout 21

22 S S S A.4.. Zigzg pproch 3 inverter chin schemtic 22

23 A.4.. Zigzg pproch 3 inverter chin lyout 23

24 S S S S S S A.5.. Sleepy stck pproch 3 inverter chin schemtic 24

25 A.5.. Sleepy stck pproch 3 inverter chin lyout 25

26 TSMC 0.18µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 9.56E E E Stck 2.46E E E Sleep 1.56E E E ZigZg 1.34E E E Sleepy Stck 1.78E E E Sleep (dul Vth) 2.22E E E ZigZg (dul Vth) 1.76E E E Sleepy Stck (dul Vth) 2.19E E E Berkeley 0.18µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 7.73E E E Stck 1.95E E E Sleep 1.06E E E ZigZg 1.01E E E Sleepy Stck 1.38E E E Sleep (dul Vth) 1.55E E E ZigZg (dul Vth) 1.47E E E Sleepy Stck (dul Vth) 1.87E E E Berkeley 0.13µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 7.00E E E Stck 1.70E E E Sleep 9.34E E E ZigZg 8.14E E E Sleepy Stck 1.20E E E Sleep (dul Vth) 1.41E E E ZigZg (dul Vth) 1.07E E E Sleepy Stck (dul Vth) 1.64E E E Berkeley 0.10µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 5.36E E E Stck 1.30E E E Sleep 7.05E E E ZigZg 6.21E E E Sleepy Stck 9.28E E E Sleep (dul Vth) 1.02E E E ZigZg (dul Vth) 8.28E E E Sleepy Stck (dul Vth) 1.22E E E Berkeley 0.07µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 4.61E E E Stck 1.28E E E Sleep 6.98E E E ZigZg 5.99E E E Sleepy Stck 8.75E E E Sleep (dul Vth) 1.14E E E ZigZg (dul Vth) 9.03E E E Sleepy Stck (dul Vth) 1.38E E E A.6. 3 inverter chin dt 26

27 W/L=12 W/L=12c W/L=12 W/L=9 W/L=9 W/L=12 c W/L=9 W/L=9 Crry W/L=4 W/L=12 W/L=12 c Sum c c B.1.. Bse cse full dder schemtic 27

28 B.1.. Bse cse full dder lyout 28

29 c W/L=2.25 c W/L=2.25 Crry c c B.2..i. Stck pproch Full Adder Cout schemtic 29

30 c W/L=8 c Crry W/L=2 c W/L=2 c Sum W/L=2.25 W/L=2.25 c c W/L=2.25 W/L=2.25 W/L=2.25 W/L=2.25 B.2..ii. Stck pproch Full Adder Sum schemtic 30

31 B.2.. Stck pproch Full Adder lyout 31

32 W/L=9 S W/L=9 W/L=9 c W/L=9 W/L=9 Crry c S B.3..i. Sleep pproch Full Adder Cout schemtic 32

33 S W/L=12 c W/L=12 W/L=12 W/L=12 W/ L=12 Crry W/L=4 W/ L=12 W/ L=12 c Sum c S B.3..ii. Sleep pproch Full Adder Sum schemtic 33

34 B.3.. Sleep pproch Full Adder lyout 34

35 W/L=9 W/L=9 c W/L=9 W/L=9 Crry c S B.4..i. Zigzg pproch Full Adder Cout schemtic. 35

36 c W/L=12 W/L=12 W/L=12 W/L=12 Crry W/L=4 W/L=12 W/L=12 c Sum c S B.4..ii. Zigzg pproch Full Adder Sum schemtic 36

37 B.4..i. Zigzg pproch Full Adder Cout lyout 37

38 B.4..ii. Zigzg pproch Full Adder Cout lyout 38

39 B.4..iii. Zigzg pproch Full Adder lyout 39

40 S S S S W/L=2.25 c W/L=2.25 c W/L=2.25 S Crry c S c S S S S B.5..i. Sleepy stck pproch Full Adder Cout Schemtic 40

41 S S c S c S S S W/L=2 Crry W/ L=2 c W/ L=2 c Crry Sum W/L=2.25 Crry W/L=2.25 W/L=2.25 c c W/L=2.25 W/L=2.25 W/L=2.25 W/L=2.25 W/L=2.25 W/L=2.25 B.5..ii. Sleepy stck pproch Full Adder Sum Schemtic 41

42 B.5..i. Sleepy stck pproch Full Adder Cout Lyout 42

43 B.5..ii. Sleepy stck pproch Full Adder Sum Lyout 43

44 B.5..iii. Sleepy stck pproch Full Adder Lyout 44

45 TSMC 0.18µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 6.97E E E Stck 1.70E E E Sleep 9.43E E E ZigZg 9.45E E E Sleepy Stck 1.36E E E Sleep (dul Vth) 1.26E E E ZigZg (dul Vth) 1.26E E E Sleepy Stck (dul Vth) 1.73E E E Berkeley 0.18µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 5.07E E E Stck 1.50E E E Sleep 6.79E E E ZigZg 6.83E E E Sleepy Stck 1.18E E E Sleep (dul Vth) 9.38E E E ZigZg (dul Vth) 9.53E E E Sleepy Stck (dul Vth) 1.63E E E Berkeley 0.13µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 4.15E E E Stck 1.21E E E Sleep 5.46E E E ZigZg 5.43E E E Sleepy Stck 9.35E E E Sleep (dul Vth) 7.53E E E ZigZg (dul Vth) 7.56E E E Sleepy Stck (dul Vth) 1.21E E E Berkeley 0.10µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 3.08E E E Stck 8.95E E E Sleep 4.13E E E ZigZg 4.17E E E Sleepy Stck 7.01E E E Sleep (dul Vth) 5.55E E E ZigZg (dul Vth) 5.62E E E Sleepy Stck (dul Vth) 9.14E E E Berkeley 0.07µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 2.91E E E Stck 8.89E E E Sleep 4.11E E E ZigZg 4.06E E E Sleepy Stck 6.79E E E Sleep (dul Vth) 6.20E E E ZigZg (dul Vth) 6.15E E E Sleepy Stck (dul Vth) 1.03E E E B.6. Adder dt 45

46 C.1.. Bse cse NAND schemtic 46

47 C.1.. Bse cse NAND lyout 47

48 C.2.. Stck pproch NAND Schemtic 48

49 C.2.. Stck pproch NAND Lyout 49

50 S S C.3.. Sleep pproch NAND Schemtic 50

51 C.3.. Sleep pproch NAND Lyout 51

52 S C.4..i. Zigzg pproch NAND Schemtic, PMOS sleep S C.4..ii. Zigzg pproch NAND Schemtic, NMOS sleep 52

53 C.4..i. Zigzg pproch NAND Lyout, PMOS sleep C.4..ii. Zigzg pproch NAND Lyout, NMOS sleep 53

54 S S S S C.5.. Sleepy stck pproch NAND Schemtic 54

55 C.5.. Sleepy stck pproch NAND Lyout 55

56 W/L=12 W/L=12 D.1.. Bse cse NOR Schemtic D.1.. Bse cse NOR Lyout 56

57 D.2.. Stck pproch NOR Schemtic 57

58 D.2.. Stck pproch NOR Lyout 58

59 W/ L=12 S W/ L=12 W/ L=12 S D.3.. Sleep pproch NOR Schemtic 59

60 D.3.. Sleep pproch NOR Lyout 60

61 W/L=12 S W/L=12 W/L=12 D.4..i. Zigzg pproch NOR Schemtic, PMOS Sleep W/L=12 W/L=12 S D.4..ii. Zigzg pproch NOR Schemtic, PMOS Sleep 61

62 D.4..i Zigzg pproch NOR Lyout, NMOS Sleep D.4..ii. Zigzg pproch NOR Lyout, PMOS Sleep 62

63 S S S S D.5.. Sleepy stck pproch NOR Schemtic 63

64 D.5.. Sleepy stck pproch NOR Lyout 64

65 TSMC 0.18µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 2.58E E E Stck 7.26E E E Sleep 3.63E E E ZigZg 5.62E E E Sleepy Stck 5.62E E E Sleep (dul Vth) 4.87E E E ZigZg (dul Vth) 7.41E E E Sleepy Stck (dul Vth) 7.41E E E Berkeley 0.18µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 1.77E E E Stck 5.50E E E Sleep 2.39E E E ZigZg 4.38E E E Sleepy Stck 4.38E E E Sleep (dul Vth) 3.36E E E ZigZg (dul Vth) 5.76E E E Sleepy Stck (dul Vth) 5.76E E E Berkeley 0.13µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 1.48E E E Stck 4.71E E E Sleep 2.07E E E ZigZg 3.59E E E Sleepy Stck 3.59E E E Sleep (dul Vth) 2.87E E E ZigZg (dul Vth) 4.86E E E Sleepy Stck (dul Vth) 4.86E E E Berkeley 0.10µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 1.11E E E Stck 3.51E E E Sleep 1.57E E E ZigZg 2.70E E E Sleepy Stck 2.70E E E Sleep (dul Vth) 2.12E E E ZigZg (dul Vth) 3.59E E E Sleepy Stck (dul Vth) 3.59E E E Berkeley 0.07µ Propgtion dely (s) Sttic Power (W) Dynmic Power (W) Are (µ 2 ) Bse cse 1.05E E E Stck 3.39E E E Sleep 1.56E E E ZigZg 2.58E E E Sleepy Stck 2.58E E E Sleep (dul Vth) 2.35E E E ZigZg (dul Vth) 3.97E E E Sleepy Stck (dul Vth) 3.97E E E E. 4-1 MUX dt 65