Memory Classification revisited. Introduction of edram

Transcription

1 Mmory Classification rvisitd Slid 1

2 Ky Points on Mmory classification Most of th Random Accss Mmoris us som kind of Row and Column basd architcturs. Unlik Static RAM, which has a gain lmnt to rtain th signal until powr down, DRAM nds th stord capacitors to b priodically rfrshd, hnc th trm Dynamic is attachd. DRAM rfrs to th DRAM mbddd insid th procssor chip. Slid 2

3 Fundamntal DRAM Opration Mmory Arrays ar composd of Row and Columns Most DRAMs us 1 Transistor as a switch and 1 Cap as a storag lmnt (Dnnard 1967) Singl Cll Accssd by Dcoding On Row / On Column (Matrix) Row (Word-Lin) conncts storag Caps to Columns (Bit-Lin) Storag Cap Transfrs Charg to Bit-Lin, Altring Bit-Lin Voltag R o w s Columns Th imag cannot b displayd. Your computr may not Word-Lin Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Th Rstart imag your cannot b displayd. Your computr may not computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. Bit-Lin Cap Transistor Slid 3

4 1T DRAM Cll Trminals Word-Lin (VWL to VPP Swing) Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. Bit-Lin (0 to VDD) Th ima g Cap( 0 to VDD) Back Bias (VBB - Bulk Only) VWL: Word-Lin Low Supply, GND or Ngativ for improvd lakag VPP: Word-Lin High Supply, 1.8V up to 3.5V dpnding on Tchnology Rquird to b at last a Vt abov VDD to writ full VDD VBB: Back Bias, Typically Ngativ to improv Lakag Not practical on SOI Slid 4

5 DRAM Cross sction Stor thir contnts as charg on a capacitor rathr than in a fdback loop. 1T dynamic RAM cll has a transistor and a capacitor Slid 5

6 Classical DRAM Organization (squar) bit (data) lins r o w d c o d r RAM Cll Array Each intrsction rprsnts a 1-T DRAM Cll word (row) slct row addrss Column Slctor & I/O Circuits Column Addrss data Slid 6

7 Logic Diagram of a Typical DRAM RAS_L CAS_L WE_L OE_L A 256K x 8 9 DRAM 8 D Control Signals (RAS_L, CAS_L, WE_L, OE_L) ar all activ low Din and Dout ar combind (D): WE_L is assrtd (Low), OE_L is disassrtd (High) D srvs as th data input pin WE_L is disassrtd (High), OE_L is assrtd (Low) D is th data output pin Row and column addrsss shar th sam pins (A) RAS_L gos low: Pins A ar latchd in as row addrss CAS_L gos low: Pins A ar latchd in as column addrss RAS/CAS dg-snsitiv Slid 7

8 DRAM Subarray Slid 8

9 DRAM logical organization (4 Mbit) Slid 9

10 DRAM architctur Slid 10

11 DRAM Rad 1. bitlin prchargd to V DD / 2 2. wordlin riss, cap. shars it charg with bitlin, causing a voltag ΔV 3. rad disturbs th cll contnt at x, so th cll must b rwrittn aftr ach rad ΔV V = 2 DD C C + cll cll C bit Slid 11

12 DRAM writ On a writ, th bitlin is drivn high or low and th voltag is forcd to th capacitor Slid 12

13 Embddd DRAM Advantags Mmory Advantag 2x Cach can provid > 10% Prformanc ~3x Dnsity Advantag ovr SRAM 1/5x Standby Powr Compard to SRAM Soft Error Rat 1000x lowr than SRAM Prformanc? DRAM can hav lowr latncy! IBM Powr7 tm 32MB DRAM L3 Dp Trnch Capacitor Low Lakag Dcoupling 25x mor Cap / µm 2 compard to planar Nois Rduction = Prformanc Improvmnt Isolatd Plat nabls High Dnsity Charg Pump Plat Nod 3.5um Slid 13

14 Dlay (ns) Embddd DRAM Prformanc 45nm DRAM vs. SRAM Latncy DRAM Total Latncy SRAM Total Latncy DRAM Wir/Rpatr Dlay SRAM Wir/Rpatr Dlay DRAM Fastr than SRAM 1Mb 4Mb 8Mb 16Mb 32Mb 64Mb Mmory Block Siz Built With 1Mb Macros Barth ISSCC 2012 Slid 14

15 Embddd DRAM Nod Advantag Poulson P7 Cors 8 8 L3 Cach 32MB SRAM 32MB DRAM Ara 544mm 2 567mm 2 Nod 32nm 45nm IBM Powr7 tm ISSCC 2011 Papr 4.9 ISSCC 2010 Papr 5.4 Slid 15

16 Som challngs in Embddd DRAM Slid 16

17 Rtntion Transfr Dvic and Storag Cap ar NOT idal dvics: thy LEAK Lakag Mchanisms includ: Ioff, Junction Lakag, GIDL,... Junction Lakag Tmpratur Dpndnc = 2x/10C Cll Charg nds to b rplnishd (Rfrshd), Mdian Rtntion Tim: T = C Δ V = 35fF x 400mV = 7 sconds Whr Δ V is accptabl loss I lak 2fA C is Cll Capacitanc is Total Lakag I lak Rtntion Distribution has Tails cratd by Dfcts and Laky Clls Wak Clls Tstd out (5x Guardband) and rplacd with Rdundancy Customr issus priodic Rfrsh Cycl # Clls Tst Fail Pass Rtntion Tim Slid 17

18 Floating Body Effcts Body potntial modulatd by coupling and lakag Bttr sourc followr vs. bulk during writ back (body coupling) Improvd writ 1 cll voltag Dgradd I off / Rtntion if body floats high (body lakag) GND pr-charg kps body low Eliminat long priods with BL high (limit pag mod) ILak FWD > ILak REV GND Whn BL = GND Body GND Th imag cannot b display d. d. Your comput Your r comput may not r may hav nough not mmory hav to nough opn th mmor imag, y to CA T h BL Th imag cannot b displayd. Your computr may not hav nough FWD WL Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Body Th imag cannot b displayd. Your computr may not hav nough REV Nod 1Volt Th imag cannot b Th imag cannot b b displayd. Your computr displayd. Your may not hav nough computr may not hav nough mmory to to opn th th imag, or or th th imag may hav bn corruptd. Rstart your computr, and thn opn th th fil fil again. If If th th rd x still appars, you appars, may hav you may to dlt hav to th dlt imag th and thn imag DT insrt and it thn again. insrt it again. BOX Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. NB

19 Array Body Coupling WL BL Body NODE Writ cycl Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. WL BL Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still 3 fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. appars, you may hav to dlt th imag and thn insrt it again. Body Th imag Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil cannot b again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. displayd. Your Th imag Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn cannot b th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. displayd. Your 2 Vt computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to Nod dlt th imag and thn insrt it again. 1 Body Coupling 1 = BL (Drain) 2 = WL (Gat) 3 = Nod (Sourc) Good Sourc Followr Slid 19

20 Array Body Charging Commodity DRAM (long pag mod) High Cll Lakag Priod Bit-Lin Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. Nt Body Charg from Lakag mbddd DRAM Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Th imag µ s Th Th Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. Bit-Lin T h i m a g c a T h i m a g c a T h i m a g ca n T h i m a g c a T h i m a g c a T h i m a g ca n T h i m a g c a T h i m a g c a T h i m a g c a T h i m a g c a T h i m a g c a T h i m a g c a Nt Body Charg from Lakag ns Slid 20

21 DRAM vs. SRAM Cycl-Tim Comparison NET: SRAM Random Cycl will continu to lad! Slid 21

22 DRAM Opration Dtails Slid 22

23 DRAM Rad, Writ and Rfrsh Writ: Rad: 1. Driv bit lin 2.. Slct row 1. Prcharg bit lin 2.. Slct row 3. Cll and bit lin shar chargs bit Vry small voltag changs on th bit lin 4. Sns (fancy sns amp) Can dtct changs of ~1 million lctrons 5. Writ: rstor th valu Rfrsh 1. Just do a dummy rad to vry cll. row slct Slid 23

24 Evry DRAM accss bgins at: Th assrtion of th RAS_L 2 ways to rad: arly or lat v. CAS DRAM Rad Timing RAS_L CAS_L WE_L OE_L A 256K x 8 9 DRAM 8 D DRAM Rad Cycl Tim RAS_L CAS_L A Row Addrss Col Addrss Junk Row Addrss Col Addrss Junk WE_L OE_L D High Z Junk Data Out High Z Data Out Rad Accss Tim Output Enabl Dlay Early Rad Cycl: OE_L assrtd bfor CAS_L Lat Rad Cycl: OE_L assrtd aftr CAS_L Slid 24

25 DRAM Writ Timing Evry DRAM accss bgins at: Th assrtion of th RAS_L 2 ways to writ: arly or lat v. CAS RAS_L CAS_L WE_L OE_L A 256K x 8 9 DRAM 8 D DRAM WR Cycl Tim RAS_L CAS_L A Row Addrss Col Addrss Junk Row Addrss Col Addrss Junk OE_L WE_L D Junk Data In Junk Data In Junk WR Accss Tim Early Wr Cycl: WE_L assrtd bfor CAS_L WR Accss Tim Lat Wr Cycl: WE_L assrtd aftr CAS_L Slid 25

26 DRAM Prformanc A 60 ns (t RAC ) DRAM can prform a row accss only vry 110 ns (t RC ) prform column accss (t CAC ) in 15 ns, but tim btwn column accsss is at last 35 ns (t PC ). In practic, xtrnal addrss dlays and turning around buss mak it 40 to 50 ns Ths tims do not includ th tim to driv th addrsss off th microprocssor nor th mmory controllr ovrhad. Driv paralll DRAMs, xtrnal mmory controllr, bus to turn around, SIMM modul, pins 180 ns to 250 ns latncy from procssor to mmory is good for a 60 ns (t RAC ) DRAM Slid 26

27 Transfr Ratio and Signal Δ Bit-Lin Voltag Calculatd from Initial Conditions and Capacitancs: Δ V = V bl - V f = V bl - Q = V bl - C bl *V bl +C cll *V cll C C bl +C cll C cll Δ V = (V bl - V cll ) C bl +C cll Transfr Ratio (typically 0.2) Δ Bit-Lin Voltag is Amplifid with Cross Coupl Sns Amp Sns Amp Compars Bit-Lin Voltag with a Rfrnc Bit-Lin Voltag - Rfrnc = Signal Pos Signal Amplifis to Logical 1, Ng Signal Amplifis to Logical 0 Slid 27

28 Short Bit-Lin, High Transfr Ratio mv 32 Bits/BL TR = Bits/BL TR = Transfr Ratio = TR = 0.33 C cll C cll +C bl Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, Th imag or th cannot imag b may displayd. hav bn Your corruptd. computr Rstart may not hav nough mmory to opn th imag, or th imag may hav bn your computr, and thn opn th fil again. If th rd corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and Th x still imag appars, cannot you b may displayd. hav to Your dlt thn computr th imag insrt may and it again. not thn hav insrt nough it again. mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and 3 Th thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. ima g Your can Th imag cannot b displayd. computr may not hav nough mmory not Your computr may not hav to opn th imag, or th imag may hav Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn nough mmory to opn th bn corruptd. Rstart your computr, corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and imag, th imag may hav and thn opn th fil again. If th rd x thn insrt it again. bn corruptd. Rstart your 10% Mor Writ Back still computr, appars, and you thn may opn hav th to dlt th imag fil again. and If thn insrt rd x still it again. appars, you may hav to dlt th imag and thn insrt it again Nod Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th 2 Th ima g can not b 2.3x Mor Signal Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. BL 1 Th ima g can not 2x Fastr Charg Transfr (90%) t = 2.3*R dv *(C bl *C cll )/(C bl +C cll ) ns Barth ISSCC 2007 Slid 28

29 Sgmntation Array Sgmntation Rfrs to WL / BL Count pr Sub-Array Longr Word-Lin is Slowr but mor Ara fficint (Lss Dcod/Drivrs) Longr Bit-Lin (mor Word-Lins pr Bit-Lin) Lss Signal (Highr Bit-Lin Capacitanc = Lowr Transfr Ratio) Mor Powr (Bit-Lin CV is Significant Componnt of DRAM Powr) Slowr Prformanc (Highr Bit-Lin Capacitanc = Slowr Sns Amp) Mor Ara Efficint (Fwr Sns Amps) Numbr of Word-Lins Activatd dtrmins Rfrsh Intrval and Powr All Clls on Activ Word-Lin ar Rfrshd All Word-Lins must b Rfrshd bfor Cll Rtntion Expirs 64ms Cll Rtntion / 8K Word Lins = 7.8us btwn rfrsh cycls Activating 2 Word-Lins at a tim = 15.6us, 2x Bit-Lin CV Powr Slid 29

30 Sns Amplifir Diffrntial Voltag Amplifid by Cross Coupl Pair V+ Δ V V BL I n0 Th Th imag cannot b b displayd. Your Your computr may not may hav not hav nough I+ n1 J Rfrnc BL St Nod Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your Whn St Nod < ( V+ Δ V ) - V tn1, I+ will start to flow (On-Sid Conduction) Whn St Nod < ( V ) - V tn0, I will start to flow (Off-Sid Conduction) Off-Sid Conduction Modulatd by St Spd and Amount of Signal Complimntary X-Coupl Pairs provid Full CMOS Lvls on Bit-Lin Slid 30

31 Sns Amplifir Slid 31

32 Slid 32

33 Mid-Lvl Rstor Sns Amplifir and Timings SETP Nod1 Strap VBLEQ WL1 EQP ST LDQT BT CBL MUX CSL SC LDQC BC CBL WL0 VBLEQ Strap Nod0 SETN Rad 1 Nod1 Writ Back Rstor Rad 0 Writ Back Rstor Nod1 ST BT ST BT Nod1 LDQC LDQC BC SC SC BC Nod0 Nod0 Slid 33

34 Nois Coupling and Local Procss Variation ffctivly dgrads signal Extrnal Nois (Wir or Sx) Rducd to Common Mod by Folding BL SA BL SA Opn Lin to Lin Coupling Limitd by Bit-Lin Twisting Foldd BL BL A A B B AB AB AB A Coupls Equally into B and B AB V t and Δ L Mis-Match Limitd by Longr Channl Lngth Ovrlay Mis-Alignmnt Limitd by Idntical Orintation Capacitiv Mis-Match Limitd by carful Physical Dsign (Symmtry) Slid 34

35 Opn and Foldd Bitlin Schms Slid 35

36 Opn and Foldd Bitlin Schmatic Slid 36

37 Foldd Bitlin Layout Slid 37

38 Intrlavd Sns Amp w/ Bit-Lin Twist Local Array Data Bit 0 Data Bit N Data Bit 127 Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. SA Column Dcod SA SA SA Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. 1 of 8 Column Dcod W r i t L o c a l R a d W r i t L o c a l R a d W r i t L o c a l R a d SA SA SA SA Column Dcod Slid 38

39 Som Dvic Fabrication Aspcts Slid 39

40 Accss Transistor Dsign: WordLin (WL) Swing CrossChip -4.5σ ChipMan ± 3σ CrossChip +4.5σ V t, nom V V WLL t, min V t, max V PP Rtntion Prformanc Margin Margin V t Variability WL=V WLL WL=V pp BL=Gnd BL=V dd RETENTION mod WRITE mod Control of CrossChip σ (Random Dopant Fluctuation) is critical Slid 40

41 Accss Transistor Dsign: HKMG Advantag V WLL V t, min V t, max V PP Rtntion Margin V t, nom V t Variability Prformanc Margin HKMG V t, nom V WLL V t, min V t, max VPP Rtntion Margin V t Variability Prformanc Margin HKMG boosts prformanc/rtntion by rducing RDF Slid 41

42 High-K Mtal Nod Dp Trnch (HK/M DT) Poly Poly TiN HfO 2 Implantd plat DT Rsistanc (a.u.) Normalizd DT Rsistanc SiON/Poly HK/M Rows TiN HfO2 intrfacial dilctric 3X improvmnt in trnch rsistanc with HK/M procss 42 Slid 42

43 Bit-Lin Capacitanc Bulk 10-20% CA N Th imag cannot b displayd b. display Your computr d. Your may comput not hav r may nough not hav mmory nough to mmory opn th to opn imag, th or th imag, imag may or th hav WL Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your Th imag cannot b Th imag cannot b Th imag cannot b Th imag cannot b b displayd. Your computr displayd. Your computr displayd. Your computr displayd. Your may not hav nough may not hav nough may not hav nough computr may not hav mmory to opn th imag, mmory to opn th imag, mmory to opn th imag, nough hav nough mmory mmory to opn or th imag may hav bn or th imag may hav bn or th imag may hav bn th to opn imag, th or imag, th imag or may th imag hav bn may hav Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th corruptd. bn corruptd. Rstart your imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still computr, Rstart your and computr, thn appars, you may hav to dlt th imag and thn insrt it again. opn and thn fil opn again. th fil If th again. rd If x th still rd appars, x still you appars, may hav you may to dlt hav th to dlt imag th and imag thn P-WELL insrt and thn it again. insrt it again. Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. N-Band M1 Bitlin Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. P N CA N Th imag cannot imag b displayd. cannot Your b computr displayd may. Your not hav comput nough r may mmory not hav to nough opn th mmory imag, or to th opn imag th may imag, hav or bn th Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn SOI Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. WL Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your P Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn BOX 1% N-Band M1 Bitlin Th imag cannot b Th imag cannot b b displayd. Your computr displayd. Your may not hav nough computr may not hav mmory to opn th imag, nough mmory to to opn or th imag may hav bn th opn imag, th imag, or th or imag th may imag hav may bn hav bn corruptd. Rstart your computr, and thn opn th th fil fil again. If If th th rd x still appars, you may hav to to dlt th th imag and thn insrt it it again. Th imag cannot b displayd. Your computr may not hav nough mmory to opn th imag, or th imag may hav bn corruptd. Rstart your computr, and thn opn th fil again. If th rd x still appars, you may hav to dlt th imag and thn insrt it again. N DT DT Slid 43

44 Conclusion DRAM dsign and rlvant procss stps has volvd normously to nabl thm to b mbddd into procssor. Thr ar som issus whn DRAM in mbddd into main cor, but thr hav bn som smart nginring choics and dsign and layout tricks to solv thm. Slid 44

45 Acknowldgmnt John Barth, IBM SRDC for most of th slids contnt. Slid 45