VLSI Design 15. Dynamic CMOS Circuits

Transcription

1 VI Desig 5. Dyamic MO ircuits 5. ircuit Families ast module: Memory arrays RMs erial Memories Dyamic memories This module Pass trasistor logic Pseudo MO logic Dyamic logic ook at peedig Up ircuits hat makes a circuit ast? 4 I = dv/dt -> t pd (/I) ΔV low capacitace 4 high curret small swig ogical eort is proportioal to /I pmo are the eemy! igh capacitace or a give curret a we take the pmo capacitace o the iput? Various circuit amilies try to do this D. Z. Pa 5. Dyamic MO ircuits D. Z. Pa 5. Dyamic MO ircuits Pseudo-MO I the old days, processes had o pmo Istead, use pull-up trasistor that is always ON I MO, use a pmo that is always ON Ratio issue Make pmo about ¼ eective stregth o pulldow etwork load P/ I ds V out 6/ V i V out P = 4 P = 4 P = Pseudo-MO Gates Desig or uit curret o output to compare with uit iverter pmo ights MO Iverter NND NOR /3 4/3 g u = 4/3 g d = 4/9 g avg = 8/9 p u = 6/3 p d = 6/9 p avg = /9 /3 8/3 8/3 g u = 8/3 g d = 8/9 g avg = 6/9 p u = /3 p d = /9 p avg = /9 g u = 4/3 g d = 4/9 /3 g avg = 8/9 p u = /3 4/3 4/3 p d = /9 p avg = /9 V i D. Z. Pa 5. Dyamic MO ircuits 3 D. Z. Pa 5. Dyamic MO ircuits 4 Pseudo-MO Desig Ex: Desig a k-iput ND gate usig pseudo-mo. Estimate the delay drivig a aout o G = * 8/9 = 8/9 I k F = G = 8/9 P = + (4+8k)/9 = (8k+3)/9 N = D = NF /N 4 8k P = + I 3 9 Pseudo-MO D. Z. Pa 5. Dyamic MO ircuits 5 Pseudo-MO Power Pseudo-MO draws power wheever = alled static power P = I V DD ew m / gate * M gates would be a problem This is why MO wet extict! Use pseudo-mo sparigly or wide NORs Tur o pmo whe ot i use e D. Z. Pa 5. Dyamic MO ircuits 6 D. Z. Pa

2 VI Desig 5. Dyamic MO ircuits Dyamic ogic Dyamic gates uses a clocked pmo pullup Two modes: precharge ad evaluate /3 4/3 tatic Pseudo-MO Dyamic Evaluate The Foot hat i pull-dow etwork is ON durig precharge? Use series evaluatio trasistor to prevet ight precharge trasistor oot ooted uooted D. Z. Pa 5. Dyamic MO ircuits 7 D. Z. Pa 5. Dyamic MO ircuits 8 ogical Eort Mootoicity uooted ooted Iverter NND NOR g d = /3 p d = /3 g d = /3 3 3 g d = /3 g d = 3/3 3 p d = 4/3 g d = /3 g d = /3 p d = 5/3 Dyamic gates require mootoically risig durig evaluatio -> -> -> ut ot -> Evaluate violates mootoicity durig evaluatio D. Z. Pa 5. Dyamic MO ircuits 9 Output should rise but does ot D. Z. Pa 5. Dyamic MO ircuits Mootoicity oes ut dyamic gates produce mootoically allig outputs durig evaluatio Illegal or oe dyamic gate to drive aother! = Evaluate mootoically alls durig evaluatio should rise but caot Domio Gates Follow dyamic stage with ivertig static gate Dyamic/static pair is called domio gate Produces mootoic outputs domio ND dyamic NND static iverter Z Evaluate Z Z = Z D. Z. Pa 5. Dyamic MO ircuits D. Z. Pa 5. Dyamic MO ircuits D. Z. Pa

3 VI Desig 5. Dyamic MO ircuits Domio Optimizatios Each domio gate triggers ext oe, like a strig o domios topplig over Gates evaluate sequetially, precharge i parallel Evaluatio is more critical tha precharge I-skewed static stages ca perorm logic Dual-Rail Domio Domio oly perorms oivertig uctios: ND, OR but ot NND, NOR, or OR Dual-rail domio solves this problem Takes true ad complemetary Produces true ad complemetary outputs D 4 D4 D 5 D5 D 6 D6 3 D3 7 D7 sig_h sig_l Meaig d ivalid _l _h D. Z. Pa 5. Dyamic MO ircuits 3 D. Z. Pa 5. Dyamic MO ircuits 4 Example: ND/NND Give _h, _l, _h, _l ompute _h = *, _l = ~( * ) Pulldow etworks are coductio complemets _l = * _l _l _h _h _h = * Example: OR/NOR ometimes possible to share trasistors _l _h = xor _h _l _l _h = xor _l _h D. Z. Pa 5. Dyamic MO ircuits 5 D. Z. Pa 5. Dyamic MO ircuits 6 eakage Dyamic ode loats high durig evaluatio Trasistors are leaky (I OFF ) Dyamic value will leak away over time Formerly millisecods, ow aosecods! Use keeper to hold dyamic ode Must be weak eough ot to ight evaluatio weak keeper eakage Power! k harge harig Dyamic gates suer rom charge sharig x = harge sharig oise x x V = V = V x DD x + D. Z. Pa 5. Dyamic MO ircuits 7 D. Z. Pa 5. Dyamic MO ircuits 8 D. Z. Pa 3

4 VI Desig 5. Dyamic MO ircuits ecodary olutio: add secodary precharge trasistors Typically eed to precharge every other ode ig load capacitace helps as well x secodary precharge trasistor Noise esitivity Dyamic gates are very sesitive to oise Iputs: V I V t Outputs: loatig output susceptible oise Noise sources apacitive crosstalk harge sharig Power supply oise Feedthrough oise d more! D. Z. Pa 5. Dyamic MO ircuits 9 D. Z. Pa 5. Dyamic MO ircuits lteratig N & P Domio ogic INPUT (stable durig = ogic lock other P blocks p ogic lock other N blocks p ogic lock VDD other P blocks To urther P blocks Domio ummary Domio logic is attractive or high-speed circuits.5 x aster tha static MO ut may challeges: Mootoicity eakage harge sharig Noise Used to be widely used i high-perormace microprocessors D. Z. Pa 5. Dyamic MO ircuits D. Z. Pa 5. Dyamic MO ircuits Pass Trasistor ircuits Use pass trasistors like switches to do logic Iputs drive diusio termials as well as gates MO + Trasmissio Gates: -iput multiplexer Gates should be restorig EP E itegratio with Pass trasistors Get rid o pmo trasistors Use weak pmo eedback to pull ully high Ratio costrait D. Z. Pa 5. Dyamic MO ircuits 3 D. Z. Pa 5. Dyamic MO ircuits 4 D. Z. Pa 4

5 VI Desig 5. Dyamic MO ircuits omplemetary Pass-trasistor ogic (P) Dual-rail orm o pass trasistor logic voids eed or ratioed eedback Optioal cross-couplig or rail-to-rail swig D. Z. Pa 5. Dyamic MO ircuits 5 D. Z. Pa 5