A Novel Current-Mode Min-Max Circuit

Transcription

1 1 Abstact: A Novel Cuent-Mode Min-Max Cicuit Ai Alikhani and Aash Ahadi This pape pesents a new CMOS cuent ode Min-Max cicuit. The poposed cicuit has lowe nube of tansistos, can detect iniu and axiu of the input cuents at the sae tie, shows hih pecision and has a low cell aea. It is desined in 0.5μ standad CMOS technoloy. Layout of the poposed stuctue is accoplished to extact the paasitic coponents, whee all the siulations ae pefoed with HSPICE level49 (BSIM3v3) paaetes obtained fo post layout cicuit extaction. 1. Intoduction Analo iniu-axiu cicuits, ae vesatile buildin blocks fo any applications such as analo sinal pocessin, fuzzy loic contolles, atificial neual netwoks, hih pecision half-wave and full-wave ectifies, telecounications, instuentations, sinal peak detectos, deodulatos etc. Analo in-ax functions ae obtained fo WTA (Winne-Take-All) cicuits [1-4]. Due to the siplicity, the poposed cicuit in [1] has been the statin point fo any in-ax cicuits in fuzzy loic applications [4,5]. Pesented cicuits in [6,7] use two diffeent stuctues fo in-ax cicuits. Usin cuent-ode analo cicuit desin has eceived wide attention due to the supply voltae scalin down and thei potential of lowe powe consuption, ate oxide beakdown [8,9,10]. This pape pesents a new cuent ode siultaneous Min-Max selecto based on CMOS technoloy with a unique stuctue. In section, poposed in-ax is explained. Pefoance analysis is accoplished in section 3. Siulation esults, to veify the pefoance of the in-ax cicuit, ae pesented in section 4; whee the

2 siulations ae pefoed with HSPICE and level49 (BSIM3v3) paaetes fo MOS tansistos. Pesented siulation esults ae obtained fo post-layout cicuit extactions to take into account paasitic coponents and seconday effects. Siulation esults confied the pefoance of the poposed in-ax. Conclusion of this wok is pesented in section 5.. The Poposed Cicuit The poposed in-ax cicuit is depicted in Fi.1. Opeation of the cicuit is based on the odified-wilson cuent io in botto of the Fi.1, which ceates equal cuent in the banches unde nodes A and B. Let us assue one of the input cuents, fo instance I inceases and (I 1 <I ). This ise leads to a voltae incease at the node B in copaison with the node A. Due to this diffeence M13 is on and M14 tuns off, hence an exta cuent equal to I -I 1 is tansfeed to the othe cuent io thouh M13 and will be added to the iniu cuent of inputs (I 1 ) to poduce the axiu output of the inputs which in this case is I. In othe wods, to obtain axiu of the inputs, the absolute diffeence between two inputs ( I 1 -I ) is added to the iniu cuent value of the. Siilaly, if (I 1 >I ), then node voltae of A inceases in copaison with the node voltae of B. Theefoe, M13 is off and M14 is on and the exta cuent (I 1 -I ) is tansfeed to the cuent io thouh M14 and will be added to the iniu cuent of the inputs to poduces the axiu value of the two input cuents. If the input cuents ae equal, two node voltaes of A and B will be equal and both tansistos M13 and M14 will tun off. In this case, both output cuents of the cicuit, iniu and axiu, ae equal. Usin this stuctue, both iniu and axiu of the inputs ae siultaneously detected. Obviously, one can eplace the odified-wilson cuent io in Fi.1 with a siple cuent io. In this way, cicuit can be ipleented with only 8 tansistos which esults in ove 50% decease in tansisto usae and cicuit aea; howeve,

3 3 this will sacifice pecision of the iniu and axiu outputs. Next section pesents esult siulations. 3. Pefoance Analysis In this section the chaacteistics of poposed Min-Max as shown in Fi. 1 such as input and output ipedance, and dynaic ane of inputs ae consideed. 3.1 Ipedances Input ipedances ae obtained fo two input pots individually. As shown in Fi. a, fist conside a state in I 1 >I, so M 14 is on and ΔI pass thouh M 14, the input ipedance fo node A can be witten as follows: in7 in7 s,14 (1) whee in7 and S,14 ae ipedances fo dain of M 7 and souce of M 14, espectively. eplacin the sall sinal odel fo tansistos in Fi. b yields: S14 o14 D 1 14o14 () In siila way sae equation obtained fo S13 (with chanin all 14 indexes with 13). D can be witten as: D 1 o 5 (3) 11 Substitutin (3) in () ives:

4 o o o S S (4) eplacin the sall sinal odel fo tansistos in Fi. a and assue all ae equal with a easonable appoxiation, we have: L o o in 7 7 () whee L is ipedance of the cuent souce of I that is ust be vey lae to iniize loadin effect. So L >> o then we have: (3) Then final esult can be witten as: 14,14, s s in in (4) Siilaly to othe input pot when I >I 1 and ΔI pass thouh M 13, as shown in Fi.c M 13 is on and the input ipedance fo node B can be witten as:, s in in (5) Assue S,13 /,13 and in siila way fo in8 yields: I V o L L o x x in (6) Assue all ae equal and ( L >> o), then we have: o L L o in (7) 7 7 o o in

5 5 Then final esult can be witten as: in8 in 8 s,13 s,14 (8) 13 Thus in both cases the input ipedances ae vey sall which is pefeed when inputs ae cuent. It is clea that with inceasin aspect atio, input ipedances ae ipoved with sacificin die chip aea and speed of cicuit. Output ipedance fo iniu output pot obtained as: out, Min o 1 o (9) And fo axiu output pot obtained as: out, Max 1 o o o o (10) So in both output pots ipedances ae enouh lae to tansfein all of output cuents to the load. Accodin to the equations, to ipove the input ipedances, one needs to incease the aspect atio and/o DC cuent bias. In evese, to ipove the output ipedance of the cicuit, one should decease DC cuent bias. Theefoe thee is a tadeoff to achieve the optial point. 3. Dynaic ane Fo siplicity please nelect body effect, econside Fi. 1, to opeate tansistos in satuation eion, in the node B: V B VGS8 VDS, sat (11) V B I I Vth (1) 8 Whee β=μc ox (W/L) is tansconductance paaete and V th is theshold voltae, assue β 1 = β = = β 1 = β, β 13 = β 14 and afte soe woks:

6 6 I V V B th I X 1 (13) Siilaly to node A, we have: V A VGS1 VDS 7, sat (14) V A I I Vth (15) 1 7 Afte soe woks: I V V A th I X (16) I MAX Min X 1, X (17) To obtain the ane of ΔI please assue I >I 1, then: V C VGS11 VDS 5, sat (18) V C I V th I (19)

7 7 V V I C th (0) eplace V C with followin equation: I I I VC VGS 6 VGS1 Vth Vth V th (1) Then: I V V th th I () I 8 V th 0 (3) So: I 0 (4) To obtain axiu ane of ΔI please note that the ai of usin M13 and M14 is ceatin an exta path fo absolute diffeence of the inputs cuent. Theefoe eithe these tansistos wok in satuation o in tiode eion the exta cuent passes thouh this exta path ceated by M13 and M14. Accodinly, ΔI eaches to its axiu when M13 o M14 ae in tiode eion. Please conside a situation that M13 is in tiode eion, theefoe: V BC V SD 13, sat (5)

8 8 V V B C V V GS1 GS 6 V V GS 7 GS1 (6) Substitutin (6) in (5) yields: I I I I I V V th th Vth V th (7) 13 Afte soe atheatical anipulation: 4I I (8) 13 Above equation shows the iniu value of ΔI that M13 and M14 ae in tiode. So the axiu ane of ΔI is equal to I dc. Fo instance, in this cicuit we used 5μA as I dc fo both inputs. The siulation esults fo axiu dynaic ane ae shown in Fi Siulation esults To veify pefoance of the poposed cicuit, HSPICE siulations wee pefoed usin TSMC 0.5μ LEVEL49 (BSIM3v3) CMOS pocess paaetes. Siulation esults ae obtained fo post layout siulations takin into account paasitic coponents. Fi. 3 shows both in and ax outputs fo a ane of two DC inputs cuents copaed with the ideal iniu and axiu outputs. Absolute and aveae eo values ae depicted fo both iniu and axiu outputs in Fi. 4. Tansient analysis with two diffeent types of inputs is also accoplished. Fistly, sinusoidal inputs with two diffeent fequencies as: 0.5MHz and 1MHz ae applied to the inputs as I1 and I espectively and esults ae shown in Fi. 5 to Fi. 8.

9 9 Secondly, tianula inputs with diffeent fequencies as: 1MHz and 5MHz as I1 and I espectively and esults ae shown in Fi. 9 and Fi. 10. It is attainable fo all these esults that eo of the iniu and axiu outputs of the poposed cicuit ae vey sall, which akes it a suitable choice fo hih pecision application. To conside delay of the poposed cicuit and in othe wod obtained axiu speed of the poposed in-ax, pulse input is applied to the cicuit. To veify the axiu ane of ΔI, iniu and axiu outputs fo sinusoidal inputs ae shown in Fi. 11. Pulse input with fequency of 50MHZ is applied, whee esults ae shown in Fi. 1. Maxiu delay in isin o fallin ede of the output is consideed as delay of the cicuit, which is about ns. Siulations ae also pefoed fo diffeent tepeatues as: 5ºC, 50ºC, 75ºC and 100ºC which esults ae shown in Fi. 13. As it is attainable fo siulation esults, cicuit has a neliible theal sensitivity. Layout of the in-ax cell is shown in Fi. 14. This cell occupies 17.65μ 8.15μ silicon aea. As it entioned analo in-ax cicuits ae vesatile buildin blocks that have any applications. As an exaple, a hih pecision ectifie is ipleented usin poposed in-ax buildin block as pesented in Fi. 15a. As it is known, usin odinay diode is not suitable to ectify vey sall sinals whee aound theshold and sub theshold points the output will have a consideable distotion. Nowadays, pocessin sall sinals ae equied in any applications such as instuentation systes, eney havestin devices, etc. As it shown in Fi. 15a, one of the inputs of the poposed in-ax cicuit is constant o only has DC value and the othe input is connected to the desied sinal to be ectified. As it cleas only with poposed inax and a cuent io hih pecision full-wave ectifie is obtained. esult obtained is shown in Fi. 15b. The diensions of used tansistos in poposed inax cicuit ae W=L=0.63μ.

10 10 5. Conclusions This pape pesents a new siultaneous cuent-ode in-ax selecto in 0.5μ CMOS standad technoloy. Usin only one stuctue to distinction in-ax, low usae device, hih speed and pecision and low die chip aea ae specifications of the poposed cicuit. Lay out of the poposed stuctue is accoplished and obtained paasitic coponents fo it also take account in all of the siulation esults that confied pefoance of the poposed cicuit.

11 11 efeences: [1] Lazzao J, yckebusch S, Mahowald MA, Mead CA. Winne-take-all netwoks of O(N) coplexity. In: Touetzky DS, edito. Advances in neual sinal pocessin systes. Los Altos, CA: Moan Kaufann; [] aiez-anulo J, Ducouday-Acevedo G, Cavajal, Lopez-Matin A. Lowvoltae hih-pefoance voltae-ode and cuent-ode WTA cicuits based on flipped voltae followes. IEEE Tansactions on Cicuits and Systes II: Expess Biefs; 5:40 3, 005 [3] Poee P, Chattakun K, "CMOS WTA axiu and iniu cicuits with thei applications to analo switch and ectifies," Micoelectonics Jounal, Vol.4, No.1, pp. 5-6, 011. [4] Batuone I, Huetas J, Baia A, Sanchez-Solano S. Cuent-ode ultiple-input ax cicuit. Electonics Lettes; 30(9):678 80, 1994 [5] Peyanfa A, Khoei A, Hadidi K, Desin of a eneal popose neuo-fuzzy contolle by usin odified adaptive-netwok-based fuzzy infeence syste. Intenational Jounal of Electonic and Counications (AEÜ) 64, , 009. [6] Yosefi Gh. Ainifa S. Neda Sh. Daneshwa M.A. Desin of a ixedsinal diital CMOS fuzzy loic contolle (FLC) chip usin new cuent ode cicuits. Intenational Jounal of Electonic and Counications (AEÜ), 010. [7] Poee P, Ankeaw K, Sodunyakanok M, Dejhan K. CMOS-based nea zeo-offset ultiple inputs ax in cicuits and its applications. Analo Inteated Cicuit and Sinal Pocessin, 61:93 105, 009. [8] Wilson, B. ecent developents in cuent conveyos and cuent-ode

12 1 cicuits. IEE Poceedins Cicuits, Devices and Systes, 137():63-77, [9] obets, G. W., Seda, A. S. All cuent-ode fequency selective cicuits. Electonics Lettes, 5(1): , [10] Yuan F. CMOS cuent-ode cicuit fo data counications. Analo Cicuit and Sinal Pocessin (ASCP), ISBN: , Spine 007.

13 13 Fiue Captions: Fi. 1: Poposed Min-Max cicuit. Fi. : Equivalent cicuit to calculate input ipedances a) Calculate ipedance fo node A b) Calculate ipedance fo souce of M13 o M14 c) Calculate ipedance fo node B. Fi. 3: DC inputs applied to the poposed Min-Max copaed with ideal outputs. Fi. 4: Output eo fo DC inputs a) Absolute and aveae eo fo the iniu output b) Absolute and aveae eo fo the axiu output. Fi. 5: a) Miniu output of the poposed in-ax cicuit fo sinusoidal inputs (Feq. I1=0.5MHz and I=1MHz), b) Coespondin absolute and aveae eo values. Fi. 6: a) Miniu output of the poposed in-ax cicuit fo sinusoidal inputs (Feq. I1=1MHz and I=0.5MHz), b) Coespondin absolute and aveae eo values. Fi. 7: a) Maxiu output of the poposed in-ax cicuit fo sinusoidal inputs (Feq. I1=0.5MHz and I=1MHz), b) Coespondin absolute and aveae eo values. Fi. 8: a) Maxiu output of the poposed in-ax cicuit fo sinusoidal inputs (Feq. I1=1MHz and I=0.5MHz), b) Coespondin absolute and aveae eo values. Fi. 9: a) Miniu b) Maxiu outputs of the cicuit fo tianula inputs (Feq. I1=1MHz and I=5MHz). Fi. 10: a) Miniu b) Maxiu outputs of the cicuit fo tianula inputs (Feq.

14 14 I1=5MHz and I=1MHz). Fi. 11: a) Maxiu ane of ΔI: Miniu output of the poposed in-ax cicuit fo sinusoidal inputs b) Maxiu output of the poposed in-ax cicuit fo sinusoidal inputs (Feq. I1, =1MHz). Fi. 1: Input ideal pulse with fequency of 50MHz. Fi. 13: Tepeatue sensitivity of the poposed cicuit in 5ºC, 50ºC, 75ºC and 100ºC. Fi. 14: Lay out of the poposed in-ax cicuit. Fi. 15: a) Poposed block diaa fo hih pecision full-wave ectifie, b) Output full-wave ectified sinal with (aplitude =10μA and Feq. = 1MHz).

15 15 Fiue 1: I1 I Iin Iax A I M13 M14 B I I ΔI C I+ΔI ΔI M7 M8 M9 M10 M11 M1 M1 M M3 M4 M5 M6

16 16 Fiue : Ix A s,14 Vx + - in7 M14 in7 D L M7 M8 M1 M (a) Ix s,13 o s,14 Vx + - M13 o M14 in D G (b) s,13 B M13 in8 + - Vx L D 'in8 M7 M8 M1 M (c)

17 17 Fiue 3: 10u 9.5u 9u 8.5u 8u 7.5u 7u 6.5u 6u 5.5u 5u 4.5u 4u 3.5u 3u.5u u 1.5u 1u 0.5u 0 Iout [ua] 0u 1u u 3u 4u 5u 6u 7u 8u 9u 10u Inputs [ ua] * I Maxiu output obtained fo poposed Min- Max by HSPICE Ideal axiu of two inputs by HSPICE Miniu output obtained fo poposed Min -Max by HSPICE Ideal iniu of two inputs by HSPICE I1

18 18 Fiue 4: 180nA 160nA 140nA 10nA 100nA 80nA 60nA 40nA 0nA 0 EO 0u 1u u 3u 4u 5u 6u 7u 8u 9u 10u Inputs [ua] 10nA 9nA 8nA 7nA 6nA 5nA 4nA 3nA EO (a) 0u u 4u 6u 8u 10u Inputs [ua] (b)

19 19 Fiue 5: 10u 8u Cuent [ua] I I1 6u 4u u 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie [ us ] (a) 500nA EO 400nA 300nA 00nA 100nA n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie [ us ] (b)

20 0 Fiue 6: 10u 8u 6u 4u u Cuent [ua] I1 I 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us ] EO 400nA 350nA 300nA 50nA 00nA 150nA 100nA 50 na 0 (a) 0 00n 400n 600 n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us ] (b)

21 1 Fiue 7: 10u 8u Cuent [ua] I I1 6u 4u u 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie [ us ] (a) EO 600nA 400nA 00nA n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie [ us ] (b)

22 Fiue 8: 10u 8u 6u 4u u Cuent [ua] I I1 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us] (a) 700nA EO 600nA 500nA 400nA 300nA 00nA 100nA n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us]

23 3 Fiue 9: 10u Cuent [ua] I I1 8u 6u 4u u 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie [ us ] (a) 10u Cuent [ua] I I1 8u 6u 4u u 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie [ us ] (b)

24 4 Fiue 10: 10u 8u 6u 4u u Cuent [ua] I1 I 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us] (a) 10u 8u 6u 4u u Cuent [ua] I1 I 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us] (b)

25 5 Fiue 11: Cuent [ua] 10u I I1 8u 6u 4u u 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us] (a) 10u Cuent [ua] I I1 8u 6u 4u u 0u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie[ us] (b)

26 6 Fiue 1: Cuent [ua] 10u 8u 6u 4u u 0u 0 5n 10n 15n 0n 5n 30n 35n 40n 45n 50n Tie[ ns]

27 7 Fiue 13: 10u Cuent [ ua] 9.5u 9u 8.5u 8u 7.5u 7u 6.5u 6u 5.5u 5u 4.5u 4u 3.5u 3u.5u u 1.5u 1u 0.5u 0 0u 1u u 3u 4u 5u 6u 7u 8u 9u 10u Inputs [ ua] Miniu output in 5ºC Maxiu output in 5ºC Miniu output in 50ºC Maxiu output in 50ºC * Miniu output in 75ºC Maxiu output in 75ºC Miniu output in 100ºC Maxiu output in 100ºC Ideal iniu and axiu also depicted

28 8 Fiue 14: Iin1 Iin Vdd Iin Iax 8.15μ Gnd 17.65μ

29 9 Fiue 15: Powe Supply.5V Input Cuent Mio 1 : 1 Output Maxiu Cuent Maxiu Cuent Idc Miniu Cuent Output Full-Wave ectified Cuent Input Cuent Iac Input1 Poposed Min-Max Idc Input (a) 10u Cuent [ua] 8u 0u u 4u 6u -u -4u -6u -8u -10u 0 00n 400n 600n 800n 1u 1.u 1.4u 1.6u 1.8u u Tie [ us] (b)