Controllable LFSR BIST. Controller C U T. Phase shifter MISR. Embedded Memory

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1 .Rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, P.Venkt Gopikumr PG Scholr / Interntionl Journl of Enineerin Reserch nd pplictions (IJER) ISSN: Vol. 2, Issue 5, September- October 22, pp Fult Detection y Usin Rndom nd Deterministic Test Pttern Techniques In Mixed-Mode IST Environment.Rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, & P.Venkt Gopikumr PG Scholr Deprtment of Electronics & ommuniction Enineerin Jwhrll Nehru Technoloicl University nntpur, Indi bstrct method for testin embedded core bsed system chips is to use built-in-self-test (IST). mixed-mode (Prtil pttern mtchin nd multi-control-sequence) built-in-self-test (IST) tht brins two new techniques. They re prtil pttern mtchin nd multi control sequence. Prtil pttern mtchin llows the reduction of the number of ptterns used for detectin rndom-pttern-resistnt fults without usin the fult simultion. multi control sequence is used to uide the liner feedbck shift reister (LFSR) to enerte these ptterns t ppliction time. The min dvntes of this method re reduction of the test dt volume, require less time to test the ppliction nd its reusbility for loic cores on system-on-chip (SO). Index Terms -uilt in self-test (IST), Liner feedbck shift reister (LFSR), rndom-ptternresistnt (RPR) fults, system-on-chips (SOs).. Introduction Desin intertion cn be incresed by mkin the Is smll size nd power should be low. The requirements for smll size nd low-power Is hve cused sinificnt increse in desin intertion. the intertion severl desins (cores) into sinle monolithic I which results in systemon-chip (SO). The number of cores interted in SO is rpidly incresin, resultin in lre mount of test dt. To chieve the ood test qulity for the complex SO by usin the finite number of I/Os is very difficult tsk. The mount of time required for this type of test ppliction is hih, it is lso bi problem to overcome ll these drwbcks nd for testin embedded core bsed system chips is to use built-in self-test (IST). The dvntes of built-in cell-test (IST) re simplicity, flexibility nd low overhed. The test pttern enertor for the IST is pseudorndom (PR) test pttern enertor for its onchip test pttern enertion. Pseudorndom test pttern enertion (PRPG) cn be implemented by usin liner feedbck shift reister. LFSR hs severl dvntes. They re low overhed, sclbility nd reuse cpbility. Fults tht re difficult to detect by pseudorndom pttern enertion (PRPG) re clled rndom-pttern-resistnt (RPR) fults. To increse the probbility of detectin the RPR fults by followin the three cteories. ut these three cteories hve drwbcks The modifiction of circuit under test The use of weihted rndom pttern enertion. The mixed mode pproch. The first cteory improves fult covere by redesinin or insertin test points. It is not lwys possible becuse of performnce restriction or intellectul property (IP) resons. The second cteory is lso to increse the probbility for test ptterns to detect RPR fults, but it is not efficient the third cteory consists of two phses: In the first phse, PR ptterns re pplied to detect the fults here fult covere is done by 6% to 8% only. In the second phse, deterministic test ptterns re injected to find the reminin fults. The deterministic ptterns re enerted by the LFSR[] by reseedin re pplin control sinl tht mtches the output of the LFSR to the desired deterministic ptterns. new technique for the enertion of the test ptterns for RPR fults by controllin the LFSR t the time of test ppliction. This technique is clled prtil pttern mtchin. Select IST[2] usin controllble LFSR with multiple scn chins to enerte deterministic ptterns. In this pproch, the system intertor is ble to develop the core s tests without knowin the ctul implementtion of the core becuse providin deterministic test ptterns nd the S-mtrix by the core provider. Hence, the method promotes desin nd test reuse without chnin or revelin IP informtion. Prtil-mtchin technique lon with multiple scn chins the IST reter usin controllble LFSR, the ols such re To reduce the test dt volume To shorten the test ppliction time Reusbility for loic cores These three mjor ols cn be chieved by mixed mode IST. When comprin this method mixed-mode IST environment to other mixed-mode pproches. In 72 P e

2 ontrollble LFSR Phse shifter MISR.Rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, P.Venkt Gopikumr PG Scholr / Interntionl Journl of Enineerin Reserch nd pplictions (IJER) ISSN: Vol. 2, Issue 5, September- October 22, pp Most mixed modes, the test flow is outlined in Fi. (). Our methodoloy is shown in Fi. (b): First, deterministic TPG is used. The ptterns re then prtilly mtched. The reminin ptterns re enerted by pplyin control sequence to the LFSR[]. In our rchitecture shown in Fi. 2: It consists of controllble LFSR nd phse shifter nd scn chins nd it is connected to the multi input sinture reister(misr) from this it is connected to embedded memory from this it is connected to IST[2] controller. Desin Desin U T To Fult Simultion with PRPG TPG T RPR Fults Deterministic ptterns TPG Prtil Mtchin Deterministic ptterns Second Phse of Mixed- Mode Reminin ptterns ontrol sequences Tm- () Improved test Qulity () (b) Improved test Qulity (b) Fi.. Mixed-mode flow In mny of the mixed modes, first the test flow is done by usin PR pttern, fult simultion is performed, nd the RPR fults re identified. Then, deterministic utomtic test pttern enertion (TPG) is used to enerte ptterns for RPR fults. ontroller IST ombintionl loic Embedded Memory Fi. 2. Proposed testin rchitecture. The second phse of the mixed-mode pproch is then pplied tht is deterministic ptterns re pplied to tret reminin fults. In our methodoloy first, deterministic TPG is used. The ptterns re then prtilly mtched. The reminin ptterns re enerted by pplyin control sequence to the LFSR. In our proposed method there re mny dvntes. First, fult simultion is eliminted but it is not in the cse of other mixed modes. Second, the 72 P e

3 .Rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, P.Venkt Gopikumr PG Scholr / Interntionl Journl of Enineerin Reserch nd pplictions (IJER) ISSN: Vol. 2, Issue 5, September- October 22, pp prtil pttern mtchin increses the number of hits nd hence leves fewer number of RPR ptterns to require LFSR control sinls. The shorter the control sequence, the smller the store needed on the chip. In section II, we describe the prtil mtchin scheme. In section III, we describe the multiplecontrol sequence(ms). Simultion results re presented in section IV, synthesis results re presented in section V, nd in section VI, we present our results. 2. PRTIL MTHING To mximize the fult covere, ll specified bits of the deterministic test ptterns hve to be fully mtched by the PR ptterns bein produced by the LFSR. If there re mny specified bits in the test pttern of lon scn chin, but it is difficult for PR pttern to hit ny deterministic ptterns with full pttern mtch. This will result in hue number of test ptterns tht re not covered, this drwbck cn be eliminted in our new prtil mtchin technique which nlyzes the binry S- mtrix. This binry S-mtrix nd utilizes the topoloy of the loic cones. This pproch increses the possibility of ptterns mtchin nd hence reduces the size of the required control sequence. ircuit Modelin Fi. 3 (b) S-rph of desin. o The binry S-mtrix cn be constructed from the S-rph [6] tht is G = (V, E), where V is the set of vertices representin the scn cells in the circuit, E is the set of edes representin connectivity between the scn cells. The first step of the test preprtion is to enerte the binry S-mtrix [6] for the cores. n entry S (i, j) = indictes tht scn cell i is feedin into scn cell j. nd S (I, j) = indictes tht scn cell i is not feedin into scn cell j. Usin the S-mtrix confirms our pproch with respect to testin without revelin IP informtion becuse the S-mtrix is represented by the connectivity of scn cells without ivin structure of the loic circuits. In the similr wy the scn chins cn lso be constricted, in such wy tht the scn cells in the sme scn chin re independent of ech other. The im ws to mke the set of liner equtions, which re necessry for the reseedin of n LFSR. In other words ll the inputs of ny loic cone re lwys in one scn chin but in our pproch where the inputs of loic cone cn be in ny scn chin. desin (c). inry S-mtrix of Fi. 3. () ISS benchmrk circuit S27. Usin Loic ones to Prtition sinle deterministic test pttern enerted by n TPG usully detects more thn one fult in the desire. When the pttern is cptured by the flipflops, the new input of ny flip flop represents the response of pttern for fults within the combintionl circuit cone converin t this flip flop. Loic cones re nothin but loic tes or simply combintionl circuits ech sub pttern corresponds to loic cone of the desin, which my contin multiple fults of the loic tes. For exmple deterministic test pttern expnded into three sub ptterns ech sub pttern detects fults in the correspondin loic cone sub ptterns hve more don t cre bits thn the oriinl pttern. Hence, they re esier to mtch with the PR ptterns then the oriinl deterministic test pttern. Now prtil pttern mtchin technique is to be pplied to the sub ptterns s n enhncement to the full pttern mtchin technique, which hs been pplied to the oriinl deterministic test ptterns. The prtil mtchin technique consists of the followin three steps. Form sub ptterns for ech deterministic pttern usin cone-mskin pproch. Generte the PR test ptterns by simultin the LFSR nd mtch them to sub ptterns. 722 P e

4 Phse shifter.rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, P.Venkt Gopikumr PG Scholr / Interntionl Journl of Enineerin Reserch nd pplictions (IJER) ISSN: Vol. 2, Issue 5, September- October 22, pp ombine the reminin unmtched sub ptterns tht re relted to the ech oriinl deterministic test pttern nd updte the finl set of deterministic test ptterns. pttern counter counts the number of cpture cycles tht occur durin ech test execution phse. U M M X 5 T S U z M X 4 T S X 3 U m- X 2 M m- S m- T m- X Fi. 4. ontrollin the LFSR The oriinl deterministic test ptterns re split in to sub ptterns for ech deterministic test pttern the number of sub ptterns is equl to the number of columns of the S-mtrix tht hve t lest one entry of. The vlue of bit i of sub pttern j is the sme s the vlue of bit i of the deterministic test pttern if nd only if S [i, j] is otherwise it is unspecified bit(x). In this method, there existin phse shifter [4] nd multiple scn chins. There re two test execution phses. Durin the first test phse, the LFSR is freely rn for user specified number of N cycles to enerte PR test ptterns for esily detectble fults. The number of PR test ptterns is the sme s the used in ll cores but with less test ppliction time becuse of multiple scn chins. In the second test phse MSs re used to direct the LFSR to enerte the reminin ptterns to detect the RPR fults. lon with the phse shifter [4] nd multiple scn chins there existin lso IST controller. pttern counter nd bit counter re prt of the IST controller. The bit counter keeps trck of the number of test dt bits bein shifted into scn chins. The TLE I Sub ptterns for deterministic pttern Deterministic Pttern Sub-Ptterns x x x x x x Loic cone The circuit shown in Fi. 3() is the ISS (Interntionl stndrd circuit nd system) benchmrk circuit S27. It cn be represented by the S-rph shown in Fi. 3(b). The correspondin binry S-mtrix is shown in Fi. 3(c). s per our methodoloy first Deterministic TPG is used nd it is found tht s.this deterministic pttern is then split into three sub-ptterns. Ech sub pttern corresponds to loic cone of the desin. Number of loic for the circuit in Fi. 3(), Tble I shown deterministic test pttern (column ) expnded into three sub ptterns. In the circuit fult ws injected t P e

5 .Rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, P.Venkt Gopikumr PG Scholr / Interntionl Journl of Enineerin Reserch nd pplictions (IJER) ISSN: Vol. 2, Issue 5, September- October 22, pp the 3 this fult is not identified by the rndom pttern nd it is detected by deterministic pttern t the.once fter findin the deterministic pttern nd in the fults re injected t the 3, 4 nd these fults re determined by rndom pttern nd those fults which re not covered by rndom pttern re identified by deterministic pttern test enertion. Thus ll the fults will be determined by this method, by pplyin both rndom pttern test enertion nd deterministic pttern test enertion, when s= the controllble LFSR [3] enerte rndom test ptterns nd when s= it will enerte the deterministic test ptterns. the body field S i, nd S i is equl to one the dvnte of MS is to control ny number of scn chin. 4. Simultion results 3. MULTIONTROL SEQUENES IST controller llows the LFSR to freely run for user defined number of cpture cycles N it beins to control the LFSR.The method of deterministic bits presented PRPG reister to feed the LFSR seeds for enertin the desired ptterns in multiple scn chin desin For controllin the LFSR, usin n MS to direct it nd to enerte nd pply the desired deterministic ptterns in multiple scn desin. The MS consists of two vectors U= (U, U, U 2..U m- ) nd S= (S, S, S 2 S m- ). The U vector ws directly injected throuh multiplexers to scn chins. ll multiplexers hve been moved to the front of LFSR to improve both the test time nd test dt volume. Phse shifters structure is bsed on the STUMPS rchitecture, one of the scn chins [5] is directly fed from the left most tp of the LFSR while other chins re fed from the phse shifter ll the ptterns supplied to ech scn chins cn be controlled. For exmple ssume tht four scn chin bein controlled by four tps from the phse shifter deterministic test ptterns indicted on These scn chins re (T, T, T 2, T 3 ) respectively. There re more dvntes in usin multi control to uide the LFSR to feed the tret test dt to the scn chins. In most of the cses only few control sequences in some scn chins hve to be specified while the reminin contents in the scn chne re utomticlly mtched to deterministic ptterns. Therefore the rest of control sequences do not need to be specified. This further reduces the test dt store requirement. The dt formt for the MS consists of two nd fields: heder nd body. The heder specifies the loic vlues for the multiplexer selectors, body holds the MSs U, U U m-. If the deterministic pttern for the ith scns chin consists of only unspecified bits then the correspondin ith control sequence U i is not needed to crete the desires vlues of deterministic ptterns. Therefore, Si is equl to zero, U i cn be skipped from the body field. However even If there is only one specified bit to be controlled in deterministic pttern the correspondin control sequence U i must be include in Fi. 5. Rndom pttern test enertion. Fi. 6. Deterministic test pttern enertion. 724 P e

6 .Rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, P.Venkt Gopikumr PG Scholr / Interntionl Journl of Enineerin Reserch nd pplictions (IJER) ISSN: Vol. 2, Issue 5, September- October 22, pp Fi. 7. S-rph nd S-mtrix. Fi..S-mtrix nd deterministic test pttern enertion. Fi. 8. ISS benchmrk circuit S Synthesis result Fi. 9. Rndom pttern test enertion Fi.. ISS benchmrk circuit S onclusion In conclusion, new pproch tht is mixed-mode IST tht mkes use of prtilmtchin technique to fcilitte the enertion of ptterns for RPR fults. The test ppliction mode uses controllble LFSR for multiple-scn-chin confiurtion. We hve nlyzed the desin throuh the cretion of binry S-mtrix nd the identifiction of loic cones. Then, we hve pplied the prtil pttern mtchin to filter the RPR fults. In ddition, we hve enerted n MS to uide the LFSR to enerte the desired ptterns insted of pplyin the whole deterministic test. the fult covere s hih s intended by the deterministic test, we hve succeeded in reducin both the test dt volume nd the test ppliction time. Moreover, in comprison with [22], both the test sequence lenth nd the hrdwre overhed re much lower. 7. cknowledment P.Venkt GopiKumr would like to thnk.rvishnkr Reddy, who hd been uidin throuh out to complete the work successfully, nd 725 P e

7 .Rvishnkr reddy Lecturer, Dr. V. Sumlth ssocite professor, P.Venkt Gopikumr PG Scholr / Interntionl Journl of Enineerin Reserch nd pplictions (IJER) ISSN: Vol. 2, Issue 5, September- October 22, pp would lso like to thnk the HOD, EE Deprtment nd other Professors for extendin their help & support in ivin technicl ides bout the pper nd motivtin to complete the work effectively & successfully References []. Koenemnn, LFSR-coded test ptterns for scn desins, in Proc. Eur.Test onf., 99, pp [2] E. Kllieros, X. Kvousinos, nd D. Nikolos, Multiphse IST: new reseedin technique for hih test-dt compression, IEEETrns. omput.-ided Desin Inter. ircuits Syst., vol. 23, no.,pp , Oct. 24 [3] D. Ky nd S. Mourd, ontrollble LFSR for built-in self-test, in Proc.IMT, 2, pp [4] J. Rjski nd J. Tyszer, Desin of phse shifters for IST pplictions, in Proc. VTS, 998, pp [5] T. Reunpeerkul, D. Ky, nd S. Mourd, Interctive IST for embeddedcore in SO: Prtil mtchin nd control sequences technique, inproc. IMT, 26, pp [6]. Greene nd S. Mourd, Prtil scn testin on the reister-trnsferlevel, in J. Electron. Test., Theory ppl., Dec. 22, vol. 8, no. 6,pp P e