Memory Management. What to do when coalescing fails. The Need for Relocation. Memory Compaction. Pure Swapping. Why we swap 4/15/2018

Transcription

1 Memory Mngement Wht to do when colescing fils 5H. Memory Compction 6A. Swpping to secondry storge 5E. Dynmic Reloction 6B. Pging Memory Mngement Units 6C. Demnd Pging 6D. Replcement Algorithms 6F. Optimiztions 6H Pging nd Segmenttion 6I. Virtul Memory nd I/O grge collection is just nother wy to free doesn t gretly help or hurt frgmenttion ongoing ctivity cn strve colescing chunks rellocted efore neighors ecome free we could stop ccepting new lloctions convoy on memory mnger would trsh throughput we need wy to rerrnge ctive memory re-pck ll processes in one end of memory crete one ig chunk of free spce t other end Memory mngement 1 Memory mngement 2 Memory Compction P F P D P C P E swp device The Need for Reloction Memory compction moves process from where we originlly loded it to new plce so we cn compct the llocted memory colesce free spce to cure externl frgmenttion But progrm is full of ddresses conditionl rnches, suroutine clls dt ddresses in the code, nd in pointers We cn t find/updte ll of these pointers s we just sw with Grge Collection Memory mngement 3 Why we swp mke est use of limited mount of memory process cn only execute if it is in memory cn t keep ll processes in memory ll the time if it isn't READY, it doesn't need to e in memory swp it out nd mke room for other processes improve CPU utiliztion when there re no READY processes, CPU is idle CPU idle time mens reduced system throughput more READY processes mens etter utiliztion 5 Pure Swpping ech segment is contiguous in memory, nd on secondry storge ll in memory, or ll on swp device swpping tkes gret del of time trnsferring entire dt (nd text) segments swpping wstes gret del of memory processes seldom need the entire segment vrile length memory/disk lloction complex, expensive, externl frgmenttion 6 1

2 The Need for Dynmic Reloction there re few resons to move process needs lrger chunk of memory swpped out, swpped ck in to new loction to compct frgmented free spce ll ddresses in the progrm will e wrong references in the code, pointers in the dt it is not fesile to re-linkge edit the progrm new pointers hve een creted during run-time 0x shred code DLL 1 Virtul Address Trnsltion privte dt privte stck 0xFFFFFFFF physicl ddress spce (s on CPU/memory us) ddress trnsltion unit (mgicl) virtul ddress spce (s seen y process) Memory mngement 7 Memory mngement 8 Segment Reloction nturl unit of lloction nd reloction process ddress spce mde up of segments ech segment is contiguous w/no holes CPU hs segment se registers point to (physicl memory) se of ech segment CPU utomticlly reloctes ll references OS uses for virtul ddress trnsltion set se to region where segment is loded efficient: CPU cn relocte every reference trnsprent: ny segment cn move nywhere 0x shred code DLL 1 Segment Reloction virtul ddress spce privte dt privte stck 0xFFFFFFFF code se register dt se register ux se register stck se register physicl memory physicl = virtul + se seg stck code dt DLL Memory mngement 9 Memory mngement 10 0x shred code privte dt Moving Segment The virtul ddress of the stck doesn t chnge DLL 1 DLL 2 DLL 3 code se register ux se register privte stck 0xFFFFFFFF dt se register stck se register physicl = virtul + se seg We just chnge the vlue in the stck se register Let s sy we need to move the stck in physicl memory code stck Physiclmemory DLL dt Privcy nd Protection confine process to its own ddress spce ech segment lso hs length/limit register CPU verifies ll offsets re within rnge genertes ddressing exception if not protecting red-only segments ssocite red/write ccess with ech segment CPU ensures integrity of red-only segments segmenttion register updte is privileged only kernel-mode code cn do this Memory mngement 12 2

3 Are Segments the Answer? very nturl unit of ddress spce vrile length, contiguous dt los ll-or-none with uniform r/w or r/o ccess convenient/powerful virtul ddress strction ut they re vrile length they require contiguous physicl memory ultimtely leding to externl frgmenttion requiring expensive swpping for compction nd in tht moment he ws enlightened pged ddress trnsltion process virtul ddress spce CODE DATA STACK physicl memory Memory mngement Pging nd Frgmenttion Pging Memory Mngement Unit virtul ddress physicl ddress pge # offset pge # offset segment is implemented s set of virtul pges internl frgmenttion verges only ½ pge (hlf of the lst one) externl frgmenttion completely non-existent (we never crve up pges) virtul pge # is used s n index into the pge tle vlid it is checked to ensure tht this virtul pge # is legl. V pge # V pge # V pge # 0 V pge # 0 V pge # V pge # pge tle offset within pge remins the sme. selected entry contins physicl pge numer Pging Reloction Exmples Swpping is Wsteful virtul ddress physicl ddress C08 3E C20 041F 1C pge fult V V V 0C A1 0 V 041F 0 V V 0D10 0AC3 pge tle process does not use ll its pges ll the time code nd dt oth exhiit reference loclity some code/dt my seldom e used keeping ll pges in memory wstes spce more spce/process = fewer processes in memory swpping them ll in nd out wstes time longer trnsfers, longer wits for disk it ritrrily limits the size of process process must e smller thn ville memory

4 Loding Pges On Demnd Pge Fult Hndling pging MMU supports not present pges CPU ccess of present pges proceeds normlly ccessing not present pge genertes trp operting system cn process this pge fult recognize tht it is request for nother pge red tht pge in nd resume process execution entire process needn t e in memory to run strt ech process with suset of its pges lod dditionl pges s progrm demnds them initilize pge tle entries to not present CPU fults when invlid pge is referenced 1. trp forwrded to pge fult hndler 2. determine which pge, where it resides 3. find nd llocte free pge frme 4. lock process, schedule I/O to red pge in 5. updte pge tle point t newly red-in pge 6. ck up user-mode PC to retry filed instruction 7. unlock process, return to user-mode Menwhile, other processes cn run Demnd Pging dvntges improved system performnce fewer in-memory pges per process more processes in primry memory more prllelism, etter throughput etter response time for processes lredy in memory less time required to pge processes in nd out less disk I/O mens reduced queuing delys fewer limittions on process size process cn e lrger thn physicl memory process cn hve huge (sprse) virtul spce Are Pge Fults Prolem? Pge fults should not ffect correctness fter fult is hndled, desired pge is in RAM process runs gin, nd cn now use tht pge (ssuming the OS properly sves/restores stte) But progrms might run veryslowly dditionl context switches wste ville CPU dditionl disk I/O wstes ville throughput processes re delyed witing for needed pges We must minimize the numer of pge fults 21 Minimizing Numer of Pge Fults There re two wys: keep the right pges in memory give process more pges of memory How do we keep right pges in memory? we hve no control over wht pges we ring in ut we cn decide which pges to evict this is clled replcement strtegy How mny pges does process need? tht depends on which process nd when this is clled the process working set Beldy's Optiml Algorithm Q: which pge should we replce? A: the one we won't need for the longest time Why is this the right pge? it delys the next pge fult s long s possile minimum numer of pge fults per unit time How cn we predict future references? Beldycnnot e implemented in rel system ut we cn run implement it for test dt strems we cn compre other lgorithms ginst it

5 Do we need n Optiml lgorithm? Be very cler on wht our gol is we re not trying minimize the # of pge fults we re trying to minimize the cost of pging TANSTAAFL we py price for every pge fult we lso py for every replcement decision some decisions re more expensive thn fults we must do cost/enefit nlysis Approximting Optiml Replcement note which pges hve recently een used use this dt to predict future ehvior Possile replcement lgorithms rndom, FIFO: strw-men... forget them Lest Recently Used ssert ner future will e like recent pst progrms do exhiit temporl nd sptil loclity if we hven t used it recently, we proly won t soon we don t hve to e right 100% of the time the more right we re, the more pge fults we sve Why Progrms Exhiit Loclity Code loclity code in sme routine is in sme/djcent pge loops iterte over the sme code few routines re clled repetedly intr-module clls re common Stck loclity ctivity focuses on this nd djcent cll frmes Dt reference loclity this is common, ut not ssured True LRU is hrd to implement mintin this informtion in the MMU? MMU notes the time, every time pge is referenced mye we cn get per-pge red/written it mintin this informtion in softwre? mrk ll pges invlid, even if they re in memory tke fult the first time ech pge is referenced then mrk this pge vlid for the rest of the time slice finding oldest pge is prohiitively expensive 16GB memory / 4K pge = 4M pges to scn Prcticl LRU surrogtes True Glol LRU Replcement must e chep cn t cuse dditionl pge fults void scnning the whole pge tle (it is ig) clock lgorithms surrogte for LRU orgnize ll pges in circulr list position round the list is surrogte for ge progressive scn whenever we need nother pge for ech pge, sk MMU if pge hs een referenced if so, reset the reference it in the MMU; skip pge if not, consider this pge to e the lest recently used 29 reference True LRU frme 0 frme 1 frme 2 frme 3 c d d e f c d e d lods 4, replcements 7! f d!!! c e c d! e 30 5

6 LRU Clock Algorithm Working Sets per process LRU reference LRU clock frme 0 frme 1 frme 2 frme 3 clock pos True LRU frme 0 frme 1 frme 2 frme 3 c d d e f c d e d lods 4, replcements 7! c d!!! f d!!!!!! e e!!! c lods 4, replcements 7 f d d c e c d d e E 2 Glol LRU is proly lunder d interction with round-roin scheduling etter to give ech process it's own pge pool do LRU replcement within tht pool fixed # of pges per process is lso d different processes exhiit different loclity which pges re needed chnges over time numer of pges needed chnges over time much like different nturl scheduling intervls we clerly wnt dynmic working sets nturl working set size (Optiml Working Sets) numer of pge fults thrshing in insufficient spce It cn t e done! the sweet spot working set size little mrginl enefit for dditionl spce More, is just more. Wht is optiml working set for process? numer of pges needed during next time slice wht if try to run process in fewer pges? needed pges replce one nother continuously this is clled "thrshing" how cn we know wht working set size is? y oserving the process ehvior which pges should e in the working-set? no need to guess, the process will fult for them Implementing Working Sets Working Set Clock Algorithm mnged working set size ssign pge frmes to ech in-memory process processes pge ginst themselves in working set oserve pging ehvior (fults per unit time) djust numer of ssigned pge frmes ccordingly pge steling (WS-Clock) lgorithms trck lst use time for ech pge, for owning process find pge lest recently used (y its owner) processes tht need more pges tend to get more processes tht don't use their pges tend to lose them pge frme referenced process lst ref clock ptr P 0 P 0 P 1 P 2 P 2 P 1 P 1 P 0 P 2 P 0 P 1 P 2 P 0 P 1 P current execution times P 0 = 55 P 1 = 75 P 2 = 80 P 0 gets fult pge 6 ws just referenced cler ref it, updte time pge 7 is (55-33=22) ms old P 0 replces his own pge t =

7 Working Set Clock Algorithm Thrshing Prevention pge frme referenced process lst ref clock ptr P 0 P 0 P 1 P 2 P 2 P 1 P 1 P 0 P 2 P 0 P 10 P 2 P 0 P 1 P current execution times P 0 = 55 P 1 = 75 P 2 = 80 P 0 gets fult pge 6 ws just referenced pge 7 is (55-33=22) ms old P 0 replces his own pge t = 25 P 0 gets fult pge 6 ws just referenced pge 7 is (55-33=22) ms old pge 8 is (80-72=8) ms old pge 9 is (55-54=1) ms old pge 10 is (75-23=52) ms old P 0 stels this pge from P 1 E 7 working set size chrcterizes ech process how mny pges it needs to run for τmilliseconds Wht if we don t hve enough memory? sum of our working sets exceeds ville memory we cnnot squeeze working set sizes this will result in thrshing reduce numer of competing processes swp some of the redyprocesses out to ensure enough memory for the rest to run we cn round-roin who is in nd out Pre-loding pge/swp hyrid Clen nd Dirty Pges wht hppens when process swps in pure swpping ll pges present efore process is run, no pge fults pure demnd pging pges re only rought in s needed fewer pges per process, more processes in memory wht if we pre-lod the lst working set? fr fewer pges to e red in thn swpping prolythe sme disk reds s pure demnd pging fr fewer initil pge fults thn pure demnd pging consider pge, recently pged in from disk there re two copies, on on disk, one in memory if the in-memory copy hs not een modified there is still vlid copy on disk the in-memory copy is sid to e "clen" we cn replce pge without writing it ck to disk if the in-memory copy hs een modified the copy on disk is no longer up-to-dte the in-memory copy is sid to e "dirty" if we write it out to disk, it ecomes "clen" gin preemptive pge lundering Copy on Write clen pges cn e replced t ny time copy on disk is lredy up to dte clen pges give flexiility to memory scheduler mny pges tht cn, if necessry, e replced ongoing ckground write-out of dirty pges find nd write-out ll dirty, non-running pges no point in writing out pge tht is ctively in use on ssumption we will eventully hve to pge out mke them clen gin, ville for replcement this is the outgoing equivlent of pre-loding fork(2) is very expensive opertion we must copy ll privte dt/stck pges sdly most will e discrded y next exec(2) ssume child will not updte most pges shre ll privte pges, mrk them copy on write chnge them to e red-only for prent nd child on write-pge fult, mke copy of tht pge on exec, remining pges ecome privte gin copy on write is common optimiztion

8 pging nd segmenttion segmenttion on top of pging pges re very nice memory lloction unit they eliminte internl nd externl frgmenttion they dmit of very simple nd powerful MMU they re not prticulrly nturl unit of dt progrms re comprised of, nd operte on, segments segments re the nturl chunks of virtul ddress spce e.g. we mp new segment into the virtul ddress spce ech code, dt, stck segment contins mny pges two levels of memory mngement strction virtul ddress spce is comprised of segments reloction & swpping is done on pge sis segment se ddressing, with pge sed reloction user processes see segments, pging is invisile segment se registers cs ds es ss process virtul ddress spce Segments collections of pges segment is nmed collection of pges ech pge hs home on secondry storge opertions on segments: crete/open/destroy mp/unmp segment to/from process find physicl pge numer of virtul pge n connection etween pging & segmenttion segment mpping implemented w/pge mpping pge fulting uses segments to find requested pge B 1 Mnging Secondry Storge where do pges live when not in memory? we swp them out to secondry storge (disk) how do we mnge our swp spce? s pool of vrile length prtitions? D llocte contiguous region for ech process 2 s rndom collection of pges? just use it-mp to keep trck of which re free s file system? crete file per process (or segment) file offsets correspond to virtul ddress offsets Pging nd Shred Segments Virtul Memory nd I/O shred memory, executles nd DLLs creted/mnged s mpple segments one copy mpped into multiple processes demnd pging sme s with ny other pges 2ndry home my e in file system shred pges don't fit working set model my not e ssocited with just one process glol LRU my e more pproprite shred pges often need/get specil hndling F 4 user I/O requests use virtul uffer ddress how cn device controller find tht dt kernel cn copy dt into physicl uffers ccessing user dt through stndrd mechnismsg 1 kernel my trnslte virtul to physicl give device the corresponding physicl ddress CPU my include n I/O MMU use pge tles to trnslte virtddrsto phys ll DMA I/O references go through the I/O MMU

9 Sctter/Gther I/O gther writes from pged memory mny controllers support DMA trnsfers entire trnsfer must e contiguous in physicl memory user uffers re in pged virtul memory user uffer my e spred ll over physicl memory sctter: red from device to multiple pges gther: writing from multiple pges to device sme three sic pproches pply copy ll user dt into contiguous physicl uffer split logicl req into chin-scheduled pge requests I/O MMU my utomticlly hndle sctter/gther process virtul ddress spce physicl memory DMA I/O strem user I/O uffer sctter reds into pged memory Kernel Spce vs. User Spce process virtul ddress spce physicl memory DMA I/O strem user I/O uffer user spce multiple segments: code, dt, stck, DLLs segments re llocted in one-pge units dt spce mnged s hep y user-mode code Kernel spce (my e virtul or physicl) lso includes ll system code nd dt structures lso includes mpped I/O spce physicl memory divided into two clsses most mnged s pges, for use y processes some mnged s storge hep for kernel lloction Typicl Kernel Virtul Address Spce user mode virtul ddress spce In kernel mode the second hlf of the virtul ddress spce ecomes ccessile. stck user code DLL DLL kernel code user dt ll of physicl memory Not to Scle (density is gretly exggerted) user stck I/O spce Moving Dt etween Kernel/User kernel often needs to ccess user dt to ccess system cll prmeters to perform red nd write system clls kernel my run in virtul ddress spce which includes current process' ddress spce specil instructions for cross-spce ccess e.g. "move from previous dt" kernel my execute w/physicl ddresses softwre trnsltion of user-spce ddresses

10 Assignments For next Lecture Introduction to IPC send(2), recv(2), nmed pipes, mmp(2) Arpci C25, 26, user-mode threds Project try to get P1B working efore l order your BegleBone Supplementry Slides Memory mngement 55 implementing pging MMU MMUs used to sit etween the CPU nd us now they re typiclly integrted into the CPU pge tles originlly implemented in specil fst registers now, w/lrger ddress spces, stored in memory entries cched in veryfst registers s they re used which mkes cche invlidtion n issue optionl fetures red/write ccess control, referenced/dirty its seprte pge tles for ech processor mode updting pging MMU dding/removing pges for current process directly updte ctive pge tle in memory privileged instruction to flush (stle) cched entries switching from one process to nother mintin seprte pge tles for ech process privileged instruction lods pointer to new pge tle relod instruction flushes previously cched entries shring pges etween multiple processes mke ech pge tle point to sme physicl pge cn e red-only or red/write shring Discussion Slides 10