What to do when coalescing fails. The Need for Relocation. Memory Compaction. Why we swap. Pure Swapping 4/14/2017. Virtual Memory and Demand Paging

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1 Wht to o when olesing fils 5H. Memory Comption 6A. Swpping to Seonry Storge 5E. Dynmi Relotion 6B. Pging Memory Mngement Units 6C. Demn Pging 6D. Replement Algorithms 6E. Thrshing n Working Sets 6F. Pging Optimiztions 6H. Pging n Segmenttion 6I. Virtul Memory n I/O grge olletion is just nother wy to free oesn t gretly help or hurt frgmenttion ongoing tivity n strve olesing hunks rellote efore neighors eome free we oul stop epting new llotions onvoy on memory mnger woul trsh throughput we nee wy to rerrnge tive memory re-pk ll proesses in one en of memory rete one ig hunk of free spe t other en 1 2 Memory Comption P F P D P C P E swp evie The Nee for Relotion Memory omption moves proess from where we originlly loe it to new ple so we n ompt the llote memory olese free spe to ure externl frgmenttion But progrm is full of resses onitionl rnhes, suroutine lls t resses in the oe, n in pointers We n t fin/upte ll of these pointers s we just sw with Grge Colletion 3 4 Why we swp mke est use of limite mount of memory proess n only exeute if it is in memory n t keep ll proesses in memory ll the time if it isn't READY, it oesn't nee to e in memory swp it out n mke room for other proesses improve CPU utiliztion when there re no READY proesses, CPU is ile CPU ile time mens reue system throughput more READY proesses mens etter utiliztion 5 Pure Swpping eh segment is ontiguous in memory, n on seonry storge ll in memory, or ll on swp evie swpping tkes gret el of time trnsferring entire t (n text) segments swpping wstes gret el of memory proesses selom nee the entire segment vrile length memory/isk llotion omplex, expensive, externl frgmenttion 6 1

2 The Nee for Dynmi Relotion there re few resons to move proess nees lrger hunk of memory swppe out, swppe k in to new lotion to ompt frgmente free spe ll resses in the progrm will e wrong referenes in the oe, pointers in the t it is not fesile to re-linkge eit the progrm new pointers hve een rete uring run-time 0x shre oe DLL 1 Virtul Aress Trnsltion privte t privte stk 0xFFFFFFFF physil ress spe (s on CPU/memory us) ress trnsltion unit (mgil) virtul ress spe (s seen y proess) 7 8 Segment Relotion nturl unit of llotion n relotion proess ress spe me up of segments eh segment is ontiguous w/no holes CPU hs segment se registers point to (physil memory) se of eh segment CPU utomtilly relotes ll referenes OS uses for virtul ress trnsltion set se to region where segment is loe effiient: CPU n relote every referene trnsprent: ny segment n move nywhere 0x shre oe DLL 1 Segment Relotion virtul ress spe privte t privte stk 0xFFFFFFFF oe se register t se register ux se register stk se register physil memory physil = virtul + se seg stk oe t DLL x shre oe privte t DLL 1 DLL 2 DLL 3 Moving Segment The virtul ress of the stk oesn t hnge oe se register ux se register privte stk 0xFFFFFFFF t se register stk se register physil = virtul + se seg We just hnge the vlue in the stk se register Let s sy we nee to move the stk in physil memory oe stk Physilmemory DLL t 11 Privy n Protetion onfine proess to its own ress spe eh segment lso hs length/limit register CPU verifies ll offsets re within rnge genertes ressing exeption if not proteting re-only segments ssoite re/write ess with eh segment CPU ensures integrity of re-only segments segmenttion register upte is privilege only kernel-moe oe n o this 12 2

3 Are Segments the Answer? very nturl unit of ress spe vrile length, ontiguous t los ll-or-none with uniform r/w or r/o ess onvenient/powerful virtul ress strtion ut they re vrile length they require ontiguous physil memory ultimtely leing to externl frgmenttion requiring expensive swpping for omption n in tht moment he ws enlightene pge ress trnsltion proess virtul ress spe CODE DATA STACK physil memory Pging n Frgmenttion Pging Memory Mngement Unit virtul ress physil ress pge # offset pge # offset segment is implemente s set of virtul pges internl frgmenttion verges only ½ pge (hlf of the lst one) externl frgmenttion ompletely non-existent (we never rve up pges) virtul pge # is use s n inex into the pge tle vli it is heke to ensure tht this virtul pge # is legl. V pge # V pge # V pge # 0 V pge # 0 V pge # V pge # pge tle offset within pge remins the sme. selete entry ontins physil pge numer Pging Relotion Exmples virtul ress physil ress C08 3E C20 041F 1C pge fult V 0C20 V 0105 V 00A1 0 V 041F 0 V 0D10 V 0AC3 pge tle Supplementry Slies 17 3

4 implementing pging MMU MMUs use to sit etween the CPU n us now they re typilly integrte into the CPU pge tles originlly implemente in speil fst registers now, w/lrger ress spes, store in memory entries he in very fst registers s they re use whih mkes he invlition n issue optionl fetures re/write ess ontrol, referene/irty its seprte pge tles for eh proessor moe upting pging MMU ing/removing pges for urrent proess iretly upte tive pge tle in memory privilege instrution to flush (stle) he entries swithing from one proess to nother mintin seprte pge tles for eh proess privilege instrution los pointer to new pge tle relo instrution flushes previously he entries shring pges etween multiple proesses mke eh pge tle point to sme physil pge n e re-only or re/write shring Swpping is Wsteful Loing Pges On Demn proess oes not use ll its pges ll the time oe n t oth exhiit referene lolity some oe/t my selom e use keeping ll pges in memory wstes spe more spe/proess = fewer proesses in memory swpping them ll in n out wstes time longer trnsfers, longer wits for isk it ritrrily limits the size of proess proess must e smller thn ville memory pging MMU supports not present pges CPU ess of present pges proees normlly essing not present pge genertes trp operting system n proess this pge fult reognize tht it is request for nother pge re tht pge in n resume proess exeution entire proess neen t e in memory to run strt eh proess with suset of its pges lo itionl pges s progrm emns them Pge Fult Hnling initilize pge tle entries to not present CPU fults when invli pge is referene 1. trp forwre to pge fult hnler 2. etermine whih pge, where it resies 3. fin n llote free pge frme 4. lok proess, sheule I/O to re pge in 5. upte pge tle point t newly re-in pge 6. k up user-moe PC to retry file instrution 7. unlok proess, return to user-moe Menwhile, other proesses n run Demn Pging vntges improve system performne fewer in-memory pges per proess more proesses in primry memory more prllelism, etter throughput etter response time for proesses lrey in memory less time require to pge proesses in n out less isk I/O mens reue queuing elys fewer limittions on proess size proess n e lrger thn physil memory proess n hve huge (sprse) virtul spe

5 Are Pge Fults Prolem? Pge fults shoul not ffet orretness fter fult is hnle, esire pge is in RAM proess runs gin, n n now use tht pge (ssuming the OS properly sves/restores stte) But progrms might run veryslowly itionl ontext swithes wste ville CPU itionl isk I/O wstes ville throughput proesses re elye witing for neee pges We must minimize the numer of pge fults Minimizing Numer of Pge Fults There re two wys: keep the right pges in memory give proess more pges of memory How o we keep right pges in memory? we hve no ontrol over wht pges we ring in ut we n eie whih pges to evit this is lle replement strtegy How mny pges oes proess nee? tht epens on whih proess n when this is lle the proess working set Bely's Optiml Algorithm Do we nee n Optiml lgorithm? Q: whih pge shoul we reple? A: the one we won't nee for the longest time Why is this the right pge? it elys the next pge fult s long s possile minimum numer of pge fults per unit time How n we preit future referenes? Belynnot e implemente in rel system ut we n run implement it for test t strems we n ompre other lgorithms ginst it Be very ler on wht our gol is we re not trying minimize the # of pge fults we re trying to minimize the ost of pging TANSTAAFL we py prie for every pge fult we lso py for every replement eision some eisions re more expensive thn fults we must o ost/enefit nlysis Approximting Optiml Replement note whih pges hve reently een use use this t to preit future ehvior Possile replement lgorithms rnom, FIFO: strw-men... forget them Lest Reently Use ssert ner future will e like reent pst progrms o exhiit temporl n sptil lolity if we hven t use it reently, we proly won t soon we on t hve to e right 100% of the time the more right we re, the more pge fults we sve Why Progrms Exhiit Lolity Coe lolity oe in sme routine is in sme/jent pge loops iterte over the sme oe few routines re lle repetely intr-moule lls re ommon Stk lolity tivity fouses on this n jent ll frmes Dt referene lolity this is ommon, ut not ssure

6 True LRU is hr to implement mintin this informtion in the MMU? MMU notes the time, every time pge is referene mye we n get per-pge re/written it mintin this informtion in softwre? mrk ll pges invli, even if they re in memory tke fult the first time eh pge is referene then mrk this pge vli for the rest of the time slie fining olest pge is prohiitively expensive 16GB memory / 4K pge = 4M pges to sn Prtil LRU surrogtes must e hep n t use itionl pge fults voi snning the whole pge tle (it is ig) lok lgorithms surrogte for LRU orgnize ll pges in irulr list position roun the list is surrogte for ge progressive sn whenever we nee nother pge for eh pge, sk MMU if pge hs een referene if so, reset the referene it in the MMU; skip pge if not, onsier this pge to e the lest reently use True Glol LRU Replement LRU Clok Algorithm referene e f e referene True LRU frme 0 frme 1 frme 2 frme 3 e f e los 4, replements 7 f e e LRU lok frme 0 frme 1 frme 2 frme 3 lok pos True LRU los 4, replements 7 f e e los 4, replements 7 E 2 frme 0 frme 1 frme 2 frme 3 e f e Working Sets per proess LRU nturl working set size Glol LRU is proly luner intertion with roun-roin sheuling etter to give eh proess it's own pge pool o LRU replement within tht pool fixe # of pges per proess is lso ifferent proesses exhiit ifferent lolity whih pges re neee hnges over time numer of pges neee hnges over time muh like ifferent nturl sheuling intervls we lerly wnt ynmi working sets numer of pge fults thrshing in insuffiient spe It n t e one the sweet spot working set size little mrginl enefit for itionl spe More, is just more

7 (Optiml Working Sets) Wht is optiml working set for proess? numer of pges neee uring next time slie wht if try to run proess in fewer pges? neee pges reple one nother ontinuously this is lle "thrshing" how n we know wht working set size is? y oserving the proess ehvior whih pges shoul e in the working-set? no nee to guess, the proess will fult for them Implementing Working Sets mnge working set size ssign pge frmes to eh in-memory proess proesses pge ginst themselves in working set oserve pging ehvior (fults per unit time) just numer of ssigne pge frmes oringly pge steling (WS-Clok) lgorithms trk lst use time for eh pge, for owning proess fin pge lest reently use (y its owner) proesses tht nee more pges ten to get more proesses tht on't use their pges ten to lose them Working Set Clok Algorithm Working Set Clok Algorithm pge frme pge frme referene referene proess P 0 P 0 P 1 P 2 P 2 P 1 P 1 P 0 P 2 P 0 P 1 P 2 P 0 P 1 P 2 proess P 0 P 0 P 1 P 2 P 2 P 1 P 1 P 0 P 2 P 0 P 10 P 2 P 0 P 1 P 2 lst ref lst ref lok ptr urrent exeution times P 0 = 55 P 1 = 75 P 2 = 80 t = 15 lok ptr urrent exeution times P 0 = 55 P 1 = 75 P 2 = 80 t = 25 P 0 gets fult pge 6 ws just referene ler ref it, upte time pge 7 is (55-33=22) ms ol P 0 reples his own pge P 0 gets fult pge 6 ws just referene pge 7 is (55-33=22) ms ol P 0 reples his own pge P 0 gets fult pge 6 ws just referene pge 7 is (55-33=22) ms ol pge 8 is (80-72=8) ms ol pge 9 is (55-54=1) ms ol pge 10 is (75-23=52) ms ol P 0 stels this pge from P 1 E Thrshing Prevention Pre-loing pge/swp hyri working set size hrterizes eh proess how mny pges it nees to run for τmilliseons Wht if we on t hve enough memory? sum of our working sets exees ville memory we nnot squeeze working set sizes this will result in thrshing reue numer of ompeting proesses swp some of the reyproesses out to ensure enough memory for the rest to run we n roun-roin who is in n out wht hppens when proess swps in pure swpping ll pges present efore proess is run, no pge fults pure emn pging pges re only rought in s neee fewer pges per proess, more proesses in memory wht if we pre-lo the lst working set? fr fewer pges to e re in thn swpping prolythe sme isk res s pure emn pging fr fewer initil pge fults thn pure emn pging

8 Clen n Dirty Pges onsier pge, reently pge in from isk there re two opies, on on isk, one in memory if the in-memory opy hs not een moifie there is still vli opy on isk the in-memory opy is si to e "len" we n reple pge without writing it k to isk if the in-memory opy hs een moifie the opy on isk is no longer up-to-te the in-memory opy is si to e "irty" if we write it out to isk, it eomes "len" gin preemptive pge lunering len pges n e reple t ny time opy on isk is lrey up to te len pges give flexiility to memory sheuler mny pges tht n, if neessry, e reple ongoing kgroun write-out of irty pges fin n write-out ll irty, non-running pges no point in writing out pge tht is tively in use on ssumption we will eventully hve to pge out mke them len gin, ville for replement this is the outgoing equivlent of pre-loing Copy on Write fork(2) is very expensive opertion we must opy ll privte t/stk pges sly most will e isre y next exe(2) ssume hil will not upte most pges shre ll privte pges, mrk them opy on write hnge them to e re-only for prent n hil on write-pge fult, mke opy of tht pge on exe, remining pges eome privte gin opy on write is ommon optimiztion pging n segmenttion pges re very nie memory llotion unit they eliminte internl n externl frgmenttion they mit of very simple n powerful MMU they re not prtiulrly nturl unit of t progrms re omprise of, n operte on, segments segments re the nturl hunks of virtul ress spe e.g. we mp new segment into the virtul ress spe eh oe, t, stk segment ontins mny pges two levels of memory mngement strtion virtul ress spe is omprise of segments relotion & swpping is one on pge sis segment se ressing, with pge se relotion user proesses see segments, pging is invisile segmenttion on top of pging segment se registers s s es ss proess virtul ress spe Segments olletions of pges segment is nme olletion of pges eh pge hs home on seonry storge opertions on segments: rete/open/estroy mp/unmp segment to/from proess fin physil pge numer of virtul pge n onnetion etween pging & segmenttion segment mpping implemente w/pge mpping pge fulting uses segments to fin requeste pge B

9 Mnging Seonry Storge where o pges live when not in memory? we swp them out to seonry storge (isk) how o we mnge our swp spe? s pool of vrile length prtitions? D llote ontiguous region for eh proess 2 s rnom olletion of pges? just use it-mp to keep trk of whih re free s file system? rete file per proess (or segment) file offsets orrespon to virtul ress offsets Pging n Shre Segments shre memory, exeutles n DLLs rete/mnge s mpple segments one opy mppe into multiple proesses emn pging sme s with ny other pges 2nry home my e in file system shre pges on't fit working set moel my not e ssoite with just one proess glol LRU my e more pproprite shre pges often nee/get speil hnling F Virtul Memory n I/O Stter/Gther I/O user I/O requests use virtul uffer ress how n evie ontroller fin tht t kernel n opy t into physil uffers essing user t through stnr mehnismsg 1 kernel my trnslte virtul to physil give evie the orresponing physil ress CPU my inlue n I/O MMU use pge tles to trnslte virtrsto phys ll DMA I/O referenes go through the I/O MMU mny ontrollers support DMA trnsfers entire trnsfer must e ontiguous in physil memory user uffers re in pge virtul memory user uffer my e spre ll over physil memory stter: re from evie to multiple pges gther: writing from multiple pges to evie sme three si pprohes pply opy ll user t into ontiguous physil uffer split logil req into hin-sheule pge requests I/O MMU my utomtilly hnle stter/gther gther writes from pge memory stter res into pge memory proess virtul ress spe user I/O uffer proess virtul ress spe user I/O uffer physil memory physil memory DMA I/O strem DMA I/O strem

10 Kernel Spe vs. User Spe user spe multiple segments: oe, t, stk, DLLs segments re llote in one-pge units t spe mnge s hep y user-moe oe Kernel spe (my e virtul or physil) lso inlues ll system oe n t strutures lso inlues mppe I/O spe physil memory ivie into two lsses most mnge s pges, for use y proesses some mnge s storge hep for kernel llotion 55 Typil Kernel Virtul Aress Spe user moe virtul ress spe In kernel moe the seon hlf of the virtul ress spe eomes essile. stk user oe DLL DLL kernel oe user t ll of physil memory Not to Sle (ensity is gretly exggerte) user stk I/O spe 56 Moving Dt etween Kernel/User kernel often nees to ess user t to ess system ll prmeters to perform re n write system lls kernel my run in virtul ress spe whih inlues urrent proess' ress spe speil instrutions for ross-spe ess e.g. "move from previous t" kernel my exeute w/physil resses softwre trnsltion of user-spe resses Assignments Projets get remote terminl server working strt plying with enryption lirry Reing Introution to Inter-Proess Communition sen(2), rev(2), mmp(2), nme pipes User Moe Thres AD 25 (introution to synhroniztion) AD 26 (thres n res) AD (thre APIs) Supplementry Slies Primry n Seonry Storge primry = min (exeutle) memory primry storge is expensive n very limite only proesses in primry storge n e run seonry = non-exeutle (e.g. Disk/SSD) loke proesses n e move to seonry storge swp out oe, t, stk n non-resient ontext mke room in primry for other "rey" proesses returning to primry memory proess is opie k when it eomes unloke 60 10

11 sheuling sttes with swpping loke swp out exit request swppe out running llote llote swp wit swp in rete rey Mnging Seonry Storge where o pges live when not in memory? we swp them out to seonry storge (isk) how o we mnge our swp spe? s pool of vrile length prtitions? D llote ontiguous region for eh proess 2 s rnom olletion of pges? just use it-mp to keep trk of whih re free s file system? rete file per proess (or segment) file offsets orrespon to virtul ress offsets